A system and method for improving digital predistortion of shortwave intermodulation and harmonic distortion

Abstract

The present invention aims to address the problem that existing digital pre-distortion methods for improving shortwave power amplifier distortion can only improve the intermodulation distortion of shortwave power amplifiers, have no ability to suppress harmonic distortion, and cannot improve the overall performance of shortwave power amplifiers. Instead, the present invention provides a system and method for improving shortwave intermodulation and harmonic distortion. This method, based on the integration of a cross-memory polynomial pre-distortion model and targeting the characteristics of shortwave signal formats and the memory effect of shortwave power amplifiers, further adopts an FIR structure in the model and utilizes its low-pass filtering characteristics to suppress higher-order harmonics in the octave of the shortwave power amplifier, while improving intermodulation and harmonic suppression, and extracting pre-distortion parameters with a higher degree of consistency, thereby improving the performance of the digital pre-distortion system.

Description

Technical Field

[0001] The present invention relates to an adaptive digital predistortion technology, and more specifically to a system and method for simultaneously improving the intermodulation distortion and harmonic distortion of a shortwave power amplifier. The system and method are suitable for improving the efficiency of a shortwave radio frequency power amplifier and reducing the design requirements for a filter group cascaded at the output end of a shortwave transmitter power amplifier. Background Art

[0002] Radio frequency waves between 1.6MHz and 30MHz are commonly referred to as the shortwave band. Shortwave communications rely primarily on reflection and refraction between the ionosphere and the ground, allowing them to travel great distances, day or night. With the continuous advancement of computers, microelectronics, and wireless communications, shortwave communication technology has made breakthroughs, playing a more important and extensive role in emergency communications, disaster relief communications, and, in particular, in unified communications and command for land, sea, and air forces, as required by the military.

[0003] Currently, shortwave radio is becoming increasingly digital, and its operating frequency band is no longer limited to the original shortwave frequency range, thus adopting multi-band and multi-channel characteristics. This digitization of shortwave radio places increasingly stringent demands on the performance of shortwave power amplifiers. Specifically, the amplifiers must meet high linearity requirements while also achieving high efficiency. To achieve this, amplifiers must be both linear and efficient. Various methods, including predistortion technology, are employed to achieve both high efficiency and high linearity. Predistortion technology also utilizes adaptive principles to track and compensate for errors in the power amplifier caused by environmental factors such as temperature and humidity. In short, predistortion technology not only improves transmitter efficiency, reduces cost, and reduces size, but also effectively increases transmitter linearity, enhancing system performance and communication quality. This technology holds significant practical significance for the future development and implementation of high-efficiency shortwave radio.

[0004] However, due to the unique characteristics of shortwave power amplifiers (SWPAs), predistortion technology faces new challenges in improving their linearity and efficiency. First, compared to power amplifiers in wireless cellular mobile communication systems, SWPAs have a larger fractional bandwidth. The performance of the power tubes varies significantly across the operating frequency range, making it impossible to achieve ideal impedance matching across the entire operating frequency band, which in turn impacts the PA's performance. Furthermore, because their low-frequency harmonics fall within the high-frequency band, eliminating them across all frequencies with a single low-pass filter is impossible. This necessitates segmenting the currently used analog harmonic filters. These filters, however, have limited switching relay lifespans, and their bulkiness, especially at high power levels, makes them susceptible to burnout. Furthermore, current analog filtering technology struggles to achieve a large attenuation resistance band, limiting harmonic suppression performance.

[0005] From the above analysis, it can be seen that the design of short-wave power amplifiers has many problems, such as wide operating frequency bandwidth, large low-frequency harmonic interference, large high-frequency band, large output port standing wave, high power tube temperature, and large leakage voltage fluctuation. These problems make it difficult for traditional pre-distortion technology to achieve the expected performance when applied to high-frequency power amplifiers.

[0006] Chinese patent CN111064439A, titled "A system and method for improving shortwave digital predistortion performance," discloses a system and method for improving shortwave digital predistortion performance. Aiming at the narrow bandwidth of shortwave signals, the weak nonlinear filter of the FIR filter is integrated to overcome the memory effect, and the memory polynomial model is integrated to extract predistortion parameters with a higher degree of fit, which are more in line with the parameters of the actual characteristics of the power amplifier, thereby improving the performance of the digital predistortion system and the linearity and efficiency of the RF power amplifier. However, the system can only improve the intermodulation distortion of the transmitter, but has no ability to suppress harmonic distortion, making it difficult to improve the overall performance of the shortwave transmitter. Summary of the Invention

[0007] The purpose of the present invention is to solve the problem that the existing digital predistortion method for improving the distortion of a shortwave power amplifier can only improve the intermodulation distortion of the shortwave power amplifier, has no ability to suppress harmonic distortion, and cannot improve the overall performance of the shortwave power amplifier. Instead, a system and method for improving the digital predistortion of shortwave intermodulation and harmonic distortion are provided.

[0008] The design concept of the present invention is: based on the characteristics of the shortwave signal format and the memory effect of the shortwave power amplifier, on the basis of integrating the cross-memory polynomial pre-distortion model, further adopting the FIR structure in the model and utilizing its low-pass filtering characteristics to suppress the high-order harmonics in the shortwave power amplifier octave, it is possible to achieve a digital pre-distortion system and method that simultaneously improves intermodulation and harmonic suppression, while improving the efficiency of the shortwave power amplifier and reducing the design requirements for the filter group cascaded at the output end of the shortwave transmitter power amplifier.

[0009] In order to achieve the above object, the technical solution adopted by the present invention is:

[0010] A digital predistortion system for improving shortwave intermodulation and harmonic distortion, which is special in that it includes a digital predistorter, an analog-to-digital converter module (DAC), a power amplifier, an attenuator (ATT), an analog-to-digital converter module (ADC), and a corresponding predistortion model parameter determination module;

[0011] The output end of the digital predistorter is electrically connected to an analog-to-digital conversion module (DAC) and a first input end of a predistortion model parameter obtaining module;

[0012] The output end of the analog-to-digital conversion module (DAC) is electrically connected to the input end of the power amplifier, and the power amplifier directly outputs the signal, wherein a portion of the signal is electrically connected to the input end of the attenuator (ATT) after coupling; the output end of the attenuator (ATT) is electrically connected to the input end of the analog-to-digital conversion module (ADC);

[0013] The output end of the analog-to-digital conversion module (ADC) is electrically connected to the second input end of the predistortion model parameter obtaining module;

[0014] The output end of the predistortion model parameter obtaining module is electrically connected to the input end of the digital predistorter.

[0015] Furthermore, the digital predistorter is provided with an ABS function module 1, a plurality of lookup tables, a plurality of delay devices, a plurality of multipliers, a first adder 2 and a second adder 6;

[0016] The first output end of the digital baseband signal is electrically connected to the first input end of the first multiplier 3, the second output end is electrically connected to the input end of the ABS function module 1, and the third output end is electrically connected to the input end of the first delay device 4;

[0017] The first output terminal of the abs function module 1 is connected to the lookup table LUT 1,1 The input terminal is electrically connected to the lookup table LUT 1,1 The output terminal is electrically connected to the first input terminal of the first adder 2;

[0018] The second output end of the abs function module 1 is electrically connected to the input end of the second delay 5, and the first output end of the second delay 5 is electrically connected to the lookup table LUT 1,2 The input terminal is electrically connected to the lookup table LUT 1,2 The output terminal is electrically connected to the second input terminal of the first adder 2;

[0019] The first output end of the first delay device 4 is electrically connected to the input end of the third delay device 8, and the second output end is electrically connected to the first input end of the second multiplier 7;

[0020] The second output terminal of the second delay device 5 is connected to the lookup table LUT K,1 The input terminal is electrically connected to the lookup table LUT K,1 The output end of is electrically connected to the first input end of the second adder 6; the third output end of the second delay device 5 is electrically connected to the input end of the fourth delay device 9;

[0021] The first output terminal of the fourth delay device (9) is connected to the lookup table LUT 1,3 The input terminal is electrically connected to the lookup table LUT 1,3The output end of the fourth delay device 9 is electrically connected to the third input end of the first adder 2; the second output end of the fourth delay device 9 is electrically connected to the lookup table LUT K,2 The input terminal is electrically connected to the lookup table LUT K,2 The output end of is electrically connected to the second input end of the second adder 6; the third output end of the fourth delay device 9 is electrically connected to the first input end of the third multiplier 10; the third output end of the fourth delay device 9 is electrically connected to the input end of the next stage delay device;

[0022] The output end of the first adder 2 is electrically connected to the second input end of the first multiplier 3, and the output end of the second adder 6 is electrically connected to the second input end of the second multiplier 7;

[0023] By analogy, the first output end of the 2j-3th delay unit is electrically connected to the input end of the 2j-1th delay unit, and the second output end of the 2j-3th delay unit is electrically connected to the first input end of the jth multiplier; wherein j≥2;

[0024] The first output terminal of the 2j-2th delay unit and the lookup table LUT 1,M The input end is electrically connected to M=j; the second output end of the 2j-2th delay device is electrically connected to the lookup table LUT K,M-1 The input end of the 2j-2th delay device is electrically connected to the input end of the 2jth delay device;

[0025] The lookup table LUT 1,M The output terminals of the first adder 2 are electrically connected to the Mth input terminal; the lookup table LUT K,M The output terminals of are respectively electrically connected to the Mth input terminal of the second adder 6;

[0026] The output ends of the first multiplier 3, the second multiplier 7, ..., and the j-th multiplier are electrically connected to the FIR low-pass filter characteristic model 11 respectively. The output signal of the FIR low-pass filter characteristic model 11 is the output signal of the digital predistorter.

[0027] The present invention further provides a method for improving shortwave intermodulation and harmonic distortion based on the digital predistortion system for improving shortwave intermodulation and harmonic distortion, the special features of which are:

[0028] The following steps are involved:

[0029] Step 1) The digital baseband signal is processed by a digital predistorter to obtain a predistorted signal;

[0030] Step 2) The predistortion signal is converted into an analog signal by a digital-to-analog converter (DAC), and amplified by a power amplifier to obtain an amplified analog signal;

[0031] Step 3) The amplified analog signal is coupled, attenuated by an attenuator (ATT), converted into a digital signal by an analog-to-digital converter (ADC) and transmitted to a predistortion parameter extraction module;

[0032] Step 4) The predistortion parameter extraction module processes the collected analog signal and predistortion signal to obtain predistortion parameters, which are then transmitted to the digital predistorter for real-time predistortion;

[0033] Step 5) Calculate the normalized mean square error NMSE between the current input signal and the predistorted output signal dB ;

[0034] Step 6) Determine the calculated normalized mean square error NMSE dB Is it greater than the preset target value?

[0035] If so, the predistortion parameters are calculated using the least squares method, and the corresponding lookup table obtained by performing power calculation on the input data is updated, and steps 4-5) are repeated using the updated lookup table to perform predistortion processing;

[0036] Otherwise, the current round of predistortion processing ends, and the next round of predistortion processing continues to use the current lookup table for predistortion processing;

[0037] Step 7) Repeat steps 4-6) to implement adaptive digital predistortion processing.

[0038] Furthermore, the processing method of the digital predistorter is:

[0039]

[0040] Among them, a k,qk with b k Solve the predistortion parameters for the bands in different LUTs respectively;

[0041] The LUT parameters are calculated by power calculation of the input data to obtain the corresponding table index address |x(n)|, and then the corresponding LUT parameters are obtained from this, that is, LUT(|x(n)|). The amplitude and phase of the signal x(n) applied to the input end of the power amplifier are then corrected to obtain the DPD(x(n)) after predistortion processing.

[0042] Furthermore, the FIR filter coefficients are calculated using least squares fitting.

[0043] Furthermore, taking the instantaneous predistortion expression as an example, step 4) is specifically as follows:

[0044] Step 4.1) The predistortion expression is:

[0045]

[0046] Among them, y n is the output signal of the digital predistorter in the discrete domain, x n is the input signal of the digital predistorter, n is the number of signal points; α m is the coefficient of the FIR filter, m=0,1,2,……M, m is the order of the FIR filter; p n is the normalized modulus value of the nth point of the input signal; α0, Δ1, α2, …, α m are the polynomial coefficients respectively;

[0047] Calculate the polynomial coefficients that minimize the objective function. The objective function is:

[0048]

[0049] Step 4.2) Write the objective function as a pre-distortion expression in matrix form, and define the error vector as:

[0050] ε=YX.*P.*W

[0051] in,

[0052] W=[α0α1α2…α m ]; Y=[y1 y2…y n ] T ;

[0053] .* represents dot product, that is, multiplying the corresponding elements of the matrix;

[0054] Step 4.3) is to make ε 2 Minimum, let X.*P=A, then the square of the error vector is expressed as:

[0055] ε 2 =Y 2 -2YA T W+W T AA T W

[0056] Differentiating W from the above formula, we get:

[0057] Where R = AA T , Q = YA;

[0058] make The least squares solution of W is:

[0059] W=R -1 Q

[0060] That is to say, the polynomial coefficients of the digital predistorter are α0, α1, Δ2,…, α m , m=0,1,2,……M.

[0061] Furthermore, in step 6), the system calculates the normalized mean square error NMSE in real time during operation. dB When it is greater than the target value, the least square method is used to calculate the predistortion parameters and send them to the digital predistorter. After the digital baseband signal is gain compensated by the digital predistorter, it is sent to the power amplifier and the NMSE is recalculated. dB .

[0062] Compared with the prior art, the present invention has the following beneficial technical effects:

[0063] 1. The digital predistortion system for improving shortwave intermodulation and harmonic distortion provided by the present invention integrates a digital predistortion model with a cross-memory polynomial structure and an FIR low-pass filter characteristic structure. By performing processing in the digital domain through the digital predistortion method, the purpose of simultaneously improving intermodulation and harmonic suppression can be achieved, and the harmonic suppression of existing analog filters can be reduced.

[0064] 2. The digital predistortion method for improving shortwave intermodulation and harmonic distortion provided by the present invention adopts a digital predistortion model that integrates a cross-memory polynomial structure and an FIR low-pass filter characteristic structure, which can simultaneously improve intermodulation and harmonic suppression, and extract predistortion parameters with higher consistency, thereby improving the performance of the digital predistortion system. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] Figure 1 This is the overall architecture diagram of the existing pre-distortion structure;

[0066] Figure 2 It is a schematic diagram of the existing pre-distortion table extraction;

[0067] Figure 3 This is an existing pre-distortion model table index structure diagram;

[0068] Figure 4 2. It is a schematic diagram of a system embodiment of the present invention for improving digital predistortion of shortwave intermodulation and harmonic distortion;

[0069] Figure 5 It is a schematic diagram of the structure of the digital predistorter of the present invention;

[0070] Figure 6 This is the LUT of the present invention K,qk The structure and storage content of

[0071] Figure 7 This is the LUT of the present invention k The structure and storage content of

[0072] Figure 8 The improved time domain waveform of the embodiment of the digital predistortion method of the present invention is compared with the overall time domain waveform of the traditional memory polynomial model result;

[0073] Figure 9 The improved time domain waveform of the embodiment of the digital predistortion method of the present invention is compared with the overall local amplified waveform of the traditional memory polynomial model result;

[0074] Figure 10 The improved frequency domain waveform result of the digital predistortion method embodiment of the present invention is compared with the overall frequency domain result of the traditional memory polynomial model;

[0075] Figure 11 The improved frequency domain waveform result of the digital predistortion method embodiment of the present invention is compared with the intermodulation distortion frequency domain result of the local amplification of the traditional memory polynomial model;

[0076] Figure 12 The figure compares the improved frequency domain waveform result of the digital predistortion method embodiment of the present invention with the second harmonic distortion frequency domain result of the local amplification of the traditional memory polynomial model;

[0077] Figure 13 The improved frequency domain waveform result of the digital predistortion method embodiment of the present invention is compared with the frequency domain result of the third harmonic distortion of the traditional memory polynomial model with local amplification;

[0078] Reference numerals:

[0079] 1-abs function module, 2-first adder, 3-first multiplier, 4-first delay, 5-second delay, 6-second adder, 7-second multiplier, 8-third delay, 9-fourth delay, 10-third multiplier, 11-FIR low-pass filter characteristic model. DETAILED DESCRIPTION

[0080] To make the objectives, advantages, and features of the present invention more apparent, a system and method for improving shortwave intermodulation and harmonic distortion proposed by the present invention are further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood by those skilled in the art that these embodiments are merely intended to explain the technical principles of the present invention and are not intended to limit the scope of protection of the present invention.

[0081] like Figure 1As shown, a pre-distortion structure of the prior art adopts a lookup table (LUT) method. The LUT is retrieved according to the amplitude of the signal, or a certain function of the input amplitude, and then the amplitude and phase of the signal applied to the input end of the power amplifier are corrected. The pre-distortion system structure includes two channels: a loop channel for data training and a pre-distortion channel. The data training channel is a loop structure, and its core part is the pre-distortion algorithm module. The module extracts the distortion characteristics of the power amplifier by processing the feedback signal (obtained by coupling the power amplifier output) after the power amplifier and the original input signal, and then obtains the LUT parameters of the power amplifier distortion inverse characteristics. When the power amplifier characteristics change with time or changes in the external environment, the pre-distortion inverse characteristic LUT parameters can be updated by the adaptive pre-distortion algorithm.

[0082] like Figure 2 The figure shows a schematic diagram of a pre-distortion parameter extraction method in the prior art. Here, X is the input signal and Y is the feedback signal. First, the output power is determined based on demand. During the first operation, the system is directly passed through, LUT(X) = X, and the first set of output data is obtained after the signal passes through the power amplifier. Feedback is used for pre-distortion, and the LUT parameters are obtained by solving min|LUT(Y)-LUT(X)|. The LUT parameters are then continuously modified during the iterative process until a satisfactory effect is obtained for the output signal Y. The LUT parameters at this point are extracted as the pre-distortion LUT at this output power for use by the system.

[0083] like Figure 3 Figure 1 shows a table index structure for a conventional predistortion model. The LUT parameters are calculated by performing power calculations on the input data to obtain the corresponding table index address |x(n)|. This LUT parameter, LLUT(|x(n)|), is then used to correct the amplitude and phase of the signal X(n) applied to the power amplifier input to obtain the post-predistortion DPD(x(n)).

[0084] like Figure 4 As shown, the digital predistortion system for improving shortwave intermodulation and harmonic distortion proposed in the present invention includes a digital predistorter, an analog-to-digital conversion module (DAC), a power amplifier, an attenuator (ATT), an analog-to-digital conversion module (ADC) and a corresponding predistortion model parameter acquisition module.

[0085] The output end of the digital predistorter is electrically connected to an analog-to-digital conversion module (DAC) and a first input end of a predistortion model parameter determination module; the output end of the analog-to-digital conversion module (DAC) is electrically connected to the input end of a power amplifier, and the power amplifier directly outputs a signal, wherein a portion of the signal is electrically connected to the input end of an attenuator (ATT) after coupling; the output end of the attenuator (ATT) is electrically connected to the input end of an analog-to-digital conversion module (ADC); the output end of the analog-to-digital conversion module (ADC) is electrically connected to the second input end of the predistortion model parameter determination module; and the output end of the predistortion model parameter determination module is electrically connected to the input end of the digital predistorter.

[0086] When the system does not perform pre-distortion processing, the digital baseband signal is directly converted into an analog signal through the DAC and amplified by the power amplifier; when pre-distortion processing is performed, the signal output from the power amplifier is attenuated by the ATT, then enters the ADC, and is sent to the pre-distortion model parameter determination module to obtain the pre-distortion parameters. Then, the obtained pre-distortion parameters are downloaded into the digital pre-distorter.

[0087] The digital baseband signal is processed by the digital predistorter to produce a predistorted signal. The predistorted signal is split into two paths: one is the forward main link midband data stream, which is sent to the power amplifier (PA) output via the analog-to-digital converter (ADC). The other is the feedback midband data stream, the digital baseband signal after the PA fused signal is down-converted. This is sent to the predistortion model parameter extraction module for predistortion parameter extraction, and then to the DPD for real-time predistortion.

[0088] Specifically, the digital predistorter is provided with an ABS function module 1, a plurality of lookup tables, a plurality of delay devices, a plurality of multipliers, a first adder 2 and a second adder 6;

[0089] The first output end of the digital baseband signal is electrically connected to the first input end of the first multiplier 3, the second output end is electrically connected to the input end of the ABS function module 1, and the third output end is electrically connected to the input end of the first delay device 4;

[0090] The first output terminal of the abs function module 1 is connected to the lookup table LUT 1,1 The input terminal is electrically connected to the lookup table LUT 1,1 The output terminal is electrically connected to the first input terminal of the first adder 2;

[0091] The second output end of the abs function module 1 is electrically connected to the input end of the second delay 5, and the first output end of the second delay 5 is electrically connected to the lookup table LUT 1,2 The input terminal is electrically connected to the lookup table LUT 1,2 The output terminal is electrically connected to the second input terminal of the first adder 2;

[0092] The first output end of the first delay device 4 is electrically connected to the input end of the third delay device 8, and the second output end is electrically connected to the first input end of the second multiplier 7;

[0093] The second output terminal of the second delay device 5 is connected to the lookup table LUT K,1 The input terminal is electrically connected to the lookup table LUT K,1 The output end of is electrically connected to the first input end of the second adder 6; the third output end of the second delay device 5 is electrically connected to the input end of the fourth delay device 9;

[0094] The first output terminal of the fourth delay device 9 is connected to the lookup table LUT 1,3 The input terminal is electrically connected to the lookup table LUT 1,3 The output end of the fourth delay device 9 is electrically connected to the third input end of the first adder 2; the second output end of the fourth delay device 9 is electrically connected to the lookup table LUT K,2 The input terminal is electrically connected to the lookup table LUT K,2 The output end of is electrically connected to the second input end of the second adder 6; the third output end of the fourth delay device 9 is electrically connected to the first input end of the third multiplier 10; the third output end of the fourth delay device 9 is electrically connected to the input end of the next stage delay device;

[0095] The output end of the first adder 2 is electrically connected to the second input end of the first multiplier 3, and the output end of the second adder 6 is electrically connected to the second input end of the second multiplier 7;

[0096] By analogy, the first output end of the 2j-3th delay unit is electrically connected to the input end of the 2j-1th delay unit, and the second output end of the 2j-3th delay unit is electrically connected to the first input end of the jth multiplier; wherein j≥2;

[0097] The first output terminal of the 2j-2th delay unit and the lookup table LUT 1,M The input end is electrically connected to M=j; the second output end of the 2j-2th delay device is electrically connected to the lookup table LUT K,M-1 The input end of the 2j-2th delay device is electrically connected to the input end of the 2jth delay device;

[0098] The lookup table LUT 1,M The output terminals of the first adder 2 are electrically connected to the Mth input terminal; the lookup table LUT K,M The output terminals of are respectively electrically connected to the Mth input terminal of the second adder 6;

[0099] The output ends of the first multiplier 3, the second multiplier 7, ..., and the j-th multiplier are electrically connected to the FIR low-pass filter characteristic model 11 respectively. The output signal of the FIR low-pass filter characteristic model 11 is the output signal of the digital predistorter.

[0100] The present invention also proposes a digital predistortion method for improving shortwave intermodulation and harmonic distortion. Based on the above digital predistortion system for improving shortwave intermodulation and harmonic distortion, the system performs predistortion processing after receiving a predistortion command input from an external source.

[0101] The input digital baseband signal, the forward signal passing through the digital predistorter, and the reverse signal fed back by the power amplifier are collected, and the currently collected signals are synchronized and aligned. Furthermore, the power amplifier modeling and predistortion parameter estimation are required in the digital predistortion system. The following steps are included:

[0102] Step 1) The digital baseband signal is processed by a digital predistorter to obtain a predistorted signal;

[0103] Step 2) The predistortion signal is converted into an analog signal by a digital-to-analog converter (DAC), and amplified by a power amplifier to obtain an amplified analog signal;

[0104] Step 3) The amplified analog signal is coupled, attenuated by an attenuator (ATT), converted into a digital signal by an analog-to-digital converter (ADC) and transmitted to a predistortion parameter extraction module;

[0105] Step 4) The distortion parameter extraction module processes the collected analog signal and predistortion signal to obtain predistortion parameters, which are then transmitted to the digital predistorter for real-time predistortion;

[0106] Step 5) Calculate the normalized mean square error NMSE between the current input signal and the predistorted output signal dB ;

[0107] Step 6) Determine the calculated normalized mean square error NMSE dB Is it greater than the preset target value?

[0108] If so, the predistortion parameters are calculated using the least squares method, and the corresponding lookup table obtained by performing power calculation on the input data is updated, and steps 4-5) are repeated using the updated lookup table to perform predistortion processing;

[0109] Otherwise, the current round of predistortion processing ends, and the next round of predistortion processing continues to use the current lookup table for predistortion processing;

[0110] Step 7) Repeat steps 4-6) to implement adaptive digital predistortion processing.

[0111] In step 4), based on Figure 5 The structure diagram of the digital predistortion model for improving shortwave intermodulation and harmonic distortion is shown in the figure, and the processing method of the digital predistorter is obtained as follows:

[0112]

[0113] Among them, a k,qk with b k Solve the predistortion parameters for the bands in different LUTs respectively;

[0114]

[0115] In formula (2), LUT K,qk Used to build polynomial systems, LUT K,qk The address is |x(n)|. Assume a LUT K,qk The number of units is 64, It's a LUT K,qk content, of which

[0116] Figure 6 Shown is the LUT K,qk structure and storage contents.

[0117] In formula (3), LUT k Used to build polynomial systems, LUT k The address is |x(n)|. Assume a LUT k The number of units is 64, It's a LUT k content, of which

[0118] Figure 7 Shown is the LUT k structure and storage contents.

[0119] Specifically, in this embodiment, k is 3, q ​​is 5, and the FIR order is 20;

[0120] When LUT K,qk and LUTs k When the parameter estimation module is updated, it calculates the required storage content. Then it writes the storage content into the LUT according to the address. K,qk and LUTs k In order to complete the LUT K,qk and LUTs k renew.

[0121] The parameter estimation module takes the instantaneous predistortion expression as an example to illustrate the calculation process of the above predistortion parameters:

[0122] Step 4.1) The predistortion expression is:

[0123]

[0124] Among them, y n is the output signal of the digital predistorter in the discrete domain, x n is the input signal of the digital predistorter, n is the number of signal points; α m is the coefficient of the FIR filter, m=0,1,2,……M, m is the order of the FIR filter; p n is the normalized modulus value of the nth point of the input signal; α0, Δ1, α2, …, α m are the polynomial coefficients respectively;

[0125] Calculate the polynomial coefficients that minimize the objective function. The objective function is:

[0126]

[0127] Step 4.2) Write the objective function as a pre-distortion expression in matrix form, and define the error vector as:

[0128] ε=YX.*P.*W

[0129] in,

[0130] W=[α0α1α2…α m ]; Y=[y1 y2…y n ] T ;

[0131] .* represents dot product, that is, multiplying the corresponding elements of the matrix;

[0132] Step 4.3) is to make ε 2 Minimum, let X.*P=A, then the square of the error vector is expressed as:

[0133] ε 2 =Y 2 -2YA T W+W T AA T W

[0134] Differentiating W from the above formula, we get:

[0135] Where R = AA T , Q = YA;

[0136] make The least squares solution of W is:

[0137] W=R-1 Q

[0138] That is to say, the polynomial coefficients of the digital predistorter are α0, α1, Δ2,…, α m , m=0,1,2,……M.

[0139] Step 5) Set the signal length to N and calculate the normalized mean square error NMSE between the current input signal and the predistorted output signal dB , N is a positive integer;

[0140]

[0141] Among them, x n Represents the nth point of the input signal, y n Indicates the nth point of the output signal.

[0142] Step 6) Determine whether the currently calculated normalized mean square error is greater than a preset target value. If so, use the least squares method to calculate the predistortion parameters, and update the lookup table accordingly. The next round of predistortion uses the updated lookup table for predistortion; otherwise, the next round of predistortion uses the current lookup table for predistortion.

[0143] Specifically, if NMSE dB If the value is less than the set target value, the pre-distortion calculation is terminated. Otherwise, the pre-distortion parameters are calculated and sent to the digital pre-distorter. After the digital baseband signal is gain compensated by the digital pre-distorter, it is sent to the power amplifier and the NMSE is recalculated. dB .

[0144] The system calculates NMSE in real time during operation dB When it is greater than the target value, a new round of pre-distortion calculation is started, and this cycle is repeated to achieve adaptive digital pre-distortion processing.

[0145] In the experiment, the shortwave power amplifier was stimulated by a two-tone signal with a 24 kHz spacing, a 40 MHz sampling rate, and a 4 MHz carrier frequency. The input signal generation and harmonic cancellation algorithm were performed in MATLAB. The signal was downloaded to a vector signal generator (ESG4438C) for injection into the power amplifier. The power amplifier's output signal was attenuated and then captured by a spectrum analyzer (N9010A), which shared the same reference clock and trigger signals as the VSG.

[0146] Figure 8The improved time domain waveform results are compared with the traditional memory polynomial model results. It can be seen that due to the presence of high-order harmonic distortion in the power amplifier output signal, a large amount of high-frequency waveform information appears in the peak part of the waveform. The traditional memory polynomial method does not produce ideal results, and high-frequency information still exists. The new method has a low-pass characteristic because the FIR is integrated into the structure, thus obtaining a smoother waveform curve. See Figure 5 Middle (local time domain waveform magnification) part.

[0147] Figure 9 This is a comparison of the overall local amplified waveform of the improved time domain waveform result of the digital predistortion method embodiment of the present invention and the traditional memory polynomial model result.

[0148] Figure 10 The improved frequency domain waveform is compared with the traditional memory polynomial model. It can be seen that after adopting the new model structure, the transmitter's third-order intermodulation index (2MHz to 30MHz) can be improved by more than 15dB compared with the traditional memory polynomial model.

[0149] Figure 11 The improved frequency domain waveform result of the digital predistortion method embodiment of the present invention is compared with the local amplified frequency domain result of the intermodulation distortion of the traditional memory polynomial model;

[0150] Figure 12 The improved frequency domain waveform result of the digital predistortion method embodiment of the present invention is compared with the local amplified frequency domain result of the second harmonic distortion of the traditional memory polynomial model;

[0151] Figure 13 The improved frequency domain waveform result of the digital predistortion method embodiment of the present invention is compared with the locally amplified frequency domain result of the third harmonic distortion of the traditional memory polynomial model;

[0152] The above comparison results can be seen in Table 1 below:

[0153] Table 1 Comparison of IMD and harmonic elimination performance of the proposed method

[0154]

[0155]

[0156] Compared with the traditional memory polynomial method, without increasing the complexity of the algorithm model, the baseband intermodulation distortion of the high-frequency power amplifier can be improved by more than 10dB, and the second and third harmonics can be suppressed to below -55dB, effectively compensating for the nonlinear distortion characteristics of the shortwave power amplifier and greatly improving the quality of shortwave radio communications.

[0157] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the present invention.

Claims

1. A digital predistortion system for improving shortwave intermodulation and harmonic distortion, characterized by: It includes a digital predistorter, an analog-to-digital conversion module (DAC), a power amplifier, an attenuator (ATT), an analog-to-digital conversion module (ADC) and a corresponding predistortion model parameter obtaining module; The output end of the digital predistorter is electrically connected to an analog-to-digital conversion module (DAC) and a first input end of a predistortion model parameter obtaining module; The output end of the analog-to-digital conversion module (DAC) is electrically connected to the input end of the power amplifier, and the power amplifier directly outputs the signal, wherein a portion of the signal is electrically connected to the input end of the attenuator (ATT) after coupling; the output end of the attenuator (ATT) is electrically connected to the input end of the analog-to-digital conversion module (ADC); The output end of the analog-to-digital conversion module (ADC) is electrically connected to the second input end of the predistortion model parameter obtaining module; The output end of the predistortion model parameter obtaining module is electrically connected to the input end of the digital predistorter; The digital predistorter is provided with an ABS function module (1), a plurality of lookup tables, a plurality of delay devices, a plurality of multipliers, a first adder (2) and a second adder (6); The first output end of the digital baseband signal is electrically connected to the first input end of the first multiplier (3), the second output end is electrically connected to the input end of the ABS function module (1), and the third output end is electrically connected to the input end of the first delay device (4); The first output terminal of the abs function module (1) is connected to the lookup table LUT 1,1 The input terminal is electrically connected to the lookup table LUT 1,1 The output end is electrically connected to the first input end of the first adder (2); The second output end of the ABS function module (1) is electrically connected to the input end of the second delay device (5), and the first output end of the second delay device (5) is electrically connected to the lookup table LUT 1,2 The input terminal is electrically connected to the lookup table LUT 1,2 The output end of is electrically connected to the second input end of the first adder (2); The first output end of the first delay device (4) is electrically connected to the input end of the third delay device (8), and the second output end is electrically connected to the first input end of the second multiplier (7); The second output terminal of the second delay device (5) is connected to the lookup table LUT K,1 The input terminal is electrically connected to the lookup table LUT K,1 The output end of the second adder (6) is electrically connected to the first input end of the second adder (6); the third output end of the second delay device (5) is electrically connected to the input end of the fourth delay device (9); The first output terminal of the fourth delay device (9) is connected to the lookup table LUT 1,3 The input terminal is electrically connected to the lookup table LUT 1,3 The output end of the fourth delay device (9) is electrically connected to the third input end of the first adder (2); the second output end of the fourth delay device (9) is electrically connected to the lookup table LUT K,2 The input terminal is electrically connected to the lookup table LUT K,2 The output end of the fourth delay device (9) is electrically connected to the second input end of the second adder (6); the third output end of the fourth delay device (9) is electrically connected to the first input end of the third multiplier (10); the third output end of the fourth delay device (9) is electrically connected to the input end of the next stage delay device; The output end of the first adder (2) is electrically connected to the second input end of the first multiplier (3), and the output end of the second adder (6) is electrically connected to the second input end of the second multiplier (7); By analogy, the first output end of the 2j-3th delay unit is electrically connected to the input end of the 2j-1th delay unit, and the second output end of the 2j-3th delay unit is electrically connected to the first input end of the jth multiplier; wherein j≥2; The first output terminal of the 2j-2th delay unit and the lookup table LUT 1,M The input terminal is electrically connected, M = j; The second output end of the 2j-2th delay device is connected to the lookup table LUT K,M-1 The input end of the 2j-2th delay device is electrically connected to the input end of the 2jth delay device; The lookup table LUT 1,M The output ends of are electrically connected to the Mth input end of the first adder (2); the lookup table LUT K,M The output terminals of the second adder (6) are electrically connected to the Mth input terminal respectively; The output ends of the first multiplier (3), the second multiplier (7), ..., and the j-th multiplier are respectively electrically connected to an FIR low-pass filter characteristic model (11), and the output signal of the FIR low-pass filter characteristic model (11) is the output signal of the digital predistorter.

2. A method for improving digital predistortion of shortwave intermodulation and harmonic distortion, based on the digital predistortion system for improving shortwave intermodulation and harmonic distortion according to claim 1, characterized in that: The following steps are involved: Step 1) The digital baseband signal is processed by a digital predistorter to obtain a predistorted signal; Step 2) converting the predistortion signal into an analog signal via a digital-to-analog converter (DAC), and amplifying the signal via a power amplifier to obtain an amplified analog signal; Step 3) The amplified analog signal is coupled and attenuated by a post attenuator (ATT), converted into a digital signal by an analog-to-digital converter (ADC) and transmitted to a predistortion parameter extraction module; Step 4) The predistortion parameter extraction module processes the collected analog signal and predistortion signal to obtain predistortion parameters, which are then transmitted to the digital predistorter for real-time predistortion; Step 5) Calculate the normalized mean square error NMSE between the current input signal and the predistorted output signal dB ; Step 6) Determine the calculated normalized mean square error NMSE dB Is it greater than the preset target value? If so, the predistortion parameters are calculated using the least squares method, and the corresponding lookup table obtained by performing power calculation on the input data is updated, and steps 4-5) are repeated using the updated lookup table to perform predistortion processing; Otherwise, the current round of predistortion processing ends, and the next round of predistortion processing continues to use the current lookup table for predistortion processing; Step 7) Repeat steps 4-6) to implement adaptive digital predistortion processing.

3. The method for improving digital predistortion of shortwave intermodulation and harmonic distortion according to claim 2, characterized in that: The processing method of the digital predistorter is: Among them, a k,qk with b k Solve the predistortion parameters for the bands in different LUTs respectively; The LUT parameters are calculated by power calculation of the input data to obtain the corresponding table index address |x(n)|, and then the corresponding LUT parameters are obtained from this, that is, LUT(|x(n)|). The amplitude and phase of the signal x(n) applied to the input end of the power amplifier are then corrected to obtain the DPD(x(n)) after predistortion processing.

4. The method for improving digital predistortion of shortwave intermodulation and harmonic distortion according to claim 2, characterized in that: The FIR filter coefficients are calculated using least squares fitting.

5. The method for improving digital predistortion of shortwave intermodulation and harmonic distortion according to claim 3, characterized in that: Taking the instantaneous predistortion expression as an example, step 4 is specifically as follows: Step 4.1) The predistortion expression is: Among them, y n is the output signal of the digital predistorter in the discrete domain, x n is the input signal of the digital predistorter, n is the number of signal points; α m is the coefficient of the FIR filter, m=0,1,2,……M, m is the order of the FIR filter; p n is the normalized modulus value of the nth point of the input signal; α0, α1, α2, …, α m are the polynomial coefficients respectively; Calculate the polynomial coefficients that minimize the objective function. The objective function is: Step 4.2) Write the objective function as a pre-distortion expression in matrix form, and define the error vector as: ε=YX.*P.*W in, W=[α0α1α2…α m ];Y=[y1 y2…y n ] T ; .* represents dot product, that is, multiplying the corresponding elements of the matrix; Step 4.3) is to make ε 2 Minimum, let X.*P=A, then the square of the error vector is expressed as: ε 2 =Y 2 -2YA T W+W T AA T IN Differentiating W from the above formula, we get: Among them, R=AA T , Q = YA; make The least squares solution of W is: W=R -1 Q That is, the polynomial coefficients of the digital predistorter are α0, α1, α2, …, α m , m=0,1,2,……M.

6. The method for improving digital predistortion of shortwave intermodulation and harmonic distortion according to claim 2, characterized in that: In step 6), the system calculates the normalized mean square error (NMSE) in real time during operation. dB When it is greater than the target value, the least square method is used to calculate the predistortion parameters and send them to the digital predistorter. After the digital baseband signal is gain compensated by the digital predistorter, it is sent to the power amplifier and the NMSE is recalculated. dB .

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