Multi-antenna secure communication system based on chaotic scrambling and index modulation in 5G network

Abstract

The multi-antenna secure communication system based on chaotic scrambling and index modulation in the 5G network of the present invention comprises the following steps: at the transmitting end, a brancher is connected to a scrambling circuit module through an index and modulation bit generator, a QAM modulator, etc. in sequence; the index bit and the index bit generated by the modulation bit generator are respectively transmitted to the corresponding index modulator; the chaos generator is connected to the scrambling circuit module through a chaotic scrambling matrix generator and a secret key generator in sequence; the scrambling circuit module is connected to a 5G transmitting antenna; at the receiving end, a chaos generator is connected to the scrambling circuit module through a chaotic scrambling matrix generator and a secret key generator in sequence; the scrambling circuit module is connected to a 5G receiving antenna, the scrambling circuit module is connected to a minimum mean square error detector through a de-cyclic prefix device, a serial-to-parallel converter, an FFT converter, and a parallel-to-serial converter in sequence, and the minimum mean square error detector is connected to the index bit and the modulation bit synthesizer in sequence through a maximum likelihood detector and a QAM demodulator.

Description

Technical Field

[0001] The present invention belongs to the field of confidential communication and information security technology in 5G networks, and specifically relates to a multi-antenna secure communication system based on chaotic scrambling and index modulation in a 5G network. Background Art

[0002] Frequency division multiplexing (OFDM) has become the most popular multi-carrier signaling format in high-speed wireless communications in 5G networks and has been incorporated into many standards such as LTE, IEEE802.11 wireless local area network (WLAN) and digital video broadcasting (DVB). Due to the efficient implementation of OFDM and its robustness to frequency selection, OFDM and its combination with multiple-input multiple-output (MIMO) systems are undoubtedly a strong alternative for 5G networks. The MIMO method expands data throughput and link range in wireless communications, and it is one of the radio circuits with great prospects for development in this field. It achieves a group gain by increasing the overall comprehensive transmission control of multiple receiving lines, which builds extraordinary effectiveness; it also achieves various gains that improve the reliability of the link. Index modulation considers creative methods to handle additional data bits that are different from traditional MIMO-OFDM, and improves the spectrum utilization of the system and communication performance by flexibly selecting activated subcarriers. However, the existing technology still has the problem of low communication security. Summary of the invention

[0003] In view of the shortcomings of the existing technology, the present invention combines MIMO and OFDM-IM transmission technologies to replace the traditional multi-carrier transmission scheme in the 5G network, uses the chaotically generated secret key to control the selection of transmission antennas to achieve secure communication, and provides a multi-antenna secure communication system based on chaotic scrambling and index modulation in the 5G network.

[0004] The innovative technology of the present invention is that the information bits are divided into N paths, each with m bits, and then divided into index bits and modulation bits. The modulation bits are modulated by QAM to generate corresponding symbols, and then the activated subcarriers are modulated by the index bits. After each path is converted from serial to parallel, it is superimposed on different subcarriers through inverse fast Fourier transform (IFFT). After parallel-to-serial conversion, a cyclic prefix is ​​added, and it is input into the circuit switching module controlled by the secret key generated by chaos, and sent to different antennas. Since the secret key is changed in real time, the encrypted transmission of information is realized by controlling it. Finally, it is transmitted through the 5G transmitting antenna. In this way, due to the unpredictable nature of the chaotic sequence, if the attacker does not obtain the complete chaotic sequence, the sent information cannot be restored. At the receiving end, after each receiving antenna receives the signal, it is transmitted to the circuit switching module controlled by the secret key generated by the chaos synchronized with the transmitting end, and exchanged to the corresponding exit. The cyclic prefix is ​​removed from each channel, and the received information is converted into frequency domain information by using the fast Fourier transform (FFT) after the serial-to-parallel conversion. After each channel performs the parallel-to-serial conversion, it is input into the minimum mean square error (MMSE) detector for calculation to eliminate Gaussian channel noise. After obtaining each channel signal, it is input into the maximum likelihood (LLR) detector for calculation to restore the sparse symbols containing 0 carried by the subcarrier, and then demodulated by the QAM signal demodulator. The demodulated signal is input into the modulation bit and index bit synthesizer, and the corresponding index bit is generated from the modulation bit by using the table lookup method. After each channel signal is restored, the delay line is used to synthesize the various channels of signals into one channel, and the original information is restored.

[0005] In order to achieve the above-mentioned object of the invention, the present invention adopts the following technical solutions:

[0006] A multi-antenna secure communication system based on chaotic scrambling and index modulation in a 5G network includes a transmitting end and a receiving end, wherein the transmitting end and the receiving end communicate with each other through a wireless channel of a 5G transmitting antenna and a 5G receiving antenna;

[0007] The transmitting end includes a branching device, N index bits and modulation bit generators, N QAM modulators, N index modulators, N serial-to-parallel converters, N IFFT converters, N parallel-to-serial converters, N cyclic prefix importers, a first chaos generator, a first chaotic scrambling matrix generator, a first secret key generator, a first scrambling circuit module, and N 5G transmitting antennas; the N ports of the branching device are respectively connected to the N input ports of the first scrambling circuit module through the N index bits and modulation bit generators, N QAM modulators, N index modulators, N serial-to-parallel converters, N IFFT converters, N parallel-to-serial converters, and N cyclic prefix importers in sequence; the index bits generated by the N index bits and modulation bit generators are respectively transmitted to the N index modulators; the first chaos generator is connected to the first scrambling circuit module through the first chaotic scrambling matrix generator and the first secret key generator in sequence; the N output ports of the first scrambling circuit module are respectively connected to the N 5G transmitting antennas;

[0008] The receiving end includes N 5G receiving antennas, a second chaos generator, a second chaos scrambling matrix generator, a second key generator, a second scrambling circuit module, N cyclic prefix removal devices, N serial-to-parallel converters, N FFT converters, N parallel-to-serial converters, a minimum mean square error detector, N maximum likelihood detectors, N QAM demodulators, and N index bits and modulation bit synthesizers; the second chaos generator is connected to the second scrambling circuit module through the second chaos scrambling matrix generator and the second key generator in turn; the N input ports of the second scrambling circuit module are connected to the N 5G receiving antennas, and the N output ports of the second scrambling circuit module are connected to the N input ports of the minimum mean square error detector through N cyclic prefix removal devices, N serial-to-parallel converters, N FFT converters, and N parallel-to-serial converters in turn, and the N output ports of the minimum mean square error detector are connected to the N index bits and modulation bit synthesizer through N maximum likelihood detectors and N QAM demodulators in turn.

[0009] At the transmitting end: the information bits are divided into N paths by the splitter, each path has m bits, and then the index bit and modulation bit generator divides the m bits of information into k1 index bits and k2 modulation bits. The k2 modulation bits are modulated by the QAM modulator to generate corresponding symbols, and then the k2 subcarriers activated by the k1 index bits are modulated in each index modulator. After each path is converted from serial to parallel by the serial-to-parallel converter, it is superimposed on different subcarriers through each inverse fast Fourier transform (IFFT). After the parallel-to-serial converter is used to convert the parallel to serial, the cyclic prefix is ​​added in the cyclic prefix device and input into the scrambling circuit module controlled by the secret key generated by chaos. The transmitting end generates a high-complexity chaotic signal, generates a scrambling matrix in the scrambling matrix generator, and then generates a secret key in the secret key generator. The secret key is used to control the input and output of each signal in the scrambling circuit module, so as to send it to different 5G antennas. Since the secret key is changed in real time, the encrypted transmission of information can be achieved by controlling it. In this way, due to the unpredictable nature of the chaotic sequence, the attacker cannot restore the sent information in real time if he does not obtain the complete chaotic sequence.

[0010] At the receiving end, a chaos generator synchronized with the transmitting end generates a high-complexity chaotic signal. In the scrambling matrix generator, a scrambling matrix is ​​generated. Then, in the secret key generator, a secret key is generated. This secret key is used to control the input and output of the scrambling circuit module where each 5G receiving antenna receives the signal, and exchanges it to the corresponding exit. The cyclic prefix remover of each route removes the cyclic prefix. After the serial-to-parallel converter performs serial-to-parallel conversion, each fast Fourier transform (FFT) is used to perform fast Fourier transform (FFT) to convert the received information into frequency domain information. After each route parallel-to-serial converter performs parallel-to-serial conversion, it is input into the minimum mean square error (MMSE) detector for calculation to eliminate Gaussian channel noise. After obtaining the signals of each route, they are input into the maximum likelihood (LLR) detector for calculation to restore the sparse symbols containing 0 carried by the subcarrier, and then demodulated by the QAM signal demodulator. The demodulated signal is input into the modulation bit and index bit synthesizer. Using the table lookup method, the corresponding k1 index bits are generated from the k2 modulation bits to synthesize into m bits of information. In this way, each signal is restored, and then the delay line is used to combine the signals into one, thus restoring the original Nm bits of information.

[0011] As a preferred solution, the chaos generators at the receiving end and the transmitting end are completely synchronized.

[0012] As a preferred solution, the signal bits are divided into N paths by a splitter, each path has m bits, and then the m-bit information is divided into k1 index bits and k2 modulation bits by an index bit and modulation bit generator. The k2 modulation bits are QAM modulated by a QAM modulator to generate corresponding symbols, and then the k2 subcarriers activated by the k1 index bits are modulated in each index modulator.

[0013] As a preferred solution, each channel is converted from serial to parallel by a serial to parallel converter and then superimposed on different subcarriers through respective inverse fast Fourier transforms (IFFTs).

[0014] As a preferred solution, after parallel-to-serial conversion using a parallel-to-serial converter, a cyclic prefix is ​​added in a cyclic prefix device and input into a scrambling circuit module controlled by a secret key generated by chaos.

[0015] As a preferred solution, the transmitting end generates a high-complexity chaotic signal, generates a scrambled matrix in the scrambled matrix generator, and then generates a secret key in the secret key generator. This secret key is used to control the input and output of each signal in the scrambled circuit module, thereby sending them to different 5G antennas.

[0016] As a preferred solution, a chaos generator synchronized with the transmitting end generates a high-complexity chaotic signal, a scrambled matrix is ​​generated in the scrambled matrix generator, and then a secret key is generated in the secret key generator. This secret key is used to control the input and output of the scrambled circuit module where each 5G receiving antenna receives the signal and exchanges it to the corresponding output.

[0017] As a preferred solution, each route removes the cyclic prefix, and after serial-to-parallel conversion by the serial-to-parallel converter, each route uses a fast Fourier transform (FFT) to convert the received information into frequency domain information.

[0018] As a preferred solution, after each routing parallel-to-serial converter performs parallel-to-serial conversion, it is input into a minimum mean square error (MMSE) detector for calculation to eliminate Gaussian channel noise. After obtaining each signal, it is input into a maximum likelihood (LLR) detector for calculation to restore the sparse symbols containing 0 carried by the subcarrier, and then demodulated using a QAM signal demodulator.

[0019] As a preferred solution, the demodulated signal is input to the index bit and modulation bit synthesizer, and the corresponding k1 index bits are generated from the k2 modulation bits by using the table lookup method to synthesize into m bits of information. In this way, each signal is restored, and then the delay line is used to synthesize the signals into one, thus restoring the original Nm bits of information.

[0020] The principle and process of the multi-antenna secure communication system based on chaotic scrambling and index modulation in the 5G network of the present invention are as follows:

[0021] The information bits are divided into N paths by the splitter, each path has m bits, and then the index bit and modulation bit generator divides the m bits of information into k1 index bits and k2 modulation bits. The k2 modulation bits are modulated by the QAM modulator to generate corresponding symbols, and then the k2 subcarriers activated by the k1 index bits are modulated in each index modulator. After each path is converted from serial to parallel by the serial-to-parallel converter, it is superimposed on different subcarriers through each inverse fast Fourier transform (IFFT). After the parallel-to-serial converter is used to convert the parallel to serial, the cyclic prefix is ​​added in the cyclic prefix device and input into the scrambling circuit module controlled by the secret key generated by chaos. The transmitter generates a high-complexity chaotic signal, generates a scrambling matrix in the scrambling matrix generator, and then generates a secret key in the secret key generator. The secret key is used to control the input and output of each signal in the scrambling circuit module, so as to send it to different 5G antennas. Since the secret key is changed in real time, the encrypted transmission of information can be achieved by controlling it. In this way, due to the unpredictable nature of the chaotic sequence, the attacker cannot restore the sent information in real time if he does not obtain the complete chaotic sequence.

[0022] At the receiving end, a chaos generator synchronized with the transmitting end generates a high-complexity chaotic signal. In the scrambled matrix generator, a scrambled matrix is ​​generated. Then, in the secret key generator, a secret key is generated. This secret key is used to control the input and output of the scrambled circuit module where each 5G receiving antenna receives the signal, and exchanges it to the corresponding exit. The cyclic prefix remover of each route removes the cyclic prefix, and after the serial-to-parallel conversion by the serial-to-parallel converter, the fast Fourier transform (FFT) is performed by each fast Fourier transform (FFT) to convert the received information into frequency domain information. After each route parallel-to-serial converter performs the parallel-to-serial conversion, it is input into the minimum mean square error (MMSE) detector, and the minimum mean square error of the received signal is statistically calculated. After obtaining each signal, it is input into the maximum likelihood (LLR) detector, and the maximum likelihood function is calculated to restore the sparse symbols containing 0 carried by the subcarrier, and then the QAM signal demodulator is used for demodulation. The demodulated signal is input to the modulation bit and index bit synthesizer. The mapping relationship table between the set index bit and the modulation bit is used to generate the corresponding k1 index bits from the k2 modulation bits by looking up the table, and then synthesize into m bits of information. In this way, each signal is restored. Then, the delay line is used to synthesize the signals into one, and the original Nm bits of information are restored.

[0023] Compared with the prior art, the present invention has the following beneficial effects:

[0024] The present invention completes a multi-antenna secure communication system based on chaotic scrambling and index modulation in a 5G network. Its security lies in: when information is input into a circuit switching module controlled by a secret key generated by chaos, the secret key is changed in real time, and the encrypted transmission of information is realized by controlling it. Finally, it is transmitted through a 5G transmitting antenna. At the same time, due to the unpredictable nature of the chaotic sequence, the attacker cannot recover the sent information if he does not obtain the complete chaotic sequence. Therefore, the system is safe. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is an architecture diagram of a secure communication system based on chaotic index modulation in a 5G network according to an embodiment of the present invention.

[0026] in:

[0027] Brancher 19, first index bit and modulation bit generator 1-1, second index bit and modulation bit generator 1-2, ..., Nth index bit and modulation bit generator 1-N, first QAM modulator 201, second QAM modulator 2-2, ..., Nth QAM modulator 2-N, first index modulator (IM) 3-1, second index modulator (IM) 3-2, ..., Nth index modulator (IM) 3-N, first serial-to-parallel converter 4-1, second serial-to-parallel converter 4-2, ..., Nth serial-to-parallel converter 4-N, first IFFT converter 5- 1. The second IFFT converter 5-2, ..., the Nth IFFT converter 5-N, the first parallel-to-serial converter 6-1, the second parallel-to-serial converter 6-2, ..., the Nth parallel-to-serial converter 6-N, the first cyclic prefix importer 7-1, the second cyclic prefix importer 7-2, the Nth cyclic prefix importer 7-N, the first chaos generator 10-1, the first chaotic scrambling matrix generator 11-1, the first secret key generator 12-1, the first scrambling circuit module 8-1, the first 5G transmitting antenna 9-1, the second 5G transmitting antenna 9-2, and the Nth 5G transmitting antenna 9-N. The first 5G receiving antenna 9-(N+1), the second 5G receiving antenna 9-(N+2), ..., the Nth 5G receiving antenna 9-2N, the second chaos generator 10-2, the second chaotic scrambling matrix generator 11-2, the second secret key generator 12-2, the second scrambling circuit module 8-2, the first de-pilot cyclic prefix 13-1, the second de-pilot cyclic prefix 13-2, ..., the Nth de-pilot cyclic prefix 13-N, the N+1th serial-to-parallel converter 4-(N+1), the N+2th serial-to-parallel converter 4-(N+2), ..., the 2Nth serial-to-parallel converter 4-2N, the first FFT converter 14-1, the second FFT converter 14-2, ..., the Nth FFT converter FT converter 14-N, N+1th parallel-to-serial converter 6-(N+1), N+2th parallel-to-serial converter 6-(N+2),…, 2Nth parallel-to-serial converter 6-2N, minimum mean square error detector (MMSE) 15, first maximum likelihood detector (LLR) 16-1, second maximum likelihood detector 16-2,…, Nth maximum likelihood detector 16-N, first QAM demodulator 17-1, second QAM demodulator 17-2,…, Nth QAM demodulator 17-N, first index bit and modulation bit synthesizer 18-1, second index bit and modulation bit synthesizer 18-2,…, Nth index bit and modulation bit synthesizer 18-N.

[0028] Figure 2 The chaotic sequences generated by the sender and receiver, (a) is the chaotic sequence generated by the sender, (b) is the chaotic sequence generated by the receiver;

[0029] Figure 3 It is the constellation diagram of QAM signal;

[0030] Figure 4 It is the relationship between signal-to-noise ratio and bit error rate in maximum likelihood decision;

[0031] Figure 5 (a) is the transmitted signal, and (b) is the received signal. DETAILED DESCRIPTION

[0032] In order to more clearly illustrate the embodiments of the present invention, the specific implementation methods of the present invention will be described below with reference to the accompanying drawings. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those of ordinary skill in the art, other accompanying drawings and other implementation methods can be obtained based on these accompanying drawings without creative work.

[0033] The multi-antenna secure communication system based on chaotic scrambling and index modulation in the 5G network of the embodiment of the present invention includes a transmitting end and a receiving end, and the transmitting end and the receiving end communicate with each other through a wireless channel between the transmitting and receiving antennas. The transmitting end and the receiving end use the same initial conditions to generate the same chaotic sequence for generating secret keys respectively, and scramble the input-output channel in the scrambling circuit module.

[0034] The transmitting end includes: a brancher 19, a first index bit and modulation bit generator 1-1, a second index bit and modulation bit generator 1-2, ..., an Nth index bit and modulation bit generator 1-N, a first QAM modulator 201, a second QAM modulator 2-2, ..., an Nth QAM modulator 2-N, a first index modulator (IM) 3-1, a second index modulator (IM) 3-2, ..., an Nth index modulator (IM) 3-N, a first serial-to-parallel converter 4-1, a second serial-to-parallel converter 4-2, ..., an Nth serial-to-parallel converter 4-N, a first IFFT converter 5-1, the second IFFT converter 5-2, ..., the Nth IFFT converter 5-N, the first parallel-to-serial converter 6-1, the second parallel-to-serial converter 6-2, ..., the Nth parallel-to-serial converter 6-N, the first cyclic prefix importer 7-1, the second cyclic prefix importer 7-2, the Nth cyclic prefix importer 7-N, the first chaos generator 10-1, the first chaotic scrambling matrix generator 11-1, the first secret key generator 10-2, the first scrambling circuit module 8-1, the first 5G transmitting antenna 9-1, the second 5G transmitting antenna 9-2, and the Nth 5G transmitting antenna 9-N.

[0035] The receiving end includes: a first 5G receiving antenna 9-(N+1), a second 5G receiving antenna 9-(N+2), an Nth 5G receiving antenna 9-2N, a second chaos generator 10-2, a second chaos scrambling matrix generator 11-2, a second secret key generator 12-2, a second scrambling circuit module 8-2, a first de-pilot cyclic prefix 13-1, a second de-pilot cyclic prefix 13-2, ..., an Nth de-pilot cyclic prefix 13-N, an N+1th serial-to-parallel converter 4-(N+1), an N+2th serial-to-parallel converter 4-(N+2), ..., a 2Nth serial-to-parallel converter 4-2N, a first FFT Converter 14-1, second FFT converter 14-2, ..., Nth FFT converter 14-N, minimum mean square error detector (MMSE) 15, first maximum likelihood detector (LLR) 16-1, second maximum likelihood detector 16-2, ..., Nth maximum likelihood detector 16-N, first QAM demodulator 17-1, second QAM demodulator 17-2, ..., Nth QAM demodulator 17-N, first index bit and modulation bit synthesizer 18-1, second index bit and modulation bit synthesizer 18-2, ..., Nth index bit and modulation bit synthesizer 18-N.

[0036] The receiver communicates with the transmitter through a wireless channel via two transmitting and receiving antennas.

[0037] The transmitter divides the information bits into N paths by the splitter, each path has m bits, and then the index bit and modulation bit generator divides the m bits of information into k1 index bits and k2 modulation bits. The k2 modulation bits are modulated by the QAM modulator to generate corresponding symbols, and then the k2 subcarriers activated by the k1 index bits are modulated in each index modulator. After each path is converted from serial to parallel by the serial-to-parallel converter, it is superimposed on different subcarriers through each inverse fast Fourier transform (IFFT). After the parallel-to-serial converter is used to convert the parallel to serial, the cyclic prefix is ​​added in the cyclic prefix device and input into the scrambling circuit module controlled by the secret key generated by chaos. The transmitter generates a high-complexity chaotic signal, generates a scrambling matrix in the scrambling matrix generator, and then generates a secret key in the secret key generator. The secret key is used to control the input and output of each signal in the scrambling circuit module, so as to send it to different 5G antennas. Since the secret key is changed in real time, the encrypted transmission of information can be achieved by controlling it. In this way, due to the unpredictable characteristics of chaotic sequences, the attacker cannot recover the transmitted information in real time if he does not obtain the complete chaotic sequence. At the receiving end, the chaotic generator synchronized with the transmitting end generates a high-complexity chaotic signal, and the scrambled matrix is ​​generated in the scrambled matrix generator. Then, the secret key is generated in the secret key generator. The secret key is used to control the input and output of the scrambled circuit module where each 5G receiving antenna receives the signal, and the signal is exchanged to the corresponding exit. The cyclic prefix remover of each route removes the cyclic prefix, and the serial-to-parallel converter performs serial-to-parallel conversion. The fast Fourier transform (FFT) is used to convert the received information into frequency domain information. After the parallel-to-serial converter of each route performs the parallel-to-serial conversion, it is input into the minimum mean square error (MMSE) detector to eliminate Gaussian channel noise. After obtaining the signals of each route, it is input into the maximum likelihood (LLR) detector for calculation to restore the sparse symbols containing 0 carried by the subcarrier, and then demodulated by the QAM signal demodulator. The demodulated signal is input to the modulation bit and index bit synthesizer. Using the table lookup method, the k2 modulation bits generate the corresponding k1 index bits, which are synthesized into m bits of information. In this way, each signal is restored. Then, the delay line is used to synthesize the signals into one, and the original Nm bits of information are restored.

[0038] The above completes the secure communication based on 5G chaotic index modulation encryption and decryption.

[0039] like Figure 1 As shown, in this embodiment, a multi-antenna secure communication system based on chaotic scrambling and index modulation in a 5G network includes a transmitting end and a receiving end. The receiving end communicates with the transmitting end through a wireless channel between a 5G transmitting antenna and a 5G receiving antenna. The transmitting end and the receiving end use the same initial conditions to generate the same chaotic sequence for encryption and decryption respectively. The specific connection relationship is as follows:

[0040] The sending end includes:

[0041] Brancher 19, first index bit and modulation bit generator 1-1, second index bit and modulation bit generator 1-2, ..., Nth index bit and modulation bit generator 1-N, first QAM modulator 2-1, second QAM modulator 2-2, ..., Nth QAM modulator 2-N, first index modulator (IM) 3-1, second index modulator (IM) 3-2, ..., Nth index modulator (IM) 3-N, first serial-to-parallel converter 4-1, second serial-to-parallel converter 4-2, ..., Nth serial-to-parallel converter 4-N, first IFFT converter 5-1 , the second IFFT converter 5-2,…, the Nth IFFT converter 5-N, the first parallel-to-serial converter 6-1, the second parallel-to-serial converter 6-2,…, the Nth parallel-to-serial converter 6-N, the first cyclic prefix importer 7-1, the second cyclic prefix importer 7-2, the Nth cyclic prefix importer 7-N, the first chaos generator 10-1, the first chaotic scrambling matrix generator 11-1, the first secret key generator 12-1, the first scrambling circuit module 8-1, the first 5G transmitting antenna 9-1, the second 5G transmitting antenna 9-2,…, the Nth 5G transmitting antenna 9-N.

[0042] The signal is input from the left side to the branching device 19, and the N right ports of the branching device 19 are respectively connected to the left ports of the first index bit and modulation bit generator 1-1, the second index bit and modulation bit generator 1-2, ..., and the Nth index bit and modulation bit generator 1-N, and the right ports of the first index bit and modulation bit generator 1-1, the second index bit and modulation bit generator 1-2, ..., and the Nth index bit and modulation bit generator 1-N are respectively connected to the left ports of the first QAM modulator 2-1, the second QAM modulator 2-2, ..., and the Nth QAM modulator 2-N, and the first index bit and modulation bit generator 1-1, the second index bit and modulation bit generator 1-2, ..., and the Nth index bit and modulation bit generator 1-N are respectively connected to the left ports of the first QAM modulator 2-1, the second QAM modulator 2-2, ..., and the Nth QAM modulator 2-N. The index bits and modulation bit generator 1-2, ..., the Nth index bits and the index bits generated by the modulation bit generator 1-N are respectively transmitted to the upper ports of the first index modulator (IM) 3-1, the second index modulator (IM) 3-2, ..., and the Nth index modulator (IM) 3-N through the upper ports, and each index modulator is controlled to allocate the subcarriers of the modulation bits; the right ports of the first QAM modulator 2-1, the second QAM modulator 2-2, ..., and the Nth QAM modulator 2-N are respectively connected to the first index modulator (IM) 3-1, the second index modulator (IM) 3-2, ..., and the Nth index modulator (IM) 3-N. The left port of the first index modulator (IM) 3-1, the second index modulator (IM) 3-2, ..., the Nth index modulator (IM) 3-N is connected to the left port of the first serial-to-parallel converter 4-1, the second serial-to-parallel converter 4-2, ..., the Nth serial-to-parallel converter 4-N respectively; the right port of the first serial-to-parallel converter 4-1, the second serial-to-parallel converter 4-2, ..., the Nth serial-to-parallel converter 4-N is connected to the left port of the first IFFT converter 5-1, the second IFFT converter 5-2, ..., the Nth IFFT converter 5-N respectively, and the first IFFT converter 5-1, the second IFFT converter 5-2, ..., the Nth The right ports of the N IFFT converters 5-N are respectively connected to the left ports of the first parallel-to-serial converter 6-1, the second parallel-to-serial converter 6-2, ..., and the Nth parallel-to-serial converter 6-N, and the right ports of the first parallel-to-serial converter 6-1, the second parallel-to-serial converter 6-2, ..., and the Nth parallel-to-serial converter 6-N are respectively connected to the left ports of the first cyclic prefix importer 7-1, the second cyclic prefix importer 7-2, ..., and the Nth cyclic prefix importer 7-N, and the right ports of the first cyclic prefix importer 7-1, the second cyclic prefix importer 7-2, ..., and the Nth cyclic prefix importer 7-N are respectively connected to the corresponding left ports of the first scrambling circuit module 8-1.The right port of the first chaos generator 10-1 is connected to the left port of the first chaos scrambling matrix generator 11-1, the right port of the first chaos scrambling matrix generator 11-1 is connected to the left port of the first secret key generator 12-1, the right port of the first secret key generator 12-1 is connected to the lower port of the first scrambling circuit module 8-1, and each right port of the first scrambling circuit module 8-1 is respectively connected to the lower port of the first 5G transmitting antenna 9-1, the second 5G transmitting antenna 9-2, ..., and the Nth 5G transmitting antenna 9-N. The signal is sent out through the first 5G transmitting antenna 9-1, the second 5G transmitting antenna 9-2, ..., and the Nth 5G transmitting antenna 9-N.

[0043] The receiving end includes: a first 5G receiving antenna 9-(N+1), a second 5G receiving antenna 9-(N+2), ..., an Nth 5G receiving antenna 9-2N, a second chaos generator 10-2, a second chaotic scrambling matrix generator 11-2, a second secret key generator 12-2, a second scrambling circuit module 8-2, a first de-pilot cyclic prefix 13-1, a second de-pilot cyclic prefix 13-2, ..., an Nth de-pilot cyclic prefix 13-N, an N+1th serial-to-parallel converter 4-(N+1), an N+2th serial-to-parallel converter 4-(N+2), ..., a 2Nth serial-to-parallel converter 4-2N, a first FFT converter 14-1, a second FFT converter 14-2, ..., a first N FFT converters 14-N, the N+1th parallel-to-serial converter 6-(N+1), the N+2th parallel-to-serial converter 6-(N+2),…, the 2Nth parallel-to-serial converter 6-2N, a minimum mean square error detector (MMSE) 15, a first maximum likelihood detector (LLR) 16-1, a second maximum likelihood detector 16-2,…, the Nth maximum likelihood detector 16-N, a first QAM demodulator 17-1, a second QAM demodulator 17-2,…, the Nth QAM demodulator 17-N, a first index bit and modulation bit synthesizer 18-1, a second index bit and modulation bit synthesizer 18-2,…, the Nth index bit and modulation bit synthesizer 18-N.

[0044] After receiving the signal, the first 5G receiving antenna 9-(N+1), the second 5G receiving antenna 9-(N+2), ..., and the Nth 5G receiving antenna 9-2N send it to the right ports of the second scrambling circuit module 8-2; the right port of the second chaotic generator 10-2 is connected to the left port of the second chaotic scrambling matrix generator 11-2, the right port of the second chaotic scrambling matrix generator 11-2 is connected to the left port of the second key generator 12-2, the right port of the second key generator 12-2 is connected to the upper port of the second scrambling circuit module 8-2, and the left ports of the second scrambling circuit module 8-2 are respectively connected to the first de-cyclic prefix device 13-1, the second de-cyclic prefix device 13-2, ..., the Nth de-cyclic prefix device The right port of the cyclic prefix device 13-N is connected, the left ports of the first decyclic prefix device 13-1, the second decyclic prefix device 13-2, ..., and the Nth decyclic prefix device 13-N are respectively connected to the right ports of the N+1th serial-to-parallel converter 4-(N+1), the N+2th serial-to-parallel converter 4-(N+2), ..., and the 2Nth serial-to-parallel converter 4-2N, the left ports of the N+1th serial-to-parallel converter 4-(N+1), the N+2th serial-to-parallel converter 4-(N+2), ..., and the 2Nth serial-to-parallel converter 4-2N are respectively connected to the right ports of the first FFT converter 14-1, the second FFT converter 14-2, ..., and the Nth FFT converter 14-N, the first FFT converter 14-1, the second The left ports of the FFT converter 14-2, ..., the Nth FFT converter 14-N are respectively connected to the right ports of the N+1th parallel-to-serial converter 6-(N+1), the N+2th parallel-to-serial converter 6-(N+2), ..., the 2Nth parallel-to-serial converter 6-2N, and the left ports of the N+1th parallel-to-serial converter 6-(N+1), the N+2th parallel-to-serial converter 6-(N+2), ..., the 2Nth parallel-to-serial converter 6-2N are respectively connected to the corresponding right ports of the minimum mean square error detector (MMSE) 15, and the left ports of the minimum mean square error detector (MMSE) 15 are respectively connected to the first maximum likelihood detector (LLR) 16-1, the second maximum likelihood detector 16-2, ..., The right port of the Nth maximum likelihood detector 16-N is connected, and the left ports of the first maximum likelihood detector (LLR) 16-1, the second maximum likelihood detector 16-2, ..., and the Nth maximum likelihood detector 16-N are respectively connected to the right ports of the first QAM demodulator 17-1, the second QAM demodulator 17-2, ..., and the Nth QAM demodulator 17-N, and the left ports of the first QAM demodulator 17-1, the second QAM demodulator 17-2, ..., and the Nth QAM demodulator 17-N are respectively connected to the right ports of the first index bit and modulation bit synthesizer 18-1, the second index bit and modulation bit synthesizer 18-2, ..., and the Nth index bit and modulation bit synthesizer 18-N.

[0045] The dotted line between the first and second chaotic signal generators 10 - 1 and 10 - 2 represents that the chaotic signals of the two are coupled and synchronized.

[0046] In this embodiment, the first scrambling circuit module and the second scrambling circuit module may be DSP tms320c66x.

[0047] The principle of the secure communication system of this embodiment will be described below in conjunction with the above system structure.

[0048] In the present invention, the receiving end communicates with the transmitting end through a wireless channel of two 5G transmitting and receiving antennas.

[0049] The transmitter divides the information bits into N paths, each with m bits, by a splitter, and then divides the m-bit information into k1 index bits and k2 modulation bits by an index bit and modulation bit generator. The k2 modulation bits are QAM modulated by a QAM modulator to generate corresponding symbols, and then the k1 index bits are used to control the activation of the k2 subcarriers for modulation in each index modulator.

[0050] After each channel is converted from serial to parallel by the serial-to-parallel converter, it is superimposed on different subcarriers through each inverse fast Fourier transform (IFFT). After the parallel-to-serial converter is used for parallel-to-serial conversion, a cyclic prefix is ​​added in the cyclic prefix device and input into the scrambling circuit module controlled by the secret key generated by chaos. The transmitter generates a high-complexity chaotic signal, generates a scrambling matrix in the scrambling matrix generator, and then generates a secret key in the secret key generator. This secret key is used to control the input and output of each signal in the scrambling circuit module, so as to send it to different 5G antennas. Since the secret key is changed in real time, the encrypted transmission of information can be achieved through its control.

[0051] In this way, due to the unpredictable nature of the chaotic sequence, the attacker cannot restore the sent information in real time if he does not obtain the complete chaotic sequence.

[0052] At the receiving end, the chaos generator synchronized with the transmitting end generates a high-complexity chaotic signal. In the scrambled matrix generator, a scrambled matrix is ​​generated. Then in the key generator, a secret key is generated. This secret key is used to control the input and output of the scrambled circuit module where each 5G receiving antenna receives the signal and exchanges it to the corresponding exit. The cyclic prefix remover of each route removes the cyclic prefix, and after serial-to-parallel conversion by the serial-to-parallel converter, the fast Fourier transform (FFT) is performed using each fast Fourier transform (FFT) device.

[0053] The received information is converted into frequency domain information. After each route parallel-to-serial converter performs parallel-to-serial conversion, it is input into the minimum mean square error detector to eliminate Gaussian channel noise. After obtaining each signal, it is input into the maximum likelihood (LLR) detector for calculation to restore the sparse symbols containing 0 carried by the subcarrier, and then demodulated using the QAM signal demodulator. The demodulated signal is input into the modulation bit and index bit synthesizer. Using the table lookup method, the corresponding k1 index bits are generated from the k2 modulation bits to synthesize into m bits of information. In this way, each signal is restored. Then, the delay line is used to synthesize the signals of each channel into one channel, and the original Nm bits of information are restored.

[0054] The process of realizing communication in the present invention is briefly summarized as follows:

[0055] 1. The transmitter divides the information bits into N paths, each path has m bits, and then the index bit and modulation bit generator divides the m bits of information into k1 index bits and k2 modulation bits.

[0056] 2. Use the QAM modulator to perform QAM modulation on the k2 modulation bits to generate corresponding symbols, and then modulate the k2 subcarriers activated by the k1 index bits in each index modulator.

[0057] 3. After each channel is converted from serial to parallel by a serial-to-parallel converter, it is superimposed on different subcarriers through inverse fast Fourier transform (IFFT).

[0058] 4. Add a cyclic prefix in the cyclic prefixer and input it into the scrambling circuit module controlled by the secret key generated by chaos.

[0059] 5. The transmitter generates a high-complexity chaotic signal, generates a scrambled matrix in the scrambled matrix generator, and then generates a secret key in the secret key generator. This secret key is used to control the input and output of each signal in the scrambled circuit module, and then sent to different 5G antennas.

[0060] 6. The chaos generator synchronized between the receiving end and the transmitting end generates a high-complexity chaotic signal. In the scrambled matrix generator, a scrambled matrix is ​​generated. Then in the key generator, a secret key is generated. This secret key is used to control the input and output of the scrambled circuit module where each 5G receiving antenna receives the signal and exchanges it to the corresponding output.

[0061] 7. Each route has its cyclic prefix removed by a cyclic prefix remover, and after being converted into a serial-to-parallel signal by a serial-to-parallel converter, a fast Fourier transform (FFT) is performed by a fast Fourier transform (FFT) device of each route.

[0062] 8. Input to the minimum mean square error detector to eliminate Gaussian channel noise. After obtaining each signal, input to the maximum likelihood (LLR) detector for calculation to restore the sparse symbols containing 0 carried by the subcarrier, and then use the QAM signal demodulator for demodulation. The demodulated signal is input to the modulation bit and index bit synthesizer. Using the table lookup method, the corresponding k1 index bits are generated from the k2 modulation bits to synthesize into m bits of information. In this way, each signal is restored, and then the delay line is used to synthesize the various signals into one, and the original Nm bits of information are restored.

[0063] The preferred embodiments and principles of the present invention are described in detail above. For those skilled in the art, according to the ideas provided by the present invention, there may be changes in the specific implementation methods, and these changes should also be regarded as the protection scope of the present invention.

Claims

1. A multi-antenna secure communication system based on chaotic scrambling and index modulation in a 5G network includes a transmitting end and a receiving end, wherein the receiving end communicates with the transmitting end through a wireless channel between a 5G transmitting antenna and a 5G receiving antenna, and is characterized in that: The transmitting end includes a brancher, N index bits and modulation bit generators, N QAM modulators, N index modulators, N serial-to-parallel converters, N IFFT converters, N parallel-to-serial converters, N cyclic prefix importers, a first chaos generator, a first chaotic scrambling matrix generator, a first secret key generator, a first scrambling circuit module, and N 5G transmitting antennas; the N ports of the brancher are respectively connected to the N input ports of the first scrambling circuit module through the N index bits and modulation bit generators, N QAM modulators, N index modulators, N serial-to-parallel converters, N IFFT converters, N parallel-to-serial converters, and N cyclic prefix importers; the index bits generated by the N index bits and modulation bit generators are respectively transmitted to the N index modulators; the first chaos generator is connected to the first scrambling circuit module through the first chaotic scrambling matrix generator and the first secret key generator in turn; The N output ports of the first scrambling circuit module are respectively connected to N 5G transmitting antennas; The receiving end includes N 5G receiving antennas, a second chaos generator, a second chaos scrambling matrix generator, a second secret key generator, a second scrambling circuit module, N cyclic prefix removal devices, N serial-to-parallel converters, N FFT converters, N parallel-to-serial converters, a minimum mean square error detector, N maximum likelihood detectors, N QAM demodulators, and N index bits and modulation bit synthesizers; the second chaos generator is connected to the second scrambling circuit module through the second chaos scrambling matrix generator and the second secret key generator in turn; the N input ports of the second scrambling circuit module are connected to the N 5G receiving antennas, and the N output ports of the second scrambling circuit module are connected to the N input ports of the minimum mean square error detector through N cyclic prefix removal devices, N serial-to-parallel converters, N FFT converters, and N parallel-to-serial converters in turn, and the N output ports of the minimum mean square error detector are connected to the N index bits and modulation bit synthesizer through N maximum likelihood detectors and N QAM demodulators in turn; At the transmitting end, the splitter divides the signal bits into N paths, each path has m bits, and the m bits of information are divided into k1 index bits and k2 modulation bits through the index bit and modulation bit generator; the QAM modulator performs QAM modulation on the k2 modulation bits to generate corresponding symbols; in the N index modulators, the k2 subcarriers activated by the k1 index bits are modulated; At the transmitting end, each channel is converted from serial to parallel by a serial-to-parallel converter and then superimposed on different subcarriers through inverse fast Fourier transform; At the transmitting end, after parallel-to-serial conversion through the parallel-to-serial converter, a cyclic prefix is ​​added in the cyclic prefixer and input into the scrambling circuit module controlled by the secret key generated by chaos; At the transmitting end, the chaos generator generates a high-complexity chaotic signal, generates a scrambled matrix in the scrambled matrix generator, and then generates a secret key in the secret key generator. This secret key is used to control the input and output of N signals in the scrambled circuit module and send them to different 5G antennas.

2. The multi-antenna secure communication system based on chaotic scrambling and index modulation in a 5G network as claimed in claim 1, characterized in that: At the receiving end, the chaos generator synchronized with the transmitting end generates a high-complexity chaotic signal, generates a scrambled matrix in the scrambled matrix generator, and then generates a secret key in the secret key generator. This secret key is used to control the input and output of the scrambled circuit module where the N 5G receiving antennas receive the signal and exchange it to the corresponding output port.

3. The multi-antenna secure communication system based on chaotic scrambling and index modulation in a 5G network as claimed in claim 2, characterized in that: At the receiving end, the cyclic prefix is ​​removed by the pilot cyclic prefix remover of each route, and after the serial-to-parallel conversion by the serial-to-parallel converter, the fast Fourier transform is performed by the fast Fourier transformer to convert the received information into frequency domain information.

4. The multi-antenna secure communication system based on chaotic scrambling and index modulation in a 5G network as claimed in claim 3, characterized in that: At the receiving end, after each route parallel-to-serial converter performs parallel-to-serial conversion, it is input into the minimum mean square error detector to perform statistical calculation of the minimum mean square error of the received signal. After obtaining each signal, it is input into the maximum likelihood detector. By calculating the maximum likelihood function, the sparse symbols containing 0 carried by the subcarrier are restored, and then demodulated using the QAM signal demodulator.

5. The multi-antenna secure communication system based on chaotic scrambling and index modulation in a 5G network as claimed in claim 4, characterized in that: At the receiving end, the demodulated signal is input to the index bit and modulation bit synthesizer, and the corresponding k1 index bits are generated from the k2 modulation bits by looking up the table using the set mapping relationship table between the index bits and the modulation bits, and synthesized into m bits of information.

6. The multi-antenna secure communication system based on chaotic scrambling and index modulation in a 5G network as claimed in claim 5, characterized in that: At the receiving end, each restored signal is combined into one signal using a delay line to restore the original Nm bits of information.

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