Semiconductor device and method for manufacturing semiconductor device

Abstract

A semiconductor device (1) is provided. The semiconductor device (1) may include: a drift region (11, 111, 13, 14, 15) of a first conductivity type; a channel region (8, 108) of a second conductivity type on the drift region (11, 111, 13, 14, 15), wherein the second conductivity type is opposite to the first conductivity type; a source region (9, 109) of the first conductivity type on the channel region (8, 108); a trench (5) forming an insulating gate and extending through the source region (9, 109) and the channel region (8, 108), such that the bottom of the trench is located at the drift region (11, 1 11, 13, 14, 15); at least one buried region (12) of the second conductivity type, wherein the buried region extends from an edge region of the drift region (11, 111, 13, 14, 15) to the trench (5) within the drift region (11, 111, 13, 14, 15) and is in direct contact with a first partial region (32) of the surface of the trench (5), wherein a second partial region (34) of the surface of the trench (5) is in direct contact with the drift region (11, 111, 13, 14, 15), and wherein the buried region (12) is conductively connected to the source region (9, 109).

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device. Background Art

[0002] In field-effect transistors (e.g., MOSFETs, such as silicon carbide MOSFETs (SiC-MOSFETs)) having a gate configured as a trench structure (also referred to as a trench structure; the terms trench and trench are used synonymously herein), a deep p+ structure is generally preferably used to shield the trench structure, which extends laterally adjacent to the trench and, if necessary, is also formed in an L-shaped manner with buried legs below the trench. For this, see, for example, US 8,946,726 B2. An alternative approach uses the implantation of a p-region below the trench (as a so-called "bubble"), for example, by implantation through the trench. (e.g., US 2018 / 0097 079 A1).

[0003] Conventional field shields show a trade-off between (lowest possible) stress and (lowest possible) resistance on the gate oxide when current flows through the drift region of a MOSFET (eg, through a JFET region that can be formed within the drift region).

[0004] The object of the present invention is to provide a semiconductor device or a method for producing such a semiconductor device which provides the highest possible protection for the gate oxide while at the same time allowing the current flow through the semiconductor device to be as unimpaired as possible. Summary of the Invention

[0005] According to one aspect of the present invention, this object is achieved by a semiconductor device comprising: a drift region of a first conductivity type; a channel region of a second conductivity type on the drift region; a source region of the first conductivity type on or in the channel region; a trench forming an insulated gate and extending through the source region and the channel region, such that the bottom of the trench is located in the drift region; and at least one buried region of the second conductivity type, extending within the drift region from an edge region of the drift region to the trench and in direct contact with a first subregion of a surface of the trench. The second conductivity type can be opposite to the first conductivity type, the second subregion of the surface of the trench can be in direct contact with the drift region, and the buried region can be electrically conductively connected to the source region.

[0006] Obviously, the semiconductor device can be designed as a field effect transistor, such as a MOSFET, in which the gate shield is provided as a buried region extending as far as the gate oxide, so that the gate oxide is particularly well protected there. However, the buried region is designed such that it contacts the trench only over a portion of its length, so that a region remains in which the (vertical) current flow is not impaired or only insignificantly impaired due to the (horizontally arranged) buried region.

[0007] According to another aspect of the present invention, the object is achieved by a method for manufacturing a semiconductor device, the method comprising: forming a drift region of a first conductivity type; forming a channel region of a second conductivity type on the drift region; forming a source region of the first conductivity type on or in the channel region; forming a trench, which forms an insulated gate and extends through the source region and the channel region, such that the bottom of the trench is located in the drift region; forming at least one buried region of the second conductivity type, which extends within the drift region from an edge region of the drift region to the trench and is in direct contact with a first partial region of a surface of the trench; and electrically conductively connecting the buried region to the source region. The second partial region of the surface of the trench may be in direct contact with the drift region, and the second conductivity type may be opposite to the first conductivity type.

[0008] Obviously, a field effect transistor, such as a MOSFET, having the above-mentioned characteristics is formed by this method.

[0009] In various embodiments, semiconductor devices, such as drift regions and, if necessary, other regions such as source regions, channel regions, and / or buried regions, can be composed of silicon carbide (SiC). Thus, in various embodiments, a SiC trench MOSFET with effective shielding of its gate oxide can be provided.

[0010] In various embodiments, a MOSFET is provided with effective shielding of its trench oxide while limiting the saturation current through an effective JFET effect.

[0011] In various embodiments, the buried region may extend below the trench. This allows the buried region to partially surround the trench bottom and, in particular, the trench edge in the rounded corner region, which results in particularly effective field shielding of the trench bottom or trench edge.

[0012] In various embodiments, the buried region can extend from an edge region of the drift region to the trench on a first side of the trench and from an edge region of the drift region to the trench on an opposite side of the trench, and each region can be in direct contact with a first partial region of the surface of the trench. This arrangement can be used, for example, as an interlaced structure, such that a higher density of shielding regions is provided below the trench, while the spacing between the buried regions is sufficiently wide in the third dimension for good current flow in the on-state condition. Thus, effective field shielding at the trench bottom can be achieved by the interdigital structure of the buried regions, with good current flow in the on-state condition.

[0013] In various embodiments, a buried region extending from the edge region to the trench on two opposite sides of the trench can also mean that there is justification invariance in the direction of the trench axis and a large overlap between the trench and the buried region in a direction perpendicular to the trench, which means that the configuration of the semiconductor device can be very tolerant to misalignment. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Developments of these aspects are shown in the dependent claims and the description. Embodiments of the invention are shown in the drawings and explained in more detail in the following description. The drawings show:

[0015] Figure 1 schematically illustrates a semiconductor device according to one embodiment;

[0016] Figure 2 schematically illustrates a semiconductor device according to one embodiment;

[0017] Figure 3 Schematically shown Figure 1 or Figure 2 A top view of a cross section of a semiconductor device in the direction of an arrow shown therein;

[0018] Figures 4A to 4I A schematic illustration of a method for manufacturing a semiconductor device according to one embodiment is shown;

[0019] Figures 5A to 5I A schematic illustration of a method for manufacturing a semiconductor device according to one embodiment is shown;

[0020] Figure 6 A flow chart of a method for manufacturing a semiconductor device according to one embodiment is shown. DETAILED DESCRIPTION

[0021] Figure 1 and Figure 2each shows a schematic cross-sectional view of a semiconductor device 1 according to one embodiment, Figure 3 Show Figure 1 or Figure 2 Schematic top view of a cross section of the semiconductor device in the direction of the arrow shown there. Figure 2 It may be a preferred embodiment of the semiconductor device 1 .

[0022] In the semiconductor device 1, some regions have a first conductivity type and other regions have a second conductivity type opposite to the first conductivity type. In the embodiment described below, the regions of the first conductivity type are n-doped and the regions of the second conductivity type are p-doped. In other embodiments not shown, the conductivity types can be completely opposite.

[0023] As in Figure 1 and Figure 2 As shown in FIG, a semiconductor device 1 may include a substrate 16, such as a SiC substrate or another wide-bandgap semiconductor substrate, which may be n-doped. The semiconductor device 1 is also referred to herein as a cell. The cell may be divided into two half-cells by a trench 5, which will be described further below. An n-doped drift region (in the narrow sense) 15 may be formed above, for example, on, the substrate 16. An n-doped region 14, hereinafter also referred to as an n-extension FET region 14, may be arranged above, for example, on, the substrate 16. At least one n-doped region 13 (hereinafter also referred to as an nJFET region 13) and at least one p-doped buried region 12 may be arranged side by side, for example, in a common plane. Above, for example, on, the n-doped regions 11, 111, hereinafter also referred to as n-extension regions 11, 111, may be arranged above, for example, on, the substrate 16. For example, the n-extension regions 11, 111 may be formed as a single layer, with the n-extension region being labeled 111 in the left cell half and 11 in the right cell half. Above, for example, p-doped channel regions 8, 108 (also referred to as body regions) can be arranged, again as two half-cells. On or in the channel regions 8, 108, n-doped source regions 9, 109 can be formed as two half-cells. The drift region 15, n-extension FET region 14, n-JFET region 13, and n-extension regions 11, 111 can be collectively understood as a drift region in a broad sense.

[0024] The semiconductor device 1 may further comprise a trench 5 extending from the upper side of the semiconductor device 1, for example from the surface of the source region 9, 109 through the source region 9, 109 and the channel region 8, 108 into the drift region (in a broad sense). For example, the bottom of the trench 5 may be located in the region where the nJFET region 13 and the p-doped buried region 12 adjoin each other, so that the surface of the trench 5 contacts not only the nJFET region 13 but also the buried region 12. In various embodiments, for example, as in Figure 1 、 2 As shown in Figures 3, 4I, and 5I, at least one buried region 12 may have a portion located below the trench 5. The area of ​​the surface of the trench 5 that contacts the buried region 12 is referred to as a first partial region 32. The area of ​​the surface of the trench 5 that contacts the nJFET region 13 is referred to as a second partial region 34. The trench 5 may have gate oxides 6 and 7 on its walls, wherein the gate oxide 7 may refer to the gate oxide on the bottom of the trench 5, which may be thicker than the gate oxide 6 on the sidewalls of the trench 5. The trench 5 may also have a gate electrode 4, which may be formed of polysilicon, for example. Figure 1 and Figure 2 Also shown is an optional additional p-doped shielding region 17 directly adjacent to the trench bottom (eg formed below trench 5). Although gate electrode 4 and gate oxides 6, 7 can be considered to belong to trench 5, the trench is collectively labeled with reference numeral 5 here.

[0025] In the semiconductor device 1, the buried region 12 can be electrically conductively connected to the source regions 9, 109. For this purpose, the p-type electrodes extending parallel to the trench 5 are connected to the buried region 12 in an electrically conductive manner. + The doped regions 10, 110 can be arranged in the edge region of each of the half cells of the semiconductor device 1: identically doped adjoining regions are electrically conductively connected to one another and thus form an electrically conductive connection. Figure 1 As shown in + The doped regions 10, 110 and / or their tails 21, 121 can extend into the buried region 12, whereby their doping overlaps with the doping of the buried region. Figure 1 In the left half of the unit, it looks like p + The doped region 110 extends only into the n-doped nJFET region 13. However, Figure 3 The schematic diagram in FIG. 1 shows that, in the direction perpendicular to the paper plane, multiple nJFET regions 13 and multiple buried regions 12 can alternate with each other not only in the left half cell but also in the right half cell. This means that the p below or above the paper plane + The doped region 110 may be in conductive contact with (at least) another buried region 12. In the semiconductor device 1, the trench 5 is always larger than the p + The doped regions 10, 110 and their tails 12, 121 are deeper.

[0026] exist Figure 2 In the embodiment, p + The doped regions 10, 110 can be configured such that the p + The doped regions do not extend into the buried region 12 but only into the n extension regions 11, 111. + The electrically conductive connection between the doped regions 10, 110 can be made, for example, by means of p-doped connecting regions 18, 118 (the p-doped connecting region 118 is located at Figure 2 is not visible in the image because it is outside the plane of the paper, but it is visible in the image Figures 4B to 4I This is shown in Figure 2 、 Figure 4I and Figure 5I Here, it may be advantageous to have a + The depth of the trench 5 extending deeper in the doped region 10 , 110 is no longer determined by the p + The depth of the doped region 10 , 110 or its tail 21 , 121 is determined.

[0027] With p + Similar to the p-doped regions 10, 110, the p-doped connection regions 18, 118 can extend parallel to the trench 5 over its entire length (this is the case in Figure 4I ), or may be formed parallel to the trench 5 only in one or more sections of the entire length, for example only above the buried region 12. Figure 5I , the right part of the figure shows a side view (in the direction of the arrow) of the semiconductor device 1 depicted on the left, which makes it possible to recognize the columnar configuration of the connection region 18 .

[0028] By means of the column-shaped embodiment of the connection region 18 (pJFET contact region), a lateral connection is produced in the n-type extension regions 11 , 111 between adjacent semiconductor devices 1 (cells), see also Figure 5I side view, which additionally increases the on-resistance R on P + The doped regions 10 , 110 and the connection regions 18 , 118 become less sensitive to adjustment tolerances relative to the trench 5 , since lateral compensation currents between adjacent cells can be achieved or simplified.

[0029] The portion of the conductive connection between the at least one buried region 12 and the source regions 9, 109 extending through the semiconductor may be referred to as a connection region. Figure 1 In the embodiment with p + The doped regions 10, 110 (and optionally also the tails 21, 121) are Figure 2 、 Figure 4I and Figure 5I In the embodiment with p + doped regions 10 , 110 (optionally also with tails 21 , 121 ) and p-doped connection regions 18 , 118 .

[0030] The shielding area 17 can be formed by burying the area 12 (which may have "fishbone" ” structure) and the p+ doped regions 10, 110 (and optionally with connection regions 18, 118) are electrically connected to the source potential and therefore represent additional shielding for the gate oxide 6, 7 against the high electric fields that occur at high voltages between the drain 3 and the source 2, 102.

[0031] For an electrically conductive connection between the at least one buried region 12 and the source regions 9 , 109 , at least one metallization 2 , 102 may also be arranged on the upper side of the semiconductor device, for example between the source regions 9 , 109 and p + The metallization can extend over the channel region 8, 108 on the doped region 10, 110. The metallization 2, 102 is at source potential. The contact between the metallization 2, 102 and the semiconductor located thereunder forms an ohmic contact. In an embodiment with a shielding region 17, the metallization can be formed by the buried region 12 and the p-type semiconductor. + The doped regions 10 , 110 are connected to a source potential.

[0032] The semiconductor device can also have a back contact 3 at drain potential, which is in contact with the substrate 16 .

[0033] In various embodiments, the semiconductor device 1 may further include an edge terminal and a gate pad (both not shown here) for receiving a cutoff voltage in a lateral direction.

[0034] As in Figure 3 As indicated in , a plurality of semiconductor devices 1 may be formed adjacent to one another and form a common active region (semiconductor device).

[0035] exist Figure 1 The buried region 12 is shown extremely schematically in FIG5 . Figure 3 In the trench 5 (or the optional shielding area 17 located directly below it and the p + The positions of the doped regions 10, 110 are indicated by dashed lines. It can be seen that the active region consists of preferably identical stripe-shaped MOSFETs arranged parallel to one another.

[0036] In various embodiments, the at least one buried region 12 can be formed as a plurality of buried regions 12, for example strips. These strips can be embedded in the n-doped nJFET region 13. This means that the first sub-region 32 has a plurality of first sub-region segments, wherein the second sub-region 34 is located between two of the first sub-region segments.

[0037] In various embodiments, the buried region 12 may be arranged such that it extends from the edge region to the trench 5 only on one side of the trench 5. In various embodiments, the buried region 12 may extend from the edge region to the trench 5 on both sides of the trench 5, for example Figure 3 As shown in . Each of the buried regions 12 can be formed so that it encloses an angle φ with the longitudinal direction of the trench 5, wherein 0°<φ≤90° can be. A preferred value can be φ=45°±5°, or for example around 30° or around 60°. All buried regions 12 located on the same side of the trench 5 can be arranged at the same angle φ, i.e. parallel to each other. In various embodiments, the buried regions 12 on one side of the trench 5 are arranged at an angle φ1 (in Figure 3 The left side of the right trench 5) may be different from the angle φ2 formed by the buried region 12 on the other side of the trench 5 (at Figure 3 For example, it can be φ1 = 60° and φ2 = 30°, as in Figure 3 In various embodiments, φ1 may be equal to φ2 (not shown). In various embodiments, φ1 and φ2 may be adjacent angles, such as in Figure 3 In this case, the buried region 12 can form a "fishbone" structure. The arrangement of the buried region 12, such as the fishbone structure, can continue periodically in parallel and perpendicular to the trench 5 in the lateral direction (preferably), and can be constructed in the entire active area. Figure 3 In the embodiment shown in , the buried region 12 extends in two directions that are neither parallel nor perpendicular to the trench 5 , or even in three directions in the presence of an additional shielding structure 17 .

[0038] In various embodiments, it is also possible that the buried region 12 contains additional strips which are arranged on the p + The doped regions 10 , 110 extend below and parallel to the trench 5 at a distance therefrom.

[0039] For example, the source potential at the metallization 2, 102 can be at a reference potential. In the case of a high drain voltage at the back contact 3 and a gate voltage below the threshold voltage, due to the doping ratio, the space charge zone can extend from the boundary between the p- and n-regions substantially into the n-doped regions, for example, into the n-extension regions 11, 111, the nJFET region 13, the n-extension FET region 14, and the drift region 15. The at least one buried region 12 (and, if necessary, the shielding structure 17) can then have the task of protecting the gate oxide 6, 7 from high fields. Effective field shielding of the bottom of the trench 5, and in particular of the edges of the trench 5 in its rounded corners, can be achieved by partial enclosure by the (p-doped) buried region 12 and, if necessary, the shielding structure 17.

[0040] In the on-state with a gate voltage above the threshold voltage, a reverse channel can be induced on the trench-side surface of the channel region 8, 108 (body region), so that a current flows from the drain 3 via the substrate 16, the drift region (in the narrow sense) 15, the n-extension FET region 14, the nJFET region 13, the n-extension region 11, 111, the channel region 8, 108 and the source region 9, 109 to the (source) metallization 2, 102. In various embodiments, the resistance can be reduced, for example, by The nJFET region 13 is configured to be narrower (eg, flatter) and is more highly doped.

[0041] Figures 4A to 4I A schematic illustration of a method for producing a semiconductor device, for example one of the semiconductor devices 1 described above, is shown according to one embodiment.

[0042] In accordance with Figures 4A to 4I In the method, the so-called double extension concept is applied. For the sake of simplicity, here or in Figures 5A to 5I Not shown is the n-extension FET region 14 which can be produced during the first epitaxy or as a deep implant after the first epitaxy.

[0043] Based on the first epitaxial layer (drift region in a narrow sense) 15 ( Figure 4A ) of a (e.g. SiC) wafer substrate 16 (the thickness and doping concentration of the first epitaxial layer depend on the desired breakdown voltage of the semiconductor device 1), the nJFET region 13 and at least one (e.g. pJFET) buried region 12 can be defined by ion implantation. Then, a second epitaxial layer 118, 18, 19 can be applied over the entire face of these structures. It can be p-doped in the lower part and n-doped in the upper part ( Figure 4B ), the lower portion forms the connection regions 18, 118 in the completed semiconductor device. Subsequently, p +The doped regions 10, 110 can be produced by means of ion implantation in such a way that p + The doped region extends into or onto the p-doped buried region 12 of the second epitaxial layer ( Figure 4C ). Subsequently, an implantation for the channel region (body region) 8, 108 may be performed ( Figure 4D ) and the following injection: the injection will remove p + The p-doped regions of the second epitaxial layer outside the doped regions 10, 100 are further doped to form n-doped n-extension regions 1, 111 ( Figure 4E ). This also enables the generation of connection regions (pJFET contact regions) 18, 118. Subsequently, the implantation ( Figure 4F ), the structure of groove 5 ( Figure 4G ) and, if necessary, an additional shielding region below the trench can be produced by implantation into the trench 5 ( Figure 4H ). The trench sidewalls can be protected by a protective layer during the implantation. Then, after trench annealing, the trench 5 can be filled and metallization can be applied to the front side and back side as drain contact 3, gate contact (neither shown) and source contact ( Figure 4I ). In principle, the order of implantation for the channel regions 8, 108 and the source regions 9, 109 can be interchanged with one another.

[0044] Figures 5A to 5I A schematic illustration of a method for producing a semiconductor device, for example one of the semiconductor devices 1 described above, is shown according to one embodiment.

[0045] In accordance with Figures 5A to 5I In the method shown, the so-called triple epitaxial concept can be applied. The wafer substrate 16 can be connected to Figure 4A The wafer substrate in the substantially corresponding ( Figure 5A ), comprising a first epitaxial layer. Then, an nJFET region 13 and at least one (e.g. pJFET) buried region 12 may be defined by ion implantation. The n extension region 11, 111 may be applied as a second epitaxial layer above the first epitaxial layer ( Figure 5B The connection regions (pJFET contact regions) 18, 118 can be produced by implantation into the second epitaxial layer ( Figure 5C Then, a third epitaxial layer 19, preferably n-doped, may be grown on the surface of the second epitaxial layer ( Figure 5D ).p + The production of the doped regions 10, 100 can be carried out by means of ion implantation. Then the implantation for the source regions 9, 109 can be carried out ( Figure 5E ), and perform p + The third epitaxial layer 19 outside the doped regions 10, 100 is re-doped to form the channel regions 8, 108 ( Figure 5F ). The structure of groove 5 ( Figure 5G ) and, if necessary, the generation of an additional shielding region 17 below the trench 5 can be generated by implantation into the trench 5 ( Figure 5H ). The trench sidewalls can be protected by a protective layer during the implantation. Then, after trench annealing, the trench 5 can be filled and metallization can be applied to the front side and the back side as drain contact 3, gate contact (both not shown) and source contact ( Figure 5I ). In principle, the order of implantation for the channel regions 8, 108 and the source regions 9, 109 can be interchanged with one another.

[0046] Contact can be achieved using the contact production and metallization methods customary in SiC technology, for example by alloying (einlegiert) Ni contacts on the front side and back side of the semiconductor device 1 with a sufficient thermal budget and then applying metallizations 2, 3, for example a front side metallization 2 based on Al or Cu and a back side (drain) metallization 3 based on Pd / Au.

[0047] Figure 6 A flow chart 60 is shown of a method for manufacturing a semiconductor device according to one embodiment.

[0048] The method may include: forming a drift region of a first conductivity type (in 61); forming at least one buried region of a second conductivity type (in 62); forming a channel region of the second conductivity type on the drift region (in 63); forming a source region of the first conductivity type on or in the channel region (in 64); forming a trench that forms an insulating gate and extends through the source region and the channel region, so that the bottom of the trench is located in the drift region (in 65); and conductively connecting the buried region to the source region, wherein at least one buried region extends from an edge region of the drift region to the trench within the drift region and can be in direct contact with a first portion of the surface of the trench, wherein a second portion of the surface of the trench can be in direct contact with the drift region, and the second conductivity type can be opposite to the first conductivity type (in 66).

[0049] Further advantageous embodiments of the method result from the description of the device and vice versa.

[0050] Furthermore, method steps according to the present invention can be repeated and performed in a sequence different from that described.

[0051] If an embodiment includes an “and / or” connection between a first feature and a second feature, this should be interpreted as meaning that the embodiment according to one embodiment has both the first feature and the second feature, and according to another embodiment has either only the first feature or only the second feature.

Claims

1. A semiconductor device (1), comprising: A drift region (11, 111, 13, 14, 15) of a first conductivity type; A second conductivity type channel region (8, 108) on the drift region (11, 111, 13, 14, 15), wherein The second conductivity type is opposite to the first conductivity type; a source region (9, 109) of the first conductivity type on or in the channel region (8, 108); a trench (5), the trench forming an insulating gate and extending through the source region (9, 109) and the channel region (8, 108) so that the bottom of the trench is located in the drift region (11, 111, 13, 14, 15); at least one buried region (12) of the second conductivity type, extending from an edge region of the drift region (11, 111, 13, 14, 15) to the trench (5) in the drift region (11, 111, 13, 14, 15) and in direct contact with a first partial region (32) of a surface of the trench (5), wherein a second partial region (34) of the surface of the trench (5) is in direct contact with the drift region (11, 111, 13, 14, 15), wherein the buried region (12) is conductively connected to the source region (9, 109), wherein the at least one buried region (12) comprises a plurality of buried regions (12); wherein the first partial region (32) of the surface of the groove (5) has a plurality of first partial region sections, wherein the second partial region (34) is located between the first partial region sections, wherein the groove extends in a longitudinal direction and in a transverse direction perpendicular to the longitudinal direction, wherein the groove (5) extends longer in the longitudinal direction than in the transverse direction; wherein the first partial region section is arranged along the longitudinal direction on a first side surface of the groove (5) and on a second side surface of the groove (5) opposite the first side surface, wherein each of the buried regions (12) encloses an angle with the longitudinal direction of the trench (5), wherein the buried region (12) in contact with the first partial area section on the first side surface encloses a first angle φ1 with the longitudinal direction of the trench (5), wherein the buried region (12) in contact with the first partial region section on the second side surface encloses a second angle φ2 with the longitudinal direction of the trench (5), Here, for 0°<α<45°, φ1=45°+α and φ2=45°-α.

2. The semiconductor device (1) according to claim 1, in, The at least one buried region (12) extends below the trench (5).

3. The semiconductor device (1) according to claim 1 or 2, in, The first partial area sections are arranged alternately along the longitudinal direction on the first side surface and the second side surface of the groove (5).

4. The semiconductor device (1) according to claim 1 or 2, wherein α＝5°。 5. The semiconductor device (1) according to claim 1 or 2, in, The conductive connection between the buried region (12) and the source region (9, 109) has a connection region of the second conductivity type, which extends between the upper surface of the channel region (8, 108) and the buried region (12).

6. A method for manufacturing a semiconductor device, the method comprising: forming a drift region (11, 111, 13, 14, 15) of a first conductivity type; At least one buried region (12) of a second conductivity type is formed; and a channel region (8, 108) of the second conductivity type is formed on the drift region (11, 111, 13, 14, 15), wherein: The second conductivity type is opposite to the first conductivity type; forming a source region (9, 109) of the first conductivity type on or in the channel region (8, 108); forming a trench (5), the trench forming an insulating gate and extending through the source region (9, 109) and the channel region (8, 108) so that the bottom of the trench is located in the drift region (11, 111, 13, 14, 15); wherein the at least one buried region extends from an edge region of the drift region (11, 111, 13, 14, 15) to the trench in the drift region (11, 111, 13, 14, 15) and is in direct contact with a first partial region (32) of the surface of the trench (5); wherein a second partial region (34) of the surface of the trench (5) is in direct contact with the drift region (11, 111, 13, 14, 15); Conductively connecting the buried region (12) to the source region (9, 109), wherein the at least one buried region (12) comprises a plurality of buried regions (12); wherein the first partial region (32) of the surface of the groove (5) has a plurality of first partial region sections, wherein the second partial region (34) is located between the first partial region sections, wherein the groove extends in a longitudinal direction and in a transverse direction perpendicular to the longitudinal direction, wherein the groove (5) extends longer in the longitudinal direction than in the transverse direction; wherein the first partial region section is arranged along the longitudinal direction on a first side surface of the groove (5) and on a second side surface of the groove (5) opposite the first side surface, wherein each of the buried regions (12) encloses an angle with the longitudinal direction of the trench (5), wherein the buried region (12) in contact with the first partial area section on the first side surface encloses a first angle φ1 with the longitudinal direction of the trench (5), wherein the buried region (12) in contact with the first partial region section on the second side surface encloses a second angle φ2 with the longitudinal direction of the trench (5), Here, for 0°<α<45°, φ1=45°+α and φ2=45°-α.

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