An LDO circuit to solve the LDO power-on transition

Abstract

The present invention discloses an LDO circuit for solving the power-on transition of LDO, comprising: a time control system T1, a switch K2 and a voltage limiting module D1, a compensation circuit is connected in parallel between the output end of the operational amplifier opa and the load end vout; the input end of the time control system T1 is connected to the power supply VDD end, the output end of the time control system T1 is grounded, the input end of the switch K2 is connected to the power supply VDD end, the control end of the switch K2 is connected to the common end of the time control system T1, and the output end of the switch K2 is connected to the common end of the compensation circuit after the voltage limiting module D1; the time control system T1 is used to control the delay opening and closing of the switch K2 after power-on. The present invention provides an LDO circuit for solving the power-on transition of LDO, which avoids the output end voltage of the LDO from outputting a voltage value exceeding our predetermined value during the VDD power-on stage.

Description

Technical Field

[0001] The invention relates to an LDO circuit for solving LDO power-on transition, belonging to the technical field of semiconductor integrated circuit manufacturing. Background Art

[0002] With the development of science and technology, semiconductor devices are becoming more and more widely used due to their own characteristics and advantages. LDO is a linear regulator that uses a transistor or field effect transistor (FET) operating in its saturation region to subtract excess voltage from the applied input voltage to generate a regulated output voltage.

[0003] LDO is widely used in analog integrated circuits. However, during the power-on process, the operational amplifier has not yet entered a stable working state, resulting in the LDO being unable to control the output voltage. In some cases, the output voltage will directly rise with the power supply voltage. The LDO may output a voltage exceeding the predetermined voltage during the power-on process, causing the output voltage to exceed the safe power consumption standard of the LDO load circuit. Summary of the invention

[0004] Purpose: In order to overcome the problem in the prior art that the output voltage of the power supply VDD is too high during the LDO power-on process, the present invention provides an LDO circuit for solving the LDO power-on transition problem.

[0005] Technical solution: To solve the above technical problems, the technical solution adopted by the present invention is:

[0006] In a first aspect, an LDO circuit for solving LDO power-on transition includes an LDO circuit, wherein the LDO circuit includes: an operational amplifier opa, a compensation circuit, and also includes: a timing control system T1 and a switch K2, wherein a compensation circuit is connected in parallel between an output end of the operational amplifier opa and a load end vout; an input end of the timing control system T1 is connected to a power supply VDD end, an output end of the timing control system T1 is grounded, an input end of the switch K2 is connected to a power supply VDD end, a control end of the switch K2 is connected to a common end of the timing control system T1, and an output end of the switch K2 is connected to a common end of the compensation circuit; the timing control system T1 is used to control the delayed opening and closing of the switch K2 after power-on.

[0007] In a second aspect, an LDO circuit for solving LDO power-on transition includes an LDO circuit, wherein the LDO circuit includes: an operational amplifier opa, a compensation circuit, and also includes: a timing control system T1 and a switch K2, wherein a compensation circuit is connected in parallel between the output end of the operational amplifier opa and a load end vout; the input end of the timing control system T1 is connected to a power supply VDD end, the output end of the timing control system T1 is grounded, the input end of the switch K2 is connected to the power supply VDD end, the control end of the switch K2 is connected to a common end of the timing control system T1, and the output end of the switch K2 is connected to the output end of the operational amplifier opa; the timing control system T1 is used to control the delayed opening and closing of the switch K2 after power-on.

[0008] As a preferred solution, it further includes: a voltage limiting module D1, and the output end of the switch K2 is connected to the common end of the compensation circuit through the voltage limiting module D1.

[0009] As a preferred solution, it further includes: a voltage limiting module D1, and the output end of the switch K2 is connected to the output end of the operational amplifier opa through the voltage limiting module D1.

[0010] As a preferred solution, the compensation circuit includes a compensation resistor R1 and a compensation capacitor C1. The output end of the operational amplifier opa is connected to the load end vout through a series branch of the compensation resistor R1 and the compensation capacitor C1. The common end of the compensation circuit is the common end of the compensation resistor R1 and the compensation capacitor C1.

[0011] As a preferred solution, the compensation circuit includes a compensation capacitor C1, and the output end of the operational amplifier opa is connected to the load end vout through the compensation capacitor C1.

[0012] As a preferred solution, the LDO circuit also includes a switch K1, the positive input terminal of the operational amplifier opa is connected to the reference voltage V_bias, the power supply terminal of the operational amplifier opa is connected to the power supply VDD, the ground terminal of the operational amplifier opa is grounded, the output terminal of the operational amplifier opa is connected to the control terminal of the switch K1, the source terminal of the switch K1 is connected to the power supply VDD, the output terminal of the switch K1 is connected in series with the resistor R2 and the resistor R3 in sequence and then grounded, the common terminal of the resistor R2 and the resistor R3 is connected to the negative input terminal of the operational amplifier opa, a capacitor C2 is provided between the output terminal of the switch K1 and the ground, and a compensation circuit is connected in parallel between the output terminal of the operational amplifier opa and the output terminal of the switch K1.

[0013] Beneficial effects: The present invention provides an LDO circuit for solving the LDO power-on transition problem. Firstly, it ensures that the output voltage of the LDO will not rise along with the rise of the VDD voltage during the VDD power-on phase, so as to prevent it from exceeding a predetermined output voltage standard. Secondly, by adjusting the voltage limit of D1, the output potential can reach the set output voltage more quickly. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 FIG. 4 is a schematic structural diagram of a first embodiment of an LDO circuit of the present invention.

[0015] Figure 2 FIG. 4 is a schematic structural diagram of a second embodiment of an LDO circuit of the present invention.

[0016] Figure 3 FIG. 4 is a schematic structural diagram of a third embodiment of an LDO circuit of the present invention.

[0017] Figure 4 FIG. 4 is a schematic structural diagram of a fourth embodiment of an LDO circuit of the present invention.

[0018] Figure 5 FIG. 4 is a schematic structural diagram of a fifth embodiment of an LDO circuit of the present invention.

[0019] Figure 6 FIG. 4 is a schematic structural diagram of a sixth embodiment of an LDO circuit of the present invention.

[0020] Figure 7 FIG. 4 is a schematic diagram of the structure of an existing LDO circuit.

[0021] Figure 8 It is a simulation schematic diagram comparing the third embodiment with the existing LDO circuit.

[0022] Fig. 9 It is a structural schematic diagram of a specific implementation of the third embodiment. DETAILED DESCRIPTION

[0023] The present invention will be further described below in conjunction with specific embodiments.

[0024] like Figure 1 As shown, a first embodiment of the present invention is an LDO circuit for solving the LDO power-on transition, including: an operational amplifier opa and current control switches K1, R2, and R3 form an operational amplifier structure, capacitors C1 and R1 are compensations for the operational amplifier, respectively compensated at the first-stage output V1 and vout ends of the operational amplifier, and C2 is a load capacitor. It also includes: a time control system T1 and a switch K2 form a time control switch system. The input end of the time control system T1 is connected to the power supply VDD end, the output end of the time control system T1 is grounded, the input end of the switch K2 is connected to the power supply VDD end, the control end of the switch K2 is connected to the common end of the time control system T1, and the output end of the switch K2 is connected to the common end of the capacitor C1 and the resistor R1.

[0025] like Figure 2As shown, a second embodiment of the present invention is an LDO circuit for solving LDO power-on transition, wherein the input end of the timing control system T1 is connected to the power supply VDD end, the output end of the timing control system T1 is grounded, the input end of the switch K2 is connected to the power supply VDD end, the control end of the switch K2 is connected to the common end of the timing control system T1, and the output end of the switch K2 is connected to the output end of the operational amplifier opa.

[0026] In the first embodiment and the second embodiment, when the output end of the switch K2 is not connected to the output end V1 of the operational amplifier opa or the common end V2 of the capacitor C1 and the resistor R1, the circuit is an existing LDO two-stage operational amplifier with compensation. The compensation is used to compensate for the phase margin and the gain margin. As a module circuit in the system circuit, the potential of each point in the circuit rises from 0 during power-on startup, and a certain amount of time is required for places with larger capacitance. In addition, the voltage V_bias at the positive input end of the operational amplifier opa in the circuit may not be stable, or the operational amplifier opa may not be stable, or the operational amplifier opa and V_bias can work quickly and stably, but because the capacitor C1 is relatively large and the power consumption of the operational amplifier opa is relatively small, the output end V1 voltage of the operational amplifier opa takes too long to stabilize (at this time, the potential of V1 rises from 0). The current control switch K1 is usually composed of Pmos. At this time, because the potential rise speed of the output terminal V1 of the operational amplifier opa cannot keep up with the rise speed of the power supply VDD, the voltage difference between the output terminal V1 and the power supply VDD will increase, causing K1 to close and fail to control the current size. Vout will directly follow the voltage rise of the power supply VDD, which may produce a standard voltage that exceeds our required voltage. When the operational amplifier opa system is stable, the load capacitor C2 begins to accumulate too much charge, and it can only leak through the resistors R2 and R3. The size of the resistors R2 and R3 will determine the rate at which C2 releases the charge, so the load may be at a high level for too long.

[0027] The switch K2 and the time control system T1 in the first embodiment can effectively solve this problem. When the power supply VDD is powered on, the time control system T1 will turn on the switch K2. At this time, the potential of the common terminal V2 connected to the switch K2 will rise with the potential of VDD and be at a high potential. The charge required by C1 during the power-on stage is no longer provided by the operational amplifier opa, but by the switch K2, which improves the power-on rate of C1. The potential difference between the output terminal V1 of the operational amplifier opa and the power supply VDD will be greatly reduced, so that the switch K1 will not be turned on, and C2 will not obtain a large amount of charge through the switch K1 during the power-on stage, limiting the rapid increase of the voltage of C2. The switch K2 is connected to V2, and the switch K2 is used as a part of the compensation R1 and C1.

[0028] The timing control system T1 controls the opening and closing of switch K2. Because the capacitance at the output terminal V1 and the common terminal V2 in the LDO is relatively small, and the resistance and capacitance of switch K2 are very small, the charging speed at V1 and V2 will be very fast, so the duration of controlling K2 to open is very short and it can be closed before the operational amplifier opa works normally. When the operational amplifier opa starts, the excess charge concentrated on C1 at V1 is discharged through the operational amplifier opa, and switch K1 slowly opens as the potential of V1 decreases, and the potential of vout slowly increases until it reaches a stable value.

[0029] When the switch K2 of the second embodiment is connected to the output terminal V1 of the operational amplifier opa, the potential at V1 is increased faster than when it is connected to V2. Similarly, the potential difference between the output terminal V1 of the operational amplifier opa and the power supply VDD will be greatly reduced, so that the switch K1 will not be turned on, and C2 will not obtain a large amount of charge through the switch K1 during the power-on stage, limiting the rapid increase of the voltage of C2. After the circuit is stable, the switch K2 is connected to V1, making the switch K2 part of the pole (after the circuit is stable, V1 is a pole in the circuit).

[0030] like Figure 3 As shown, a third embodiment of the present invention is an LDO circuit for solving the LDO power-on transition, further comprising: a time control system T1 and a switch K2 form a time control switch system, and a voltage limiting module D1. The input end of the time control system T1 is connected to the power supply VDD end, the output end of the time control system T1 is grounded, the input end of the switch K2 is connected to the power supply VDD end, the control end of the switch K2 is connected to the common end of the time control system T1, and the output end of the switch K2 is connected to the common end of the capacitor C1 and the resistor R1 after passing through the voltage limiting module D1.

[0031] like Figure 4 As shown, a fourth embodiment of the present invention is an LDO circuit for solving LDO power-on transition, wherein the input end of the timing control system T1 is connected to the power supply VDD end, the output end of the timing control system T1 is grounded, the input end of the switch K2 is connected to the power supply VDD end, the control end of the switch K2 is connected to the common end of the timing control system T1, and the output end of the switch K2 is connected to the output end of the operational amplifier opa after passing through the voltage limiting module D1.

[0032] Compared with the working principle of the first embodiment, the third embodiment adds a voltage limiting module D1. The voltage limiting module D1 can be a diode or a MOS tube. The purpose is to make a potential difference between the output end of the switch K2 and V2 during power-on. The potential at V2 will not rise to close to the power supply VDD, but a part of the voltage will be limited by D1. In this way, after the operational amplifier opa is stable, the potential at V1 does not need to release the charge from the highest potential to the stable value through the operational amplifier opa. Instead, the switch K2 limits the voltage through D1 at the beginning to make the potential at V1 close to the stable value, reducing the time for C1 to release the charge from the high level, and the time for vout to rise from the low level to the stable value will be shortened.

[0033] The fourth embodiment directly applies the stepped-down potential to V1, which not only stabilizes the rise of the vout voltage, but also shortens the time for the vout voltage to stabilize.

[0034] like Figure 5 As shown, a fifth embodiment of the present invention is an LDO circuit for solving the LDO power-on transition, the compensation circuit has only capacitor C1, the input end of the time control system T1 is connected to the power supply VDD end, the output end of the time control system T1 is grounded, the input end of the switch K2 is connected to the power supply VDD end, the control end of the switch K2 is connected to the common end of the time control system T1, and the output end of the switch K2 is connected to the output end of the operational amplifier opa. A capacitor C1 is connected in parallel between the output end of the operational amplifier opa and the load vout.

[0035] like Figure 6 As shown, the sixth embodiment of the present invention is an LDO circuit for solving the LDO power-on transition, the compensation circuit has only capacitor C1, the input end of the time control system T1 is connected to the power supply VDD end, the output end of the time control system T1 is grounded, the input end of the switch K2 is connected to the power supply VDD end, the control end of the switch K2 is connected to the common end of the time control system T1, and the output end of the switch K2 is connected to the output end of the operational amplifier opa after the voltage limiting module D1. A capacitor C1 is connected in parallel between the output end of the operational amplifier opa and the load vout.

[0036] The working principles of the fifth and sixth embodiments are the same as those of the second and fourth embodiments, except that the compensation resistor R1 is not included, because the capacitor C1 can also perform the compensation function.

[0037] Embodiment 1:

[0038] like Figure 7 As shown in FIG. 1 , it is an existing LDO circuit, wherein the compensation circuit includes a compensation resistor R1 and a compensation capacitor C1. Now, the working conditions of the existing LDO circuit and the LDO circuit of the third embodiment after power-on are simulated and compared. Figure 8As shown, the top dotted line is the voltage transient curve of the power supply VDD, the middle dotted line is the load vout response curve of the existing LDO circuit as the power supply VDD voltage rises, and the bottom solid line is the load vout response curve of the LDO circuit of the third embodiment as the power supply VDD voltage rises. Although the final load vout output voltage of the two LDO circuits is 2V, the existing LDO circuit structure will output a voltage far exceeding the stable value as the power supply voltage rises, and the time required for the third embodiment to output to stability is shorter. The output voltage of the LDO circuit structure of the present invention can stably rise from a low level to a stable value.

[0039] Embodiment 2:

[0040] like Fig. 9 As shown, a specific structure of the third embodiment of the present invention, wherein the current control switch K1 adopts the pmos tube Mp1, the switch K2 adopts the pmos tube Mp2, the voltage limiting module D1 adopts the pmos tube Mp3, the time control system T1 adopts a series circuit of a resistor R4 and a capacitor C3, the resistor R4 is connected to the power supply VDD, the output end of the capacitor C3 is grounded, the common end of the resistor R4 and the capacitor C3 is connected to the G pole of the pmos tube Mp2, and the pmos tube Mp3 is connected in series with the drain of the pmos tube Mp2 and the common end between the compensation circuit resistor R1 and the capacitor C1 using a diode connection.

[0041] opa is an operational amplifier, V_bias is a reference voltage, and the voltage drop of pmos tube Mp3 is close to a Vth, which is close to the Vgs voltage on pmos tube Mp1, that is, the potential difference between V1 and the power supply VDD after stabilization. The delay system composed of resistor R4 and capacitor C3, in the power-on stage, the voltage of the upper plate of C3 is lower than the power supply VDD, so that the pmos tube Mp2 is in the open stage, and the potential at V1 and V2 will rise with the rise of the power supply voltage. When the power supply voltage is stable, the potential of C3 will gradually approach VDD, the pmos tube Mp2 will be closed, and the load vout will output a stable voltage as opa gradually stabilizes.

[0042] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. An LDO circuit for solving LDO power-on transition, comprising an LDO circuit, characterized in that: The LDO circuit includes: an operational amplifier opa, a compensation circuit, and also includes: a time control system T1 and a switch K2. The compensation circuit is connected in parallel between the output terminal V1 of the operational amplifier opa and the load terminal vout. The input terminal of the time control system T1 is connected to the power supply VDD terminal, the output terminal of the time control system T1 is grounded, the input terminal of the switch K2 is connected to the power supply VDD terminal, the control terminal of the switch K2 is connected to the common terminal of the time control system T1, and the output terminal of the switch K2 is connected to the common terminal V2. The time control system T1 is used to control the delay opening and closing of the switch K2 after power-on; The compensation circuit includes a compensation resistor R1, a compensation capacitor C1, an output terminal V1 of the operational amplifier opa is connected to the load terminal vout through a series branch of the compensation resistor R1 and the compensation capacitor C1, and a common terminal V2 is a common terminal of the compensation resistor R1 and the compensation capacitor C1; The LDO circuit also includes a switch K1, a positive input terminal of the operational amplifier opa is connected to a reference voltage V_bias, a power supply terminal of the operational amplifier opa is connected to a power supply VDD, a ground terminal of the operational amplifier opa is grounded, an output terminal V1 of the operational amplifier opa is connected to a control terminal of the switch K1, a source terminal of the switch K1 is connected to a power supply VDD, an output terminal of the switch K1 is connected in series with a resistor R2 and a resistor R3 in sequence and then grounded, a common terminal of the resistor R2 and the resistor R3 is connected to a negative input terminal of the operational amplifier opa, a capacitor C2 is provided between the output terminal of the switch K1 and the ground, and a compensation circuit is connected in parallel between the output terminal V1 of the operational amplifier opa and the output terminal of the switch K1; When the power supply VDD is powered on, the time control system T1 will turn on the switch K2. At this time, the potential of the common terminal V2 connected to the switch K2 will rise with the potential of VDD and be at a high potential. The charge required for the compensation capacitor C1 during the power-on stage is no longer provided by the operational amplifier opa, but by the switch K2, which improves the power-on rate of the compensation capacitor C1. The potential difference between the output terminal V1 of the operational amplifier opa and the power supply VDD will be greatly reduced, so that the switch K1 will not be turned on, and the capacitor C2 will not obtain a large amount of charge through the switch K1 during the power-on stage, limiting the rapid increase of the voltage of the capacitor C2. The timing control system T1 controls the switch K2 to be closed before the operational amplifier opa works normally; when the operational amplifier opa is started, the excess charge concentrated on the compensation capacitor C1 at the output terminal V1 of the operational amplifier opa is discharged through the operational amplifier opa, and the switch K1 is slowly opened as the potential of the output terminal V1 of the operational amplifier opa decreases, and the potential of the load terminal vout is slowly increased until it reaches a stable value.

2. The LDO circuit for solving the LDO power-on transition problem according to claim 1, characterized in that: The time control system T1 adopts a series circuit of a resistor R4 and a capacitor C3, the resistor R4 is connected to the power supply VDD, the output end of the capacitor C3 is grounded, the switch K2 adopts a MOS tube, the voltage limiting module D1 adopts a MOS tube, the common end of the resistor R4 and the capacitor C3 is connected to the G pole of the MOS tube of the switch K2, and the MOS tube diode connection of the voltage limiting module D1 is connected in series to the MOS tube drain of the switch K2 and the common end V2.

3. An LDO circuit for solving LDO power-on transition, comprising an LDO circuit, characterized in that: The LDO circuit includes: an operational amplifier opa, a compensation circuit, and also includes: a time control system T1 and a switch K2. A compensation circuit is connected in parallel between the output terminal V1 of the operational amplifier opa and the load terminal vout. The input terminal of the time control system T1 is connected to the power supply VDD terminal, the output terminal of the time control system T1 is grounded, the input terminal of the switch K2 is connected to the power supply VDD terminal, the control terminal of the switch K2 is connected to the common terminal of the time control system T1, and the output terminal of the switch K2 is connected to the output terminal V1 of the operational amplifier opa. The time control system T1 is used to control the delay opening and closing of the switch K2 after power-on. The compensation circuit includes a compensation capacitor C1, and the output terminal V1 of the operational amplifier opa is connected to the load terminal vout through the compensation capacitor C1; The LDO circuit also includes a switch K1, a positive input terminal of the operational amplifier opa is connected to a reference voltage V_bias, a power supply terminal of the operational amplifier opa is connected to a power supply VDD, a ground terminal of the operational amplifier opa is grounded, an output terminal V1 of the operational amplifier opa is connected to a control terminal of the switch K1, a source terminal of the switch K1 is connected to a power supply VDD, an output terminal of the switch K1 is connected in series with a resistor R2 and a resistor R3 in sequence and then grounded, a common terminal of the resistor R2 and the resistor R3 is connected to a negative input terminal of the operational amplifier opa, a capacitor C2 is provided between the output terminal of the switch K1 and the ground, and a compensation circuit is connected in parallel between the output terminal V1 of the operational amplifier opa and the output terminal of the switch K1; When the power supply VDD is powered on, the time control system T1 will turn on the switch K2. At this time, the potential of the output terminal V1 of the operational amplifier opa connected to the switch K2 will rise with the potential of VDD and be at a high potential. The charge required for the compensation capacitor C1 during the power-on stage is no longer provided by the operational amplifier opa, but by the switch K2, which improves the power-on rate of the compensation capacitor C1. The potential difference between the output terminal V1 of the operational amplifier opa and the power supply VDD will be greatly reduced, so that the switch K1 will not be turned on, and the capacitor C2 will not obtain a large amount of charge through the switch K1 during the power-on stage, which limits the rapid increase of the voltage of the capacitor C2. The timing control system T1 controls the switch K2 to be closed before the operational amplifier opa works normally; when the operational amplifier opa is started, the excess charge concentrated on the compensation capacitor C1 at the output terminal V1 of the operational amplifier opa is discharged through the operational amplifier opa, and the switch K1 is slowly opened as the potential of the output terminal V1 of the operational amplifier opa decreases, and the potential of the load terminal vout is slowly increased until it reaches a stable value.

4. The LDO circuit for solving the LDO power-on transition problem according to claim 3, characterized in that: The time control system T1 adopts a series circuit of a resistor R4 and a capacitor C3, the resistor R4 is connected to the power supply VDD, the output end of the capacitor C3 is grounded, the switch K2 adopts a MOS tube, the voltage limiting module D1 adopts a MOS tube, the common end of the resistor R4 and the capacitor C3 is connected to the G pole of the MOS tube of the switch K2, and the MOS tube diode connection of the voltage limiting module D1 is connected in series to the MOS tube drain of the switch K2 and the common end V2.

Images