Soft start circuit of synchronous boost DC-DC converter

Abstract

A soft start circuit of a synchronous boost DC-DC converter is used for restraining current overshoot and voltage overshoot of the synchronous boost DC-DC converter in the starting process and comprises a first soft start module and a second soft start module. The first soft start module belongs to system open-loop work, and suppresses a channel length modulation effect through the same drain end voltage of a clamping matching tube and a power upper tube, so as to obtain a precisely controlled charging current. A second soft start module belongs to system closed-loop work, and the method comprises the following steps: in the first stage, VOUT partial voltage is synchronized; in the second stage, constant-current charging is carried out; and in the third stage, the error amplifier vref rises gently through preset voltage RC charging. According to the invention, current overshoot and voltage overshoot are effectively suppressed through two soft start stages, and the starting circuit has a wide application prospect in the field of starting circuits.

Description

Technical Field

[0001] The present invention belongs to the technical field of starting circuits, and particularly relates to a soft-start circuit for a synchronous boost DC-DC converter. Background Art

[0002] During the startup phase of a synchronous boost DC-DC converter, there is a risk of device damage due to current overshoot and voltage overshoot. Therefore, a suitable soft-start circuit is required. The soft-start circuit configures appropriate charging current and soft-start time for the startup of the power supply chip, so that the output voltage slowly rises to the set value after startup. In the first soft-start stage, traditional soft-start circuits mostly use a current mirror method to control the power transistor to charge the output capacitor with an approximately constant current. Due to the different drain voltages of the power transistor and the matching transistor, the current matching effect of the power transistor and the matching transistor is poor affected by the channel length modulation effect. In the second stage, the reference voltage terminal of the error amplifier is usually made to rise slowly. However, since the difference between the positive and negative terminals of the error amplifier is still large, there is still a risk of output voltage overshoot. Summary of the Invention

[0003] In order to overcome the above-mentioned deficiencies of the prior art, the purpose of the present invention is to provide a soft-start circuit for a synchronous boost DC-DC converter, which realizes a smooth transition of the startup process through two processes of the first soft-start stage and the second soft-start stage, and avoids current and voltage overshoot.

[0004] In order to achieve the above purpose, the technical solution adopted by the present invention is: A soft-start circuit includes: a first soft-start module and a second soft-start module.

[0005] In one or more embodiments of the present invention, the supply voltage of the first soft-start module is provided by the supply voltage VIN of the boost converter; ib1 is provided by the bandgap reference; vrefs is provided by the low-dropout linear regulator.

[0006] In one or more embodiments of the present invention, one end of the reference resistor R1 of the first soft-start module is grounded and the other end is connected to the positive terminal of the error amplifier, and the negative terminal of the error amplifier is connected to the reference voltage vrefs. The error amplifier clamps the voltage on the reference resistor R1 to generate a determined current in the matching transistor.

[0007] In one or more embodiments of the present invention, the eighteenth transistor M18 of the first soft-start module is connected to the seventeenth transistor M17 in the form of a current mirror to clamp the currents in the branches where the eighteenth transistor M18 and the seventeenth transistor M17 are located through the size relationship between the eighteenth transistor M18 and the seventeenth transistor M17.

[0008] In one or more embodiments of the present invention, the nineteenth transistor M19 and the twentieth transistor M20 of the first soft-start module are connected in the form of a current mirror to determine the current in the branch where the eighteenth transistor M18 is located through the twentieth transistor M20 and the nineteenth transistor M19.

[0009] In one or more embodiments of the present invention, the size ratio of the seventeenth transistor M17 and the eighteenth transistor M18 of the first soft-start module is the ratio of the preset currents of two branches, forming a source comparator.

[0010] In one or more embodiments of the present invention, for the first error amplifier of the first soft-start module, its first stage consists of the sixth transistor M6 and the seventh transistor M7 as input pair transistors, and the thirteenth transistor M13 and the fourteenth transistor M14 are connected in diode form as a load. The second stage consists of the fourth transistor M4, the fifth transistor M5, the eleventh transistor M11, the fifteenth transistor M15, the twelfth transistor M12, and the sixteenth transistor M16 connected in the form of an active current mirror.

[0011] In one or more embodiments of the present invention, the output of the error amplifier of the first soft-start module is connected to the gates of the matching transistor and the power transistor to form negative feedback, so that the drain voltages of the matching transistor and the power transistor are both the output voltage of the converter, suppressing the channel length modulation effect.

[0012] In one or more embodiments of the present invention, the first soft-start module makes the source-drain-gate voltages of the matching transistor and the power transistor approximately the same. The power transistor and the matching transistor are in proportion, and the power transistor can accurately match the current in the matching transistor in proportion.

[0013] In one or more embodiments of the present invention, the positive terminal of the VIN_VOUT comparator of the first soft-start module is connected to the input voltage VIN of the synchronous boost type DCDC converter, and the negative terminal is connected to the output voltage VOUT of the synchronous boost type DCDC converter to generate the first soft-start stage completion voltage signal preok.

[0014] In one or more embodiments of the present invention, the supply voltage VDD of the second soft-start module is provided by the input voltage VIN of the VIN synchronous boost type DCDC converter. The current source ib is provided by the bandgap reference. The voltage at the FB terminal is a voltage division of the output voltage of the synchronous boost type DC-DC converter. The reference voltages vref1 and vref2 are provided by the low dropout linear regulator. The control signal preok is provided by the first soft-start module.

[0015] In one or more embodiments of the present invention, the vref signal of the second soft start module is provided for use by the error amplifier of the synchronous boost DCDC converter, and the overshoot of the output voltage VOUT is suppressed by the slowly rising vref signal. When the SSDN signal is high, it indicates that the soft start phase is completed.

[0016] In one or more embodiments of the present invention, the second soft start module consists of the twenty-first transistor M21, the twenty-second transistor M22, the twenty-third transistor M23, and the twenty-fourth transistor M24 to form a current mirror to proportionally copy the current generated by the current source for charging the first capacitor C1 and the second capacitor C2.

[0017] In one or more embodiments of the present invention, the second soft start module uses the twenty-fifth transistor M25 as a switching transistor to control the conduction and cutoff of the current in the branch where the twenty-fourth transistor M24 is located.

[0018] In one or more embodiments of the present invention, the second soft start module consists of the twenty-sixth transistor M26 and the twenty-seventh transistor M27 to form a first transmission gate; the twenty-eighth transistor M28 and the twenty-ninth transistor M29 to form a second transmission gate; the thirtieth transistor M30 and the thirty-first transistor M31 to form a third transmission gate.

[0019] In one or more embodiments of the present invention, the first transmission gate in the second soft start module controls the conduction and cutoff of the charging of the first capacitor C1 by FB, the second transmission gate controls the conduction and cutoff of the charging of the second capacitor C2 by the current mirror current, and the third transmission gate controls the conduction and cutoff of the charging of the second capacitor C2 by vref1.

[0020] In one or more embodiments of the present invention, the input signal of the second soft start module is connected to the input of the third inverter, and the output of the third inverter is connected to the input of the fourth inverter to generate two control signals fby and fbn to control the switching on and off of the twenty-fifth transistor M25 and the first transmission gate.

[0021] In one or more embodiments of the present invention, the positive terminal of the SSDN comparator of the second soft start module is connected to the first capacitor C1, the negative terminal is connected to the reference voltage vref2, and the output terminal is connected to the input terminal of the first inverter. The output terminal of the first inverter is connected to the input terminal of the second inverter to generate two control signals selvrefn and selvrefy to control the conduction and cutoff of the second transmission gate and the third transmission gate.

[0022] In one or more embodiments of the present invention, the output of the SSDN comparator of the second soft start module is connected to the delay module, and the output of the delay module is then connected to the SSDN output terminal to indicate that the soft start phase is completed.

[0023] Compared with the prior art, the soft start circuit of the present invention avoids current and voltage overshoots in the following manner. After the synchronous boost DCDC converter is powered on, the soft start circuit first operates through the first soft start module. The error amplifier clamps the voltage across the reference resistor R1, generating a determined current in the branch where the seventeenth transistor M17 is located. As the output voltage VOUT of the synchronous boost DCDC converter rises to the point where the eighteenth transistor M18 and the nineteenth transistor M19 operate in the saturation region, the current in the branch where the eighteenth transistor M18 is located is determined by the current mirror in the branch where the twentieth transistor is located. Further, the current ratio of the seventeenth transistor M17 and the eighteenth transistor M18 is the same as the size ratio, and the terminals of the matching transistors are clamped to the same as the drain terminal of the power transistor, making the source-drain-gate voltages of the matching transistors and the power transistors approximately the same, and the load capacitance can be charged with a constant current accurately. The state of the output voltage VOUT is monitored through the VIN_VOUT comparator. When VOUT rises to be lower than VIN by a threshold VTH1 (the set value in the embodiment of the present invention is 200 mV), the preok signal goes high, and the first startup stage is completed. The system loop starts to operate, and the soft start circuit generates a slowly rising vref through the second soft start module. Different from the traditional scheme, the vref rise in the present invention is divided into three stages: In the first stage, when the first soft start stage is not completed, the second soft start module pre-charges the first capacitor C1 of the second soft start module through the FB terminal with the divided voltage of the output voltage VOUT in advance, so as to avoid too large a voltage difference across the error amplifier when the system enters the loop after the pre-charging of the first soft start stage is completed. Through this stage, the overshoot of the output voltage VOUT can be suppressed; In the second stage, after the preok signal arrives, the first transmission gate of the second soft start module is closed, and the first capacitor C1 and the second capacitor are charged with a constant current by the current mirror, and the vref of the error amplifier rises at a fixed slope; In the third stage, when the first capacitor C1 and the second capacitor C2 are charged to be lower than vref1 by a threshold (set as vref2 in this embodiment), the second transmission gate is closed, and the third transmission gate is opened to charge the second charging capacitor C2 with vref1 through the current limiting resistor R2. Through this stage, the reference voltage vref of the error amplifier can rise smoothly to the set value vref1 and stabilize at vref1. The soft start circuit of the present invention realizes a smooth transition during the startup process through the two processes of the first soft start stage and the second soft start stage, avoiding current and voltage overshoots. Description of the Drawings

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments recorded in the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0025] Figure 1 This is the schematic diagram of the first soft start module of the soft start circuit in an embodiment of the present invention.

[0026] Figure 2 This is the schematic diagram of the second soft start module of the soft start circuit in an embodiment of the present invention.

[0027] Figure 3 This is the simulation schematic diagram of each signal in an embodiment of the present invention. Detailed implementation manners

[0028] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0029] "Coupled", "connected", or "linked" in the specification includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrical conduction medium, which may have parasitic inductance or parasitic capacitance; indirect connection may also include a connection through other active devices or passive devices on the basis of achieving the same or similar functional purposes, such as a connection through circuits or components such as switches and transmission gates. Additionally, in the invention, words such as "first", "second", etc. are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply that there is a certain actual relationship, quantity, or order between these technical features.

[0030] In the detailed description of the specification, reference is made to the accompanying drawings that form a part of it, in which the same reference numerals always represent the same components, and which are shown by way of exemplary embodiments that can be implemented. It should be understood that other embodiments can be utilized and structural or logical changes can be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be considered limiting.

[0031] The various operations in the specification can be described as a plurality of discrete actions or operations in the order that is most helpful for understanding the claimed subject matter. However, the described order should not be construed as implying that these operations must be order-related. Specifically, these operations may not be executed in the order presented. The described operations can be executed in an order different from that of the described embodiments. Various additional operations can be performed in additional embodiments and / or the described operations can be omitted.

[0032] For the purposes of the present disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0033] Various components and devices may be referred to or shown herein in the singular form (e.g., "MOS transistor", "transistor", "switch", etc.), but this is merely for convenience of discussion, and any element referred to in the singular form may include a plurality of such elements in accordance with the teachings herein.

[0034] The specification describes the use of the phrases "in one embodiment" or "in other embodiments" or "in some embodiments", which may each refer to one or more of the same or different embodiments. In addition, the terms "comprising", "including", "having", etc. used with respect to the embodiments of the present disclosure are synonymous.

[0035] As Figure 1 shown, in one embodiment of the present invention, a soft start circuit, the first soft start module includes a first error amplifier, a bias circuit, a matching transistor M8, a source comparator, a reference resistor, a VIN_VOUT comparator, and various interface pins.

[0036] Wherein the source terminal of the first transistor M1 is connected to the input voltage VIN of the synchronous boost DC-DC converter, and the gate terminal and the drain terminal are connected together to form a diode-type connection, and then a reference current generated by a bandgap reference is connected to the drain terminal of M1. In this way, the gate voltage determined by the current reference ib can be generated at the gate of the first transistor M1.

[0037] The bias circuit implements the gate terminals of the second transistor M2, the third transistor M3, and the twenty-first transistor M21 to be connected to the gate terminal of the first transistor, and the source terminals are connected to the drain terminal of the synchronous boost DC-DC converter, so as to mirror-generate currents at the drain terminals of the second transistor M2, the third transistor M3, and the twenty-first transistor M21 in proportion to the size of the first transistor.

[0038] In Figure 1 it, the supply voltage of the first soft start module is connected to the supply voltage VIN of the boost converter; ib1 is provided by a bandgap reference; vrefs is provided by a low dropout linear regulator.

[0039] The first error amplifier of the first soft start module, the first stage of which uses the sixth transistor M6 and the seventh transistor M7 as input pair transistors, and the thirteenth transistor M13 and the fourteenth transistor M14 are connected in diode configuration as the load. The second stage is composed of the fourth transistor M4, the fifth transistor M5, the eleventh transistor M11, the fifteenth transistor M15, the twelfth transistor M12 and the sixteenth transistor M16 connected in the form of an active current mirror.

[0040] Among them, the sources of the sixth transistor M6 and the seventh transistor M7 are connected to the source terminal of the third transistor M3. The drain terminal of the sixth transistor M6 is connected to the drain terminal of the thirteenth transistor M13. At the same time, the gate terminal of the thirteenth transistor M13 is connected to the source terminal of the thirteenth transistor M13 to form a diode-connected load of the first-stage amplifier.

[0041] The drain terminal of the seventh transistor M7 is connected to the drain terminal of the fourteenth transistor M14. The gate terminal of the fourteenth transistor M14 is connected to the source terminal of the thirteenth transistor M14 to form a diode-connected load of the first-stage amplifier.

[0042] The gates of the twelfth transistor M12 and the sixteenth transistor M16 are respectively connected to the drain terminals of the thirteenth transistor M13 and the fourteenth transistor M14, serving as the input pair transistors of the second stage of the error amplifier.

[0043] The gates of the ninth transistor M9 and the tenth transistor M10 are connected together and connected to the drain terminal of the second transistor M2. At the same time, the drain terminal of the tenth transistor M10 is connected to the source terminal of the ninth transistor M9 to serve as the bias circuit of the cascode structure composed of the eleventh transistor M11, the twelfth transistor M12, the fifteenth transistor M15 and the sixteenth transistor M16, so as to ensure that the cascode structure can operate in the saturation region.

[0044] The source terminals of the eleventh transistor M11 and the fifteenth transistor M15 are respectively connected to the drain terminals of the twelfth transistor M12 and the sixteenth transistor M16 to form a cascode structure to increase the gain of the error amplifier. At the same time, the gate terminals of the eleventh transistor M11 and the fifteenth transistor M15 are connected to the drain terminal of the ninth transistor M9 to be biased.

[0045] The gates of the fourteenth transistor M14 and the fifteenth transistor M15 are connected together. And the drain terminal of the fourteenth transistor M14 is connected to the drain terminal of the eleventh transistor M11 and the gate terminal of the fourteenth transistor M14. The source terminal of the fifth transistor M5 is connected to the drain terminal of the fifteenth transistor M15 to form an active current mirror.

[0046] Further, the source terminal of the fifth transistor M5 serves as the output terminal of the error amplifier, the sixth transistor M6 serves as the negative input terminal of the error amplifier, and the gate terminal of the seventh transistor serves as the positive input terminal of the error amplifier. The positive terminal of the error amplifier is connected to the reference resistor R1, and the negative terminal is connected to the reference voltage vrefs. By clamping the voltage across the reference resistor R1, a determined current is generated in the matching transistor.

[0047] The eighth transistor M8 is a matching transistor. Its source terminal is connected to the source terminal of the power transistor on the synchronous boost DC-DC converter, its gate terminal is connected to the gate terminal of the power transistor on the synchronous boost DC-DC converter and the output terminal of the error amplifier. Its drain terminal is connected to the source terminal of the seventeenth transistor M17.

[0048] The drain terminal of the seventeenth transistor M17 is connected to the resistor R1 and the positive input terminal of the error amplifier, and its gate terminal is connected to the gate terminal of the eighteenth transistor M18.

[0049] The source terminal of the eighteenth transistor M18 is connected to the output voltage VOUT of the synchronous boost DC-DC converter, and its drain terminal is connected to its own source terminal, forming a current mirror with the seventeenth transistor M17 to clamp the current in the branches where the eighteenth transistor M18 and the seventeenth transistor M17 are located according to the size relationship between the eighteenth transistor M18 and the seventeenth transistor M17.

[0050] The size ratio of the seventeenth transistor M17 to the eighteenth transistor M18 is the ratio of the preset currents of the two branches, forming a source comparator. The output of the error amplifier is connected to the gates of the matching transistor and the power transistor to form negative feedback, so that the drain voltages of the matching transistor M8 and the power transistor are both the output voltage of the converter, suppressing the channel length modulation effect. The source-drain-gate voltages of the matching transistor and the power transistor are approximately the same, the power transistor and the matching transistor are in proportion, and the power transistor can accurately match the current in the matching transistor according to the proportion.

[0051] The gate terminals of the nineteenth transistor M19 and the twentieth transistor M20 are connected to the drain terminal of the twentieth transistor M20. At the same time, the drain terminal of the nineteenth transistor M19 is connected to the drain terminal of the eighteenth transistor M18, and the drain terminals of the twentieth transistor M20 and the twenty-first transistor M21 are connected to obtain a bias current. The nineteenth transistor M19 and the twentieth transistor M20 are connected in the form of a current mirror to determine the current in the branch where the eighteenth transistor M18 is located according to the twentieth transistor M20 and the nineteenth transistor M19.

[0052] The positive terminal of the VIN_VOUT comparator is connected to the input voltage VIN of the synchronous boost DC-DC converter, and the negative terminal is connected to the output voltage VOUT to generate the first soft start stage completion voltage signal preok.

[0053] Such as Figure 2As shown, a soft start circuit in an embodiment of the present invention, the second soft start module includes a bias circuit, a current mirror current mirroring circuit, a switch circuit, a first transmission gate, a second transmission gate, a third transmission gate, a first inverter, a second inverter, a third inverter, a fourth inverter, a first capacitor C1, a second capacitor C2, a current limiting resistor R2, an SSDN comparator, and each interface pin.

[0054] The supply voltage VDD of the second soft start module is provided by the input voltage VIN of the VIN synchronous boost DC-DC converter. The ib2 interface is connected to the bandgap reference current, the FB terminal is connected to the voltage dividing resistor of the output voltage of the synchronous boost DC-DC converter. The reference voltages vref1 and vref2 are provided by a low dropout linear regulator, and vref1 is the voltage value preset for the vref of the synchronous boost converter error amplifier. vref2 is a voltage value that is lower than vref1 by a threshold voltage (set to 200 mV in this embodiment). The control signal preok is provided by the first soft start module, and the output signal vref is the reference voltage of the synchronous boost converter error amplifier.

[0055] As Figure 2 shown, the gates of the twenty-first transistor M21 and the twenty-second transistor M22 are connected, and at the same time connected to the drain of the twenty-first transistor M21, forming a current mirror to mirror the current of the branch of the twenty-first transistor M21 to the branch of the twenty-second transistor M22 in proportion.

[0056] The drain of the twenty-second transistor M22 is connected to the drain of the twenty-third transistor M23 to control the current in the twenty-third transistor M23.

[0057] The gates of the twenty-third transistor M23 and the twenty-fourth transistor M24 are connected and connected to the drain of the twenty-third transistor M23 to form a current mirror to copy the current of the branch where the twenty-third transistor M23 is located in a proportional relationship. This current is used to charge the first capacitor C1 and the second capacitor C2.

[0058] The gate of the twenty-fifth transistor M25 is connected to the fbn signal, and the drain is connected to the drain of the twenty-fourth transistor M24. As a switch transistor, it controls the conduction and cut-off of the current in the branch where the twenty-fourth transistor M24 is located.

[0059] The twenty-sixth transistor M26 and the twenty-seventh transistor M27 form the first transmission gate; the twenty-eighth transistor M28 and the twenty-ninth transistor M29 form the second transmission gate; the thirtieth transistor M30 and the thirty-first transistor M31 form the third transmission gate.

[0060] One end of the first transmission gate is connected to the drain of the twenty-fourth transistor and to the first capacitor C1, and is also connected to the positive terminal of the SSDN comparator to detect the completion of charging on the first capacitor C1. The first transmission gate is controlled by the fbn signal and the fby signal to turn on and off the transmission gate.

[0061] One end of the second transmission gate is connected to the positive terminal of the SSDN comparator, and the other end is connected to the second capacitor C2. The signal selvrefn and the signal selvrefy control the voltage division of the output voltage VOUT of the synchronous boost converter to charge the first capacitor C1 and the second capacitor C2.

[0062] One end of the third transmission gate is connected to the current-limiting resistor R2, and the other end is connected to the second capacitor C2. The signal selvrefn and the signal selvrefy control the preset voltage vref1 to charge the second capacitor C2.

[0063] The positive terminal of the SSDN comparator is connected to the first capacitor C1, and the negative terminal is connected to the preset voltage vref2 to detect whether the voltage of the first capacitor is charged to the voltage vref2. The output terminal of the SSDN comparator is connected to the delay module delay and the input terminal of the first inverter.

[0064] The output of the first inverter is connected to the input of the second inverter to generate two opposite control signals: the signal selvrefn and the signal selvrefy, to control the on and off of the second transmission gate and the third transmission gate.

[0065] The preok signal is generated by the first soft-start module, and the preok signal indicates the completion of the first soft-start module. The preok is connected to the input terminal of the third inverter, and the output terminal of the third inverter is connected to the input terminal of the fourth inverter to generate two opposite control signals: the signal fby and the signal fbn, to control the on and off of the first transmission gate.

[0066] Figure 2 The shown vref signal is provided for the error amplifier of the synchronous boost DC-DC converter. The slow-rising vref signal is used to suppress the overshoot of the output voltage VOUT. The output of the SSDN comparator is connected to the delay module, and the output of the delay module is then connected to the SSDN output terminal to indicate the completion of the soft-start phase. After the synchronous boost DCDC converter is powered on, the soft start circuit first works through the first soft start module. The error amplifier clamps the voltage on the reference resistor R1, generating a determined current in the branch where the seventeenth transistor M17 is located. As the output voltage VOUT of the synchronous boost DCDC converter rises to the point where the eighteenth transistor M18 and the nineteenth transistor M19 operate in the saturation region, the current in the branch where the eighteenth transistor M18 is located is determined by the current mirror in the branch where the twentieth transistor is located. Further, the current ratio of the seventeenth transistor M17 and the eighteenth transistor M18 is the same as the size ratio, and the terminals of the matching transistors are clamped to the same as the drain terminal of the power transistor, making the source-drain-gate voltages of the matching transistors and the power transistors approximately the same, and the load capacitance can be accurately charged with a constant current. The state of the output voltage VOUT is monitored by the VIN_VOUT comparator. When VOUT rises to be lower than VIN by a threshold VTH1 (the set value in the embodiment of the present invention is 200 mV), the preok signal goes high, and the first startup stage is completed.

[0067] After the first soft start stage is completed, the system loop starts to work, and the soft start circuit generates a slowly rising vref through the second soft start module. The rise of vref in the present invention is divided into three stages: In the first stage, when the first soft start stage is not completed, the second soft start module pre-charges the first capacitor C1 of the second soft start module through the FB terminal with the divided voltage of the output voltage VOUT in advance, so as to avoid too large a voltage difference between the two ends of the error amplifier when the system enters the loop after the pre-charging of the first soft start stage is completed. Through this stage, the overshoot of the output voltage VOUT can be suppressed; In the second stage, after the preok signal arrives, the first transmission gate of the second soft start module is closed, and the first capacitor C1 and the second capacitor are charged with a constant current by the current mirror, and the vref of the error amplifier rises at a fixed slope; In the third stage, when the first capacitor C1 and the second capacitor C2 are charged to be lower than vref1 by a threshold (set to vref2 in this embodiment), the second transmission gate is closed, and the third transmission gate is opened to charge the second charging capacitor C2 through the current limiting resistor R2 by vref1. Through this stage, the reference voltage vref of the error amplifier can rise smoothly to the set value vref1 and stabilize at vref1. The soft start circuit of the present invention realizes a smooth transition during the startup process through two processes of the first soft start stage and the second soft start stage, avoiding current and voltage overshoots.

Claims

1. A soft start circuit of a synchronous boost DC-DC converter, comprising a first soft start module and a second soft start module, characterized in that: The first soft start module includes a first error amplifier, a bias circuit, a matching tube, a source comparator, a reference resistor, and a VIN_VOUT comparator; The second soft start module includes a current mirror, a first transmission gate, a second transmission gate, a third transmission gate, an SSDN comparator, a first capacitor, a second capacitor, a first inverter, a second inverter, a third inverter, a fourth inverter, and a delay circuit; The first error amplifier of the first soft-start module, wherein the first stage is composed of the sixth transistor M6 and the seventh transistor M7 as an input pair, the thirteenth transistor M13 and the fourteenth transistor M14 are connected in a diode type as a load, and the second stage is composed of the fourth transistor M4, the fifth transistor M5, the eleventh transistor M11, the fifteenth transistor M15, the twelfth transistor M12 and the sixteenth transistor M16 connected in an active current mirror form; The positive terminal of the VIN_VOUT comparator of the first soft-start module is connected to the synchronous boost type DCDC converter input voltage VIN, and the negative terminal is connected to the synchronous boost type DCDC converter output voltage VOUT to generate a first soft-start stage completion voltage signal preok; The first soft start module, the matching tube gate is connected to the gate of the boost converter P power tube and is also connected to the output of the error amplifier, and the source end is connected to PVIN to make the matching tube and the power tube source, drain, and gate voltages equal; The first soft-start module, one end of the reference resistor R1 is grounded and the other end is connected to the positive end of the error amplifier, and the negative end of the error amplifier is connected to the reference voltage vrefs to generate a constant current vrefs / R1 on the reference resistor R1; The source comparator of the first soft-start module is connected to VOUT at one end and connected to the drain end of the matching tube at another end to clamp the power and the drain end voltage of the matching tube; The second soft-start module is composed of a twenty-first transistor M21, a twenty-second transistor M22, a twenty-third transistor M23 and a twenty-fourth transistor M24 to form a current mirror to proportionally copy the current generated by the current source to charge the first capacitor C1 and the second capacitor C2; The second soft-start module comprises a 26th transistor M26 and a 27th transistor M27 forming a first transmission gate; a 28th transistor M28 and a 29th transistor M29 forming a second transmission gate; and a 30th transistor M30 and a 31st transistor M31 forming a third transmission gate; The input signal of the second soft-start module is connected to the input of the third inverter, and the output of the third inverter is connected to the input of the fourth inverter to generate two control signals fby and fbn to control the switching of the twenty-fifth transistor M25 and the first transmission gate; The positive terminal of the SSDN comparator of the second soft start module is connected to the first capacitor C1, the negative terminal is connected to the reference voltage vref2, the output terminal is connected to the first inverter input terminal, and the first inverter output terminal is connected to the second inverter input terminal to generate two control signals selvrefn and selvrefy to control the conduction and shutdown of the second transmission gate and the third transmission gate; The output signal preok of the first soft start module is connected to the preok input terminal of the second soft start module; The output of the SSDN comparator of the second soft start module is connected to the delay module, and the output of the delay module is then connected to the SSDN output terminal to indicate that the soft start phase is completed.

2. The soft start circuit of a synchronous boost DC-DC converter according to claim 1, characterized in that: The power supply voltage of the first soft-start module is provided by the power supply voltage VIN of the boost converter; ib is provided by a bandgap reference; VREFs is provided by a low voltage drop linear regulator.

3. The soft start circuit of a synchronous boost DC-DC converter according to claim 1, characterized in that: The second soft-start module uses the twenty-fifth transistor M25 as a switch tube to control the on and off of the current in the branch where the twenty-fourth transistor M24 is located.

4. The soft start circuit of a synchronous boost DC-DC converter according to claim 1, characterized in that: The first transmission gate in the second soft-start module controls the on and off of FB charging the first capacitor, the second transmission gate controls the on and off of the current mirror current charging the second capacitor, and the third transmission gate controls the on and off of vref1 charging the second capacitor.

5. The soft start circuit of a synchronous boost DC-DC converter according to claim 1, characterized in that: After the synchronous boost DCDC converter is powered on, the soft start circuit first works through the first soft start module, the error amplifier clamps the voltage on the reference resistor R1, and generates a certain current in the branch where the seventeenth transistor M17 is located. As the output voltage VOUT of the synchronous boost DCDC converter rises to the eighteenth transistor M18 and the nineteenth transistor M19 work in the saturation region, the current in the branch where the eighteenth transistor M18 is located is determined by the branch where the twentieth transistor is located through the current mirror. Further, the current ratio and size ratio of the seventeenth transistor M17 and the eighteenth transistor M18 are the same, and the end of the matching tube is clamped to the same as the drain end of the power tube, so that the voltages of the source, drain and gate of the matching tube and the power tube are approximately the same, and the load capacitor can be accurately charged with a constant current. The output voltage VOUT state is monitored by the VIN_VOUT comparator. When VOUT rises to a threshold value VTH1 lower than VIN (the setting value of the implementation case of the present invention is 200mV), the preok signal turns high, and the first startup stage is completed.

6. The soft start circuit of a synchronous boost DC-DC converter according to claim 1, characterized in that: After the first soft start phase is completed, the system loop starts to work, and the soft start circuit generates a slowly rising vref through the second soft start module. The rise of vref in the present invention is divided into three stages: in the first stage, when the first soft start phase is not completed, the second soft start module charges the first capacitor C1 of the second soft start module in advance through the FB terminal with the divided voltage of the output voltage VOUT, so as to avoid the voltage difference between the two ends of the error amplifier when the system enters the loop after the pre-charging of the first soft start phase is completed. Through this stage, the overshoot of the output voltage VOUT can be suppressed; in the second stage, after the arrival of the preok signal, the first transmission gate of the second soft start module is closed, and the current mirror charges the first capacitor C1 and the second capacitor with a constant current, and the error amplifier vref rises with a fixed slope; in the third stage, when the first capacitor C1 and the second capacitor C2 are charged to a threshold value lower than vref1 (set as vref2 in this embodiment), the second transmission gate is closed, and the third transmission gate is opened to charge the second charging capacitor C2 through the current limiting resistor R2 by vref1. Through this stage, the reference voltage vref of the error amplifier can rise smoothly to the set value vref1 and stabilize at vref1. The soft start circuit of the present invention realizes a smooth transition of the start process through two processes of a first soft start stage and a second soft start stage, thereby avoiding current and voltage overshoot.

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