Current model and parameter extraction method of field effect transistor

Abstract

The invention discloses a current model and parameter extraction method of a field effect transistor. The method comprises the following steps: constructing a current model of the field effect transistor; parameters are extracted based on a current model of the field effect transistor. According to the invention, the linear or super-linear (nonlinear) behavior of the output characteristic of the transistor at a low VDS can be represented, and the channel length modulation effect of the output characteristic of the transistor at a high VDS can also be represented; and different grid-source voltage power law parameter characteristic behaviors possibly occurring in the two conditions of the current of the transistor can be represented.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit design, and particularly relates to a current model and parameter extraction method for a field-effect transistor. Background Art

[0002] In the process of integrated circuit design, invoking the device model of a transistor is the primary step for circuit simulation. Establishing an accurate transistor model helps to perform functional evaluation and optimization on the overall performance of the integrated circuit and its system.

[0003] A thin-film transistor is a type of field-effect transistor. At present, the current model of the thin-film transistor widely used in commercial EDA software is the RPI model [Silvaco, SPICE Models Manual; Cadence, Virtuoso Simulator Components and Device Models Reference]. The RPI model combines the current models of the linear region and the saturation region and takes into account the influence of the junction resistance. The RPI model can characterize both the channel length modulation effect that may occur when the transistor output characteristic is at high V DS and the linear behavior that may occur when the transistor output characteristic is at low V DS , but it cannot characterize the superlinear (nonlinear) behavior that may occur when at low V DS , nor can it characterize the different gate-source voltage power-law parameter characteristic behaviors that may occur when at low V DS and high V DS . In order to characterize the superlinear (nonlinear) behavior that may occur when the transistor output characteristic is at low V DS , the successor B. research group of the RPI model introduced the junction resistance R DS related to V C0 exp(-ηV DS ), and proposed an improved RPI model [H. Cortes-Ordonez, et al. IEEE TED2020, 67(12):5685-5692, DOI:10.1109 / TED.2020.3032082]. To a certain extent, this improved RPI model can characterize both the channel length modulation effect that may occur when the transistor output characteristic is at high V DS and the linear or superlinear (nonlinear) behavior that may occur when the transistor output characteristic is at low V DS . However, there are still three limitations: (1) In order to characterize the linear or superlinear (nonlinear) behavior that may occur when the transistor output characteristic is at low V DS , the junction resistance R DS related to VC0 exp(-ηV DS ) is reasonable. However, as is well known, at high V DS , if the channel length modulation effect is ignored (i.e., λ = 0), the current of the transistor has reached the saturation state at this time, and the current of the transistor should be independent of V DS . Therefore, at high V DS , it is unreasonable to introduce the junction resistance R DS related to V C0 exp(-ηV DS ). (2) In order to characterize the channel length modulation effect that may occur in the output characteristics of the transistor at high V DS , it is reasonable to introduce the channel length modulation term 1 + λV DS . However, as is well known, at low V DS , there is no channel length modulation effect in the transistor. Therefore, at low V DS , it is unreasonable to introduce the channel length modulation effect term 1 + λV DS . (3) Corresponding to the two cases of low V DS and high V DS , the same gate-source voltage power-law parameter γ is used in this model. However, the current of the transistor may also exhibit different gate-source voltage power-law parameter behaviors in the above two cases, and this model cannot characterize this behavior of the transistor current. SUMMARY OF THE INVENTION

[0004] To solve the above technical problems, the present invention proposes a current model and parameter extraction method for a field-effect transistor. The proposed model can not only characterize the linear or superlinear (nonlinear) behavior that may occur in the output characteristics of the transistor at low V DS , but also characterize the channel length modulation effect that may occur in the output characteristics of the transistor at high V DS , and can also characterize the different gate-source voltage power-law parameter characteristic behaviors that the current of the transistor may exhibit in the above two cases.

[0005] To achieve the above object, the present invention provides a current model and parameter extraction method for a field-effect transistor, including:

[0006] Construct a current model of the field-effect transistor;

[0007] Extract parameters based on the current model of the field-effect transistor.

[0008] Optionally, constructing a current model of the field-effect transistor includes:

[0009] First, for the transistor at low V DS and high V DSIn these two cases, current models are established separately and then combined to form a unified current model.

[0010] At low V DS , the power-law parameters γ L and β are introduced, and the current model is

[0011]

[0012] and

[0013]

[0014] where μ 0L is the carrier mobility prefactor at low V DS , and γ L is the gate-source voltage power-law parameter at low V DS .

[0015] Substituting Equation (2) into Equation (1), we get

[0016]

[0017] At high V DS , the power-law parameters γ S and the channel length modulation parameter λ are introduced, and the current model is

[0018] I DS-S = f S ×(1 + λV DS ) (4)

[0019] and

[0020]

[0021] where μ 0S is the carrier mobility prefactor at high V DS , and γ S is the gate-source voltage power-law parameter at high V DS .

[0022] Substituting Equation (5) into Equation (4), we get

[0023]

[0024] Applying the minimum function to Equation (3) and Equation (6), we obtain a current model that is valid for both high V DS and low V DS ,

[0025]

[0026] where m is the connection between I DS-L and I DS-Sparameters;

[0027] Substituting Eqs. (3) and (6) into Eq. (7), Eq. (7) is rearranged as

[0028]

[0029] or

[0030]

[0031] Technical effects of the present invention: The present invention discloses a current model and parameter extraction method for a field-effect transistor, which can characterize both the linear or superlinear (nonlinear) behavior that may occur in the transistor output characteristics at low V DS and the channel length modulation effect that may occur in the transistor output characteristics at high V DS , and can also characterize the different gate-source voltage power-law parameter characteristic behaviors that may occur in the transistor current in the above two cases. Description of the Drawings

[0032] The drawings constituting a part of this application are used to provide a further understanding of this application. The schematic embodiments of this application and their descriptions are used to explain this application and do not constitute an improper limitation of this application. In the drawings:

[0033] Figure 1 are the output characteristics of the amorphous InGaZnO thin-film transistor with the channel length L of 50 μm and the offset lengths L offset of the drain end and the source end being 10 μm and 2 μm respectively in the embodiment of the present invention. The experimental data is compared with the calculation results of Eq. (17), where (a) the offset length L offset is 10 μm and (b) the offset length L offset is 2 μm;

[0034] Figure 2 are the output characteristics of the amorphous InGaZnO thin-film transistor with the channel length L of 5 μm and the offset lengths L offset of the drain end and the source end being 10 μm and 2 μm respectively in the embodiment of the present invention. The experimental data is compared with the calculation results of Eq. (17), where (a) the offset length L offset is 10 μm and (b) the offset length L offset is 2 μm;

[0035] Figure 3 are the output characteristics of the amorphous InGaZnO thin-film transistor with the channel length L of 200 μm and the drain end offset length L offset of 100 μm in the embodiment of the present invention. The experimental data is compared with the calculation results of Eq. (17);

[0036] Figure 4 For the embodiment of the present invention f S and f L along with V GS variation, where (a) is f S , (b) is f L ;

[0037] Figure 5 This is the output characteristic of an amorphous InGaZnO thin-film transistor with a channel length L of 200 μm and a drain-end offset length L offset of 100 μm in the embodiment of the present invention. The experimental data is compared with the calculation result of Equation (8);

[0038] Figure 6 This is a schematic flow chart of a current model and parameter extraction method for a field-effect transistor in the embodiment of the present invention. Detailed implementation manners

[0039] It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The present application will be described in detail below with reference to the drawings and in combination with the embodiments.

[0040] It should be noted that the steps shown in the flowchart of the drawings can be executed in a computer system such as a set of computer-executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than here.

[0041] In the process of integrated circuit design, calling the device model of a transistor is the first step in circuit simulation. Establishing an accurate transistor model helps to perform functional evaluation and optimization on the overall performance of the integrated circuit and its system.

[0042] A typical current model applicable to a general field-effect transistor (taking an N-channel field-effect transistor as an example) is as follows:

[0043] When V DS < V GS - V TH ), the transistor operates in the linear region, and the current model of the transistor (the current flowing from the drain end to the source end) is

[0044]

[0045] When V DS << V GS - V TH ), the transistor operates in the deep linear region. From Equation (1), we get

[0046]

[0047] When VDS ≥V GS -V TH When, the transistor operates in the saturation region, and the current model of the transistor is

[0048]

[0049] where μ is the carrier mobility, which is a constant; C i is the gate insulation layer capacitance per unit area; W and L are the channel width and channel length of the transistor respectively; V TH is the threshold voltage of the transistor; V GS is the voltage applied between the gate terminal and the source terminal of the transistor, i.e., the gate-source voltage; V DS is the voltage applied between the drain terminal and the source terminal of the transistor, i.e., the drain-source voltage.

[0050] A thin film transistor is a type of field effect transistor. In terms of the device model, the difference between a thin film transistor and a general field effect transistor is that the carrier mobility of a thin film transistor is usually not a constant.

[0051] The typical current model of a thin film transistor (taking an N-channel thin film transistor as an example) is as follows:

[0052] When V DS <V GS -V TH When, the transistor operates in the linear region, and the current model of the transistor is

[0053]

[0054] When V DS <<V GS -V TH When, the transistor operates in the deep linear region. From Equation (4), we get

[0055]

[0056] When V DS ≥V GS -V TH When, the transistor operates in the saturation region, and the current model of the transistor is

[0057]

[0058] where μ0 is the pre-factor of the carrier mobility; γ is the gate-source voltage power law parameter.

[0059] If μ0 = μ and γ = 0, Equations (4), (5), and (6) will be simplified to Equations (1), (2), and (3).

[0060] At present, the current model of thin-film transistors widely used in commercial EDA software is the RPI model [Silvaco, SPICE Models Manual; Cadence, Virtuoso Simulator Components and Device Models Reference]:

[0061]

[0062] where λ is the channel length modulation coefficient; R C is the junction resistance, which is a constant; α is a parameter related to the saturation drain-source voltage V DSSAT , V DSSAT = α(V GS - V TH ); m is a parameter connecting V DS and α(V GS - V TH ).

[0063] As can be seen from Equation (7), the RPI model combines the current model in the deep linear region (Equation (5)) and the current model in the saturation region (Equation (6)), and takes into account the influence of the junction resistance. Equation (7) can characterize both the channel length modulation effect that may occur in the transistor output characteristics at high V DS , and the linear behavior that may occur in the transistor output characteristics at low V DS , but it cannot characterize the superlinear (nonlinear) behavior that may occur at low V DS .

[0064] To characterize the superlinear (nonlinear) behavior that may occur in the transistor output characteristics at low V DS , as reported in the literature [H. Cortes-Ordonez, et al. IEEE TED 2020, 67(12): 5685 - 5692, DOI: 10.1109 / TED.2020.3032082], the successor of the RPI model, the B. research group introduced a junction resistance R DS related to V C0 exp(-ηV DS ), and proposed an improved RPI model.

[0065]

[0066] where R C0 and η are the pre-parameters and exponential parameters of the junction resistance related to V DS , respectively.

[0067] If R C0 = RC, η = 0, related to VDS The relevant junction resistance R C0 exp(-ηV DS ) will become a constant junction resistance R C , and Equation (8) will become Equation (7).

[0068] At low V DS , the transistor operates in the deep linear region. From Equation (8),

[0069]

[0070] At high V DS , the transistor operates in the saturation region. From Equation (8),

[0071]

[0072] If R C0 = 0, λ = 0, Equations (9) and (10) will become Equations (5) and (6).

[0073] As reported in [H.Cortes-Ordonez, et al. IEEE TED 2020, 67(12):5685-5692, DOI:10.1109 / TED.2020.3032082], to a certain extent, Equation (8) can characterize both the channel length modulation effect that may occur in the transistor output characteristics at high V DS , and the linear or superlinear (nonlinear) behavior that may occur in the transistor output characteristics at low V DS .

[0074] However, by analyzing Equations (9) and (10), it will be found that Equation (8) still has three limitations:

[0075] 1. In Equation (9), in order to characterize the linear or superlinear (nonlinear) behavior that may occur in the transistor output characteristics at low V DS , it is reasonable to introduce the junction resistance R DS related to V C0 exp(-ηV DS ). However, as is well known, at high V DS , if the channel length modulation effect is ignored (i.e., λ = 0), the current of the transistor has reached the saturation state at this time, and the transistor current should be independent of V DS . Therefore, in Equation (10), it is unreasonable to introduce the junction resistance R DS related to V C0 exp(-ηV DS ).

[0076] 2. In Equation (10), in order to characterize the channel length modulation effect that may occur in the transistor output characteristics at high V DS it is reasonable to introduce the channel length modulation term 1 + λV DS . However, as is well known, at low V DS there is no channel length modulation effect in the transistor. Therefore, in Equation (9), it is unreasonable to introduce the channel length modulation effect term 1 + λV DS .

[0077] 3. Corresponding to the two cases of low V DS and high V DS , the same gate-source voltage power-law parameter γ is used in Equation (9) and Equation (10). However, the transistor current may also exhibit different gate-source voltage power-law parameter behaviors in the above two cases, and Equation (8) cannot characterize this behavior of the transistor current.

[0078] As Figure 6 shown, this embodiment provides a current model and parameter extraction method for a field-effect transistor, including:

[0079] First, establish current models for the transistor in the two cases of low V DS and high V DS respectively, and then merge them to form a unified current model.

[0080] At low V DS , introduce the power-law parameters γ L and β, and the current model is

[0081]

[0082] and

[0083]

[0084] where μ 0L is the carrier mobility pre-factor at low V DS , and γ L is the gate-source voltage power-law parameter at low V DS .

[0085] Substitute Equation (12) into Equation (11) to get

[0086]

[0087] 2. At high V DS , introduce the power-law parameter γ S and the channel length modulation parameter λ, and the current model is

[0088] I DS-S = f S ×(1 + λVDS ) (14)

[0089] and

[0090]

[0091] where μ 0S is the carrier mobility pre-factor at high V DS , and γ S is the gate-source voltage power-law parameter at high V DS .

[0092] Substituting Equation (15) into Equation (14), we get

[0093]

[0094] Applying the minimum function to Equation (13) and Equation (16), a current model that is valid for both high V DS and low V DS is obtained,

[0095]

[0096] where m is the parameter connecting I DS-L and I DS-S .

[0097] Substituting Equation (13) and Equation (16) into Equation (17), Equation (17) is rearranged as

[0098]

[0099] or

[0100]

[0101] Comparing Equation (18) with Equation (8), it can be seen that Equation (18) is different from Equation (8).

[0102] In the current model Equation (17) proposed by the present invention, Equation (13) I DS valid for high V DS-L and Equation (16) I DS valid for low V DS-S are given separately. Equation (17) can overcome the limitations of Equation (8), and the advantages of Equation (17) are reflected in three aspects

[0103] 1. In Equation (13), in order to characterize the linear or superlinear (nonlinear) behavior that may occur in the transistor output characteristics at low V DS , it is reasonable to introduce the DS term related to V . As is well known, at high V DSWhen the channel length modulation effect is ignored (i.e., λ = 0), after the drain-source current reaches the saturation state, the transistor current should be independent of V DS . Therefore, in Equation (16), it is reasonable that no term related to V DS is introduced. .

[0104] 2. In Equation (16), in order to characterize the channel length modulation effect that may occur in the transistor output characteristics at high V DS , it is reasonable to introduce the channel length modulation term 1 + λV DS . However, as is well known, at low V DS , there is no channel length modulation effect in the transistor. Therefore, in Equation (13), it is also reasonable that no channel length modulation term 1 + λV DS is introduced.

[0105] 3. In Equation (13) and Equation (16), two gate-source voltage power-law parameters γ L and γ S are introduced respectively. The current of the transistor may exhibit different power-law parameter characteristic behaviors of the gate-source voltage in the above two cases, and Equation (17) can characterize this behavior of the transistor current.

[0106] Next, the experimental data of thin-film transistors reported in the literature [J. Jeong et al. Semicond. Sci. Technol. 2013 28(2): 025015, DOI: 10.1088 / 0268-1242 / 28 / 2 / 025015] and the literature [X. Li et al. IEEE EDL. 2020 41(3): 405 - 408, DOI: 10.1109 / LED.2020.2970434] are used to verify Equation (17). The thin-film transistors reported in these two literatures are high-voltage amorphous InGaZnO thin-film transistors, which are structures with offset drain and source ends. The output characteristics of the transistor exhibit linear or superlinear (nonlinear) behavior at low V DS , and exhibit channel length modulation effect at high V DS . As shown in Figure 1 , the output characteristics of amorphous InGaZnO thin-film transistors with channel length L of 50 μm and offset lengths L offset of the drain and source ends of 10 μm and 2 μm respectively are compared with the calculation results of Equation (17). As shown in Figure 2 , the output characteristics of amorphous InGaZnO thin-film transistors with channel length L of 5 μm and offset lengths L offset of the drain and source ends of 10 μm and 2 μm respectively are compared with the calculation results of Equation (17).Figure 1 The parameter values used for calculation are shown in Table 1, Figure 2 and the parameter values used for calculation are shown in Table 2.

[0107] Table 1

[0108]

[0109] Table 2

[0110]

[0111] As Figure 1 and Figure 2 shown, the current model formula (17) proposed by the present invention can not only characterize the linear or superlinear (nonlinear) behavior that appears in the transistor output characteristics at low V DS , but also characterize the channel length modulation effect that appears in the transistor output characteristics at high V DS . As Figure 3 shown, for the output characteristics of an amorphous InGaZnO thin-film transistor with a channel length L of 200 μm and a drain-end offset length L offset of 100 μm, the experimental data are compared with the calculation results of formula (17). Figure 3 The parameter values used for calculation are shown in Table 3. As Figure 3 shown, the current model formula (17) proposed by the present invention can not only characterize the superlinear (nonlinear) behavior that appears in the transistor output characteristics at low V DS , but also characterize the channel length modulation effect that appears in the transistor output characteristics at high V DS .

[0112] Table 3

[0113]

[0114] Taking Figure 3 as an example, in the current model formula (17) proposed by the present invention, the process for determining the parameter values is as follows,

[0115] 1. Use formula (14) to fit the experimental data at high V Figure 3 when V GS = 30 V to determine the value of λ, and at the same time extract the value of f DS at V S = 30 V. GS

[0116] 2. Use formula (14) to fit the experimental data at high V Figure 3 when V GS ranges from 26 V to 6 V to extract f DS at the above different V S values. GS ​The value at... Extract the f S The values from 30 V to 6 V are plotted in Figure 4 (a) and represented by open circle symbols. Fit the open circle symbols in Figure 4 (a) with Equation (15) to determine the values of V TH , μ S and γ S .

[0117] 3. Fit the experimental data at V Figure 3 = 30 V at low V GS with Equation (11) to determine the value of β, and at the same time extract f DS at V L = 30 V. GS

[0118] 4. Fit the experimental data at V Figure 3 from 26 V to 6 V at low V GS with Equation (11), extract f DS at the above different V L . Extract the f GS from 30 V to 6 V and plot it in L (b) and represent it with open circle symbols. Fit the open circle symbols in Figure 4 (b) with Equation (12) to determine the values of μ Figure 4 and γ L . L

[0119] 5. Fit the experimental data at V Figure 3 = 30 V at medium V GS with Equation (17) to determine the value of m. DS

[0120] As Figure 5 shown, the output characteristics of the amorphous InGaZnO thin-film transistor with a channel length L of 200 μm and a drain-end offset length L offset of 100 μm. The experimental data is compared with the calculation results of Equation (8). Figure 5 The parameter values used in the calculation are shown in Table 5.

[0121] Table 5

[0122] Parameter Value( Figure 4 ) Unit W 60 μm L 200 μm <![CDATA[C i > 10.3 <![CDATA[nF / cm 2 > <![CDATA[V TH > -0.5 V <![CDATA[μ0]]> <![CDATA[1.12×10 -1 > <![CDATA[cm 2 V -(1+γ) s -1 > α 16.5 - <![CDATA[R C0 > <![CDATA[1.5×10 9 > Ω η <![CDATA[1.3×10 -2 > <![CDATA[V -1 > γ 0.2 - λ <![CDATA[7×10 -5 > <![CDATA[V -1 > m 30 -

[0123] Comparing Figure 5 with Figure 3 , it can be seen the advantages of the model Equation (17) proposed by the present invention: As Figure 3 shown, Equation (17) can characterize the transistor at low V DS and high V DS ​​​When, at different V GS When (30V to 6V); as Figure 5 shown, Equation (8) cannot characterize the experimental data of the transistor at low V DS When, at different V GS When (26V to 6V). This is because for Figure 3 , as shown in Table 3, in Equation (17), two gate-source voltage power-law parameters γ DS and high V DS are introduced respectively for these two cases; γ L = 0.55 and γ S = 0.2; for Figure 5 , as shown in Table 5, in Equation (8), only one gate-source voltage power-law parameter γ = 0.2 is introduced for low V DS and high V DS .

[0124] The above is only a preferred specific embodiment of the present application, but the protection scope of the present application is not limited thereto. Any change or replacement that can be easily thought of by those skilled in the art within the technical scope disclosed by the present application should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A current model and parameter extraction method for a field effect transistor, characterized in that: include: Construct a current model of a field effect transistor; Parameters are extracted based on a current model of the field effect transistor.

2. The current model and parameter extraction method of the field effect transistor according to claim 1, characterized in that: Building a current model for a field effect transistor involves: First, the transistor is at low V DS and high V DS In these two cases, current models are established separately and then merged to form a unified current model. At low V DS When the power law parameter γ is introduced L and β, the current model is and where μ 0L For low V DS The carrier mobility prefactor, γ L For low V DS The gate-source voltage power law parameters when ; Substituting equation (2) into equation (1), we get At high V DS When the power law parameter γ is introduced s and channel length modulation parameter λ, the current model is I DS-S =f S ×(1+λV DS ) (4) and where μ 0S For high V DS The carrier mobility prefactor, γ s For high V DS The gate-source voltage power law parameters when ; Substituting equation (5) into equation (4), we get Apply the function of taking the smaller value to equation (3) and equation (6), and we get DS and low V DS The current model is valid at the same time. Where m is the connection I DS-L and I DS-S Parameters; Substituting equation (3) and equation (6) into equation (7), equation (7) can be rearranged as follows: or

Images