A broadband input buffer with high linearity implemented based on a bootstrap capacitor

Abstract

A broadband high-linearity input signal buffer based on a bootstrap capacitor provided by the present invention is composed of a sampling capacitor C3 technology, an input transistor M2 based on a bootstrap capacitor C1 and an AC floating resistor R technology, and a common-source common-gate structure with a low output impedance. The capacitor C3 using the sampling capacitor technology can compensate for the slew rate of the input signal buffer during high-frequency large-amplitude positive input, achieving the purpose of improving linearity; at the same time, the common-source common-gate structure with a low output impedance can reduce the output impedance of the input buffer, and the technology based on the bootstrap capacitor and the AC floating resistor ensures that the drain-source voltage of the input transistor is constant, eliminating the channel length modulation effect, thereby improving the overall performance of the analog-to-digital converter ADC.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuit design, and particularly relates to a broadband input buffer with high linearity implemented based on a bootstrap capacitor. Background Art

[0002] With the development of integrated circuits, there is an increasing market demand for high-speed and high-precision analog-to-digital converters. The front-end sample-and-hold circuit of high-speed and high-precision analog-to-digital converters requires a wider input bandwidth compared to low frequencies, which makes the challenges in circuit design continuously increase.

[0003] Traditional input buffers, such as Figure 1 shown, are implemented by source followers. These buffers have high input impedance and low output impedance. These characteristics can isolate the kickback noise caused by the sampling switch, reduce the non-linearity caused by the load, and provide a relatively large bandwidth. However, the disadvantages are that: as the input changes, the drain current also changes, resulting in changes in parameters such as Gm and Res, generating non-ideal effects, that is, non-linearity effects.

[0004] Referring to Figure 1 , there are two main reasons for the non-linearity of the switch:

[0005] First, the on-resistance Rs and capacitance of the switch are finite and change with the input, thus affecting the -3dB bandwidth of the switch. For the -3dB bandwidth of the switch, it can be expressed as follows:

[0006]

[0007] Second, during the process of the switch turning from closed to open, clock feedthrough will occur, and the parasitic capacitance charge will be redistributed. Reducing its influence is to reduce the switch size and increase the load capacitance.

[0008] Therefore, traditional input buffers have problems such as a decrease in linearity with input changes under large signals, the bandwidth of the buffer itself changing with the input, and the parasitic capacitance of the device deteriorating the linearity, etc. Summary of the Invention

[0009] In order to solve the above problems existing in the prior art, the present invention provides a broadband input buffer with high linearity implemented based on a bootstrap capacitor. The technical problems to be solved by the present invention are realized through the following technical solutions:

[0010] A broadband input buffer with high linearity implemented based on a bootstrap capacitor provided by the present invention includes:

[0011] Switch Φ_s, first capacitor C1, second capacitor C2, third capacitor C3, fourth capacitor CL, resistor R1, first MOS transistor M1, second MOS transistor M2, third MOS transistor M3, fourth MOS transistor M4, fifth MOS transistor M5, and sixth MOS transistor M6;

[0012] The high-power supply voltage VDDH is connected to one end of the resistor R1 and the drain of the first MOS transistor M1 respectively. The other end of the resistor R1 is connected to the negative terminal of the first capacitor C1 and the gate of the first MOS transistor M1. The positive terminal of the first capacitor C1 is connected to the positive terminals of the second capacitor C2, the third capacitor C3, and the gate of the second MOS transistor M2, and is connected to the sinusoidal input voltage VIN. The negative terminal of the second capacitor C2 is connected to the source of the first MOS transistor M1 and the drain of the second MOS transistor M2. The negative terminal of the third capacitor C3 is connected to the gate of the third MOS transistor M3, the source of the fifth MOS transistor M5, and the drain of the sixth MOS transistor M6. The drain of the fifth MOS transistor M5 is connected to the source of the second MOS transistor M2 and one end of the switch Φ_s. The other end of the switch Φ_s is connected to the positive terminal of the fourth capacitor CL. The negative terminal of the fourth capacitor CL is connected to the power ground. The gate of the fifth MOS transistor M5 is connected to the drain of the third MOS transistor M3 and the drain of the fourth MOS transistor M4. The gate of the sixth MOS transistor M6 is connected to the first input voltage VBN1. The source of the third MOS transistor M3 is connected to the low-power supply voltage VDDL. The gate of the fourth MOS transistor M4 is connected to the second input voltage VBN2. The source of the fourth MOS transistor M4 is connected to the source of the sixth MOS transistor M6 and the power ground.

[0013] Optionally, the high-power supply voltage VDDH and the low-power supply voltage VDDL are DC power supply voltages. The low-power supply voltage VDDL is 0.8V, and the high-power supply voltage VDDH is 1.8V. The sinusoidal input voltage VIN is a sinusoidal voltage signal. The first input voltage VBN1 and the second input voltage VBN2 are DC bias voltages, and the magnitudes of the first input voltage VBN1 and the second input voltage VBN2 are different.

[0014] Optionally, the first MOS transistor M1, the second MOS transistor M2, the fourth MOS transistor M4, the fifth MOS transistor M5, and the sixth MOS transistor M6 are PMOS transistors, and the third MOS transistor M3 is an NMOS transistor.

[0015] Optionally, one end of the upper plate of the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor CL is the positive terminal, and one end of the lower plate is the negative terminal.

[0016] A broadband high-linearity input signal buffer based on a bootstrap capacitor provided by the present invention is composed of a sampling capacitor C3 technology, an input transistor M2 based on a bootstrap capacitor C1 and an AC floating resistor R technology, and a low-output impedance cascode structure. The capacitor C3 using the sampling capacitor technology can compensate the slew rate of the input signal buffer when a high-frequency large-amplitude positive input occurs, achieving the purpose of improving linearity. At the same time, the low-output impedance cascode structure can reduce the output impedance of the input buffer. The technology based on the bootstrap capacitor and the AC floating resistor ensures that the drain-source voltage of the input transistor is constant, eliminating the channel-length modulation effect, thereby improving the overall performance of the analog-to-digital converter ADC.

[0017] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a schematic structural diagram of a traditional input buffer provided by an embodiment of the present invention;

[0019] Figure 2 is a schematic diagram of a high-linearity broadband input buffer implemented based on a bootstrap capacitor provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0020] The present invention will be further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0021] As Figure 2 shown, a high-linearity broadband input buffer implemented based on a bootstrap capacitor provided by the present invention includes:

[0022] Switch Φ s , a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor CL, a resistor R1, a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, and a sixth MOS transistor M6;

[0023] The high-voltage power supply VDDH is respectively connected to one end of the resistor R1 and the drain of the first MOS transistor M1. The other end of the resistor R1 is connected to the negative end of the first capacitor C1 and the gate of the first MOS transistor M1. The positive end of the first capacitor C1 is connected to the positive ends of the second capacitor C2, the third capacitor C3, and the gate of the second MOS transistor M2, and a sinusoidal input voltage VIN is connected thereto. The negative end of the second capacitor C2 is connected to the source of the first MOS transistor M1 and the drain of the second MOS transistor M2. The negative end of the third capacitor C3 is connected to the gate of the third MOS transistor M3, the source of the fifth MOS transistor M5, and the drain of the sixth MOS transistor M6. The drain of the fifth MOS transistor M5 is connected to the source of the second MOS transistor M2 and one end of the switch Φ s one end, switch Φs The other end is connected to the positive terminal of the fourth capacitor CL, and the negative terminal of the fourth capacitor CL is connected to the power ground; the gate of the fifth MOS transistor M5 is connected to the drain of the third MOS transistor M3 and the drain of the fourth MOS transistor M4; the gate of the sixth MOS transistor M6 is connected to the first input voltage VBN1; the source of the third MOS transistor M3 is connected to the low power supply voltage VDDL; the gate of the fourth MOS transistor M4 is connected to the second input voltage VBN2; the source of the fourth MOS transistor M4 is connected to the source of the sixth MOS transistor M6 and the power ground.

[0024] Among them, the first MOS transistor M1, the second MOS transistor M2, the fourth MOS transistor M4, the fifth MOS transistor M5, and the sixth MOS transistor M6 are PMOS transistors, and the third MOS transistor M3 is an NMOS transistor.

[0025] Reference Figure 2 , the broadband high-linearity input signal buffer shown in the present invention has two working states, namely the sampling state and the holding state. When the input signal buffer is in the sampling state, the switch Φ_s is closed, and the input signal is sampled to the upper plate of CL. When the input signal buffer is in the holding state, the switch Φ_s is opened, and the signal sampled by the capacitor CL is held and supplied to the subsequent ADC for quantization.

[0026] It should be noted that: the third MOS transistor M3, the fourth MOS transistor M4, the fifth MOS transistor M5, and the sixth MOS transistor M6 always operate in the saturation region. The capacitor C3 couples the input VIN to the source of the fifth MOS transistor to generate a current I2 to compensate I1, thereby improving the linearity. The capacitor C2 couples the input VIN to the source of the first MOS transistor M1. At the same time, the capacitor C1 and the resistor R1 couple the input VIN to the gate of the first MOS transistor M1. Therefore, the gate-source voltage of the first MOS transistor M1 remains almost unchanged. The capacitor C1 couples the input VIN to the drain of the second MOS transistor M2. Therefore, the drain-source voltage of the second MOS transistor M2 remains almost unchanged. At the same time, the gate of the fifth MOS transistor M5 is connected to the drains of the third MOS transistor M3 and the fourth MOS transistor M4, thereby reducing the output impedance.

[0027] A broadband high-linearity input signal buffer based on a bootstrap capacitor provided by the present invention is composed of an extraction capacitor C3 technology, an input transistor M2 based on a bootstrap capacitor C1 and an AC floating resistor R technology, and a low-output-impedance cascode structure. The capacitor C3 using the extraction capacitor technology can compensate the slew rate of the input signal buffer during high-frequency large-amplitude positive input to achieve the purpose of improving linearity; at the same time, the low-output-impedance cascode structure can reduce the output impedance of the input buffer, and the bootstrap capacitor and AC floating resistor technology ensure the constant drain-source voltage of the input transistor, eliminating the channel-length modulation effect, thereby improving the overall performance of the analog-to-digital converter ADC.

[0028] In an alternative embodiment of the present invention, the power supply high voltage VDDH and the power supply low voltage VDDL are DC power supply voltages, the power supply low voltage VDDL is 0.8V, and the power supply high voltage VDDH is 1.8V; the sine input voltage VIN is a sine voltage signal; the first input voltage VBN1 and the first input voltage VBN2 are DC bias voltages, and the magnitudes of the first input voltage VBN1 and the first input voltage VBN2 are different.

[0029] In an alternative embodiment of the present invention, one end of the upper plate of the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor CL is the positive end, and one end of the lower plate is the negative end.

[0030] It should be noted that: the present invention can adjust MOS transistors and capacitors according to different processes and different ADC performances, and the function is: to improve the linearity of the input buffer.

[0031] In the present invention, unless otherwise clearly specified and defined, terms such as "installation", "connection", "connection", "fixation" and the like should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal connection of two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0032] The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. A broadband input buffer with high linearity implemented based on a bootstrap capacitor, characterized in that Comprising: Switch (Φ s ), first capacitor (C1), second capacitor (C2), third capacitor (C3), and fourth capacitor (CL), resistor (R1), first MOS transistor (M1), second MOS transistor (M2), third MOS transistor (M3), fourth MOS transistor (M4), fifth MOS transistor (M5), and sixth MOS transistor (M6); The power supply high voltage (VDDH) is respectively connected to one end of a resistor (R1) and the drain of a first MOS transistor (M1), and the other end of the resistor (R1) is connected to the negative terminal of a first capacitor (C1) and the gate of the first MOS transistor (M1); the positive terminal of the first capacitor (C1) is connected to the positive terminals of a second capacitor (C2), a third capacitor (C3) and the gate of a second MOS transistor (M2), and a sinusoidal input voltage (VIN) is applied; the negative terminal of the second capacitor (C2) is connected to the source of the first MOS transistor (M1) and the drain of the second MOS transistor (M2); the negative terminal of the third capacitor (C3) is connected to the gate of a third MOS transistor (M3), the source of a fifth MOS transistor (M5) and the drain of a sixth MOS transistor (M6); the drain of the fifth MOS transistor (M5) is connected to the source of the second MOS transistor (M2) and one end of a switch (Φ s ), and the other end of the switch (Φ s ) is connected to the positive terminal of a fourth capacitor (CL), and the negative terminal of the fourth capacitor (CL) is connected to the power supply ground; the gate of the fifth MOS transistor (M5) is connected to the drain of the third MOS transistor (M3) and the drain of a fourth MOS transistor (M4); the gate of the sixth MOS transistor (M6) is applied with a first input voltage (VBN1); the source of the third MOS transistor (M3) is connected to the power supply low voltage (VDDL); the gate of the fourth MOS transistor (M4) is applied with a second input voltage (VBN2); the source of the fourth MOS transistor (M4) is connected to the source of the sixth MOS transistor (M6) and the power supply ground.

2. The high-linearity broadband input buffer implemented based on a bootstrap capacitor according to claim 1, wherein The power supply high voltage (VDDH) and the power supply low voltage (VDDL) are DC power supply voltages, the power supply low voltage (VDDL) is 0.8V, and the power supply high voltage (VDDH) is 1.8V; the sinusoidal input voltage (VIN) is a sinusoidal voltage signal; the first input voltage (VBN1) and the first input voltage (VBN2) are DC bias voltages, and the magnitudes of the first input voltage (VBN1) and the first input voltage (VBN2) are different.

3. The high-linearity broadband input buffer implemented based on a bootstrap capacitor according to claim 1, wherein The first MOS transistor (M1), the second MOS transistor (M2), the fourth MOS transistor (M4), the fifth MOS transistor (M5), and the sixth MOS transistor (M6) are PMOS transistors, and the third MOS transistor (M3) is an NMOS transistor.

4. The high-linearity broadband input buffer implemented based on a bootstrap capacitor according to claim 1, wherein One end of the upper plates of the first capacitor (C1), the second capacitor (C2), the third capacitor (C3), and the fourth capacitor (CL) is the positive end, and one end of the lower plates is the negative end.

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