Dynamic pole compensation LDO circuit

Abstract

The invention relates to the technical field of LDO (Low Dropout Regulator) circuits, in particular to a dynamic pole compensation LDO (Low Dropout Regulator) circuit, which is characterized in that the current of PM0 is dynamically mirrored through PM1, a channel length modulation effect is eliminated by combining a current mirror structure formed by PM2, PM3, NM0 and NM1, a super source follower formed by NM5, NM6 and NM7 is adopted, secondary poles of the LDO are pushed out of a bandwidth, the phase margin is greatly improved, and the performance of the LDO circuit is improved. Dynamic load current is mirrored to PM9 (diode connection) through NM9, a dynamic zero point is formed in combination with a capacitor C1, a secondary pole is compensated along with load change in real time, the problem that a primary pole and a secondary pole are too close in traditional Miller compensation is avoided, NM2 is introduced to break a degeneracy point of a current mirror, normal starting and stable working of a circuit are ensured, and the circuit is stable in performance. The gm value of the super source follower is adjusted through the dynamic current mirror images of PM5 and PM7, so that the secondary pole frequency is automatically adjusted along with the change of the load current, the adaptive optimization of the pole in the full-load range is realized, and the stability consistency under the light load and the heavy load is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of LDO circuits, and in particular to a dynamic pole compensation LDO circuit. Background Art

[0002] Low dropout regulators (LDOs) are primarily used to provide a stable operating voltage for internal chip circuits. Generally speaking, LDOs have two primary poles: one at the error amplifier output stage and one at the power transistor output stage. Because the pole at the power transistor output stage varies with the load resistance in the connected load circuit, when these two poles are close together, the LDO circuit can oscillate.

[0003] Traditional LDOs often suffer from slow transient output voltage response to dynamic load changes, leading to increased power supply noise and impacting system stability and performance. This problem is particularly prominent in high-precision and high-frequency applications. Furthermore, when existing LDO devices are cascaded, the mutual influence between each stage often causes stage offset, further impacting the accuracy and stability of the output voltage.

[0004] The stability of LDO under light load and heavy load is difficult to compromise, especially when the LDO has large load capacitance, such as more than uF. When the current changes greatly (0mA to 100mA), the phase margin difference between light load and heavy load is even greater, so it is necessary to find a more effective compensation method to make the LDO work stably. Figure 1 As a traditional compensation method, the traditional Maitreya zero-adjustment resistor compensation adjusts the zero point position of the system by introducing an adjustable resistor in the feedback network of the LDO, thereby compensating for the phase margin change caused by the load change to a certain extent, that is, compensation is performed by separating the main pole and the secondary pole. However, it is only applicable to the compensation when the main pole is internal. When the load capacitance is large, the main pole is usually external. At this time, if the Maitreya capacitor is used again, not only will the Maitreya capacitor be extremely large and the efficiency be low, but it is also very likely that the main and secondary poles are close, and the LDO cannot work stably. Moreover, with the changes in process and the influence of temperature, the resistance value of the zero-adjustment resistor may also change, resulting in unstable compensation effect. Summary of the Invention

[0005] In order to solve the problem that the existing Maitreya zero-adjustment resistor compensation has certain limitations in practical applications, resulting in unstable compensation effect, the present invention provides a dynamic pole compensation LDO circuit, which adopts a precise dynamic current mirror module to give a super source follower dynamic bias, so that the secondary pole of the LDO changes with the change of the load current, so that the secondary pole of the LDO always remains at a farther position, and the stability will not be reduced due to the change of the load current. No additional Maitreya zero-adjustment resistor compensation is required, avoiding the stability problems caused by excessive Maitreya capacitance, low efficiency and close primary and secondary poles, so that the LDO can work stably under various load conditions.

[0006] The present invention provides a dynamic pole compensation LDO circuit, comprising an operational amplifier module, an output drive module, a current mirror bias module, a voltage buffer module, a dynamic compensation module and a feedback control module. The operational amplifier module comprises an operational amplifier, an inverting input terminal of the operational amplifier is connected to a reference voltage Vref, and a non-inverting input terminal is connected to a feedback voltage Vfb. The operational amplifier performs differential amplification on the input reference voltage Vref and the feedback voltage Vfb, and outputs a driving signal. The output drive module comprises a PMOS tube group and an NMOS tube group. The PMOS tube group comprises PM0, PM1, PM2, PM3 and PM4. The drain of PM0 is connected to the output voltage Vout. PM1 dynamically mirrors the current of PM0. The sources of PM2 and PM3 are respectively connected to the drains of PM1 and PM0 for receiving current signals. PM4 copies the current of PM1. The NMOS tube group comprises NM0, NM1 and NM3. NM0 and NM1 are interconnected with the gates of PM2 and PM3 to form a current mirror, so that the drain-source voltage V DS is consistent and is used for current signal transmission. NM3 copies the current of NM1, and the current of PM4 is equal to the current of NM3. The current mirror bias module includes two sets of mirror units. The mirror unit dynamically mirrors the current of PM4 to adjust the transconductance gm value of the super source follower. The voltage buffer module includes NM8 and NM5, NM6, and NM7 with a common drain. NM5 mirrors the current of NM8. NM5, NM6, and NM7 form a super source follower to push the secondary pole of the LDO out of the bandwidth. The current mirror bias module is NM5, NM6, and NM7 provide appropriate gate voltages, and the source output follows the gate input signal. The dynamic compensation module includes NM9, PM9, and capacitor C1. NM9 mirrors the current from NM1 to PM9. PM9 and capacitor C1 form a zero point to compensate for the LDO's secondary pole. The feedback control module includes resistors R1 and R2, which divide the output voltage Vout to generate a feedback voltage Vfb, which is sent back to the non-inverting input of the operational amplifier, forming a negative feedback loop. The super source follower pushes the secondary pole outside the bandwidth, and the secondary point is compensated by the dynamic zero, leaving only the LDO's main pole, equivalent to a single-pole system, effectively improving the LDO's stability and transient response speed.

[0007] Furthermore, two sets of mirror units include PM5, PM6, and PM7, PM8, which mirror each other. PM5 and PM7 dynamically mirror the current of PM4. The gates of PM6 and PM8 are connected to VB1 and VB2, respectively, providing static current for PM6 and PM8. VB1 and VB2 provide a suitable static operating point for the transistor, ensuring stable operation in the amplified state.

[0008] Furthermore, the output driver module also includes NM2, whose source is grounded, drain is connected to the current mirror formed by NM0, NM1, PM2, and PM3, and gate is connected to VB3, which is used to break the degeneracy point of the current mirror and ensure normal startup of the circuit.

[0009] Furthermore, the other end of the source of NM2 is connected to a load capacitor CL, the other end of which is connected to the output voltage Vout. The load capacitor CL, resistors R1 and R2 form an RC network to filter out high-frequency noise and ripple in the output voltage and improve the power supply rejection ratio (PSR).

[0010] Furthermore, one end of capacitor C1 is connected to the gate and drain of PM9, and the other end is connected to the output of the operational amplifier, so that the power supply rejection ratio (PSR) is high.

[0011] Furthermore, one end of capacitor C1 is connected to the gate and drain of PM9, and the other end is grounded. This can keep the secondary pole away from the primary pole, simplify the circuit structure, reduce mutual interference between components, and further improve stability.

[0012] Furthermore, PM2, PM3, NM2, NM3, and PM4 are removed, and the gates of PM0, PM1 and NM0, NM1 are interconnected to form a current mirror, simplifying the circuit structure and reducing area and power consumption.

[0013] Furthermore, by removing NM8, NM5, and NM6, NM7's gate is connected to the op amp output, its source is connected to the current mirror bias module, and its drain is grounded. This makes the circuit simpler and more convenient, avoiding the high-frequency noise problem that a super source follower might cause.

[0014] Furthermore, the operational amplifier module also includes a phase compensation capacitor, which is connected between the output terminal and the inverting input terminal of the operational amplifier to improve the stability of the circuit, reduce phase delay, and avoid oscillation.

[0015] Furthermore, it also includes an overcurrent protection module, which monitors the current of the output drive module and automatically cuts off the output when the current exceeds a set threshold to protect the circuit and load from damage.

[0016] The beneficial effects of the present invention are: (1) The present invention provides a dynamic pole compensation LDO circuit. Through the current mirror composed of PM2, PM3, NM1, and NM0, the VDS of PM1 and PM0 are made consistent, which reduces the channel length modulation effect and makes the dynamic current mirror more accurate. The addition of NM2 breaks the degeneracy point and ensures the normal startup of the circuit. (2) The present invention provides a dynamic pole compensation LDO circuit. The dynamic current mirrored by NM9 flows into PM9. PM9 is a diode connection, and the equivalent resistance is 1 / gm. While gm is proportional to the current, the equivalent resistance of PM9 is connected in series with the capacitor C1 to form a dynamic zero point. Although the secondary point of the LDO does not change, the primary point changes with the current of the load, thereby indirectly compensating the secondary point of the LDO. The secondary pole frequency is far from the primary point frequency, so a large capacitor is not required to compensate the secondary point. Compared with the traditional Maitreya zeroing resistor compensation, it greatly saves area. (3) The present invention provides a dynamic pole compensation LDO circuit. By combining a dynamic super source follower with dynamic secondary point compensation, the dynamic super source follower pushes the secondary pole out of the bandwidth, and the secondary point is compensated by the dynamic zero point, leaving only the LDO main pole, which is equivalent to a single-pole system and greatly enhances stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. Those skilled in the art can also derive other drawings based on these drawings without inventive efforts. Figure 1 It is the traditional Maitreya zero-adjustment resistance compensation; Figure 2 is a circuit diagram of embodiment 1; Figure 3 is a circuit diagram of embodiment 2; Figure 4 is a circuit diagram of embodiment 3; Figure 5 is a circuit diagram of embodiment 4; Figure 6 is the phase margin at light load; Figure 7 is the phase margin at heavy load; DETAILED DESCRIPTION

[0018] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0019] Example 1, as Figure 2A dynamic pole-compensated LDO circuit is shown, comprising an operational amplifier module, an output driver module, a current mirror bias module, a voltage buffer module, a dynamic compensation module, and a feedback control module. A precise dynamic current mirror is used to dynamically bias a super source follower, causing the LDO's secondary pole to change with changes in load current. The super source follower (1 / (gmgmro)) structure pushes the secondary pole farther than the buffer of a source follower (1 / gm), resulting in higher efficiency. The current mirror bias module adjusts the super source follower's bias current in real time based on changes in load current, ensuring that the LDO's secondary pole remains at a relatively distant location, preventing stability degradation due to load current fluctuations. Furthermore, dynamic zero-follower compensation is employed, with the pole offset being a secondary pole. The secondary pole's frequency is further away from the primary pole's frequency, requiring less capacitance. Furthermore, the capacitance can be further reduced by adjusting the current to control the resistance. The dynamic super source follower pushes the secondary pole out of the bandwidth. The secondary point is compensated by the dynamic zero point, leaving only the LDO main pole, which is equivalent to a single-pole system. The stability is enhanced and it can still work stably even under large load capacitance, effectively improving the stability and transient response speed of the LDO.

[0020] Specifically, the operational amplifier module includes an operational amplifier, the inverting input terminal of the operational amplifier is connected to the reference voltage Vref, and the non-inverting input terminal is connected to the feedback voltage Vfb. The operational amplifier differentially amplifies the input reference voltage Vref and the feedback voltage Vfb and outputs a drive signal; the operational amplifier module differentially amplifies the reference voltage Vref and the feedback voltage Vfb to ensure the stability of the output voltage Vout. The design of the operational amplifier enables the circuit to respond quickly to small changes in the input voltage, thereby maintaining the output voltage at a constant level.

[0021] The output driver module includes a PMOS tube group and an NMOS tube group. The PMOS tube group includes PM0, PM1, PM2, PM3 and PM4. The drain of PM0 is connected to the output voltage Vout, PM1 dynamically mirrors the current of PM0, the sources of PM2 and PM3 are connected to the drains of PM1 and PM0 respectively, for receiving current signals, PM4 copies the current of PM1, and the NMOS tube group includes NM0, NM1 and NM3. NM0, NM1 are interconnected with the gates of PM2 and PM3 to form a current mirror, so that the drain-source voltage VDS of PM1 and PM0 is consistent for current signal transmission, and NM3 copies the current of NM1. The current in PM4 is equal to the current in NM3. PM0 is the power transistor of the LDO. When the PM0 current varies with the load, PM1 dynamically mirrors PM0's current. When the load current fluctuates, PM2 and PM3 quickly detect this change and accurately replicate and transfer the current through NM1 and NM0, effectively adjusting the LDO's pole position. PM2, PM3, NM0, and NM1 mirror each other, aligning the VDS of PM1 and PM0. This eliminates the channel length modulation effect of PM1, ensuring accurate mirroring of PM0's current and accurate transfer of PM1's mirrored current. The PMOS and NMOS transistors in the output driver module work together to achieve precise transmission and dynamic adjustment of current signals. The current mirror structure ensures accurate replication and transfer of current signals while maintaining consistency in drain-source voltage VDS, improving circuit efficiency and stability.

[0022] The current mirror bias module consists of two mirror units. These units dynamically mirror the current of PM4 to adjust the transconductance (gm) of the super source follower. The super source follower is connected to the output of the LDO. By adjusting the gm value, the LDO's output impedance can be dynamically adjusted. When the load current increases, the current of PM0 also increases. Through the dynamic mirroring of the current mirror bias module, the mirror units can quickly detect the change in PM4's current and adjust the gm value of the super source follower accordingly, thereby reducing the LDO's output impedance and improving the system's transient response. Conversely, when the load current decreases, the current of PM0 decreases. The mirror units can also dynamically adjust the gm value of the super source follower, increasing the LDO's output impedance and maintaining system stability. This dynamic adjustment mechanism ensures that the LDO circuit maintains good performance under various load conditions. By dynamically mirroring the current of PM4, the current mirror bias module adjusts the gm value of the super source follower, thereby optimizing the circuit's frequency response and stability.

[0023] The voltage buffer module includes NM8 and the common drain NM5, NM6, and NM7. NM5 mirrors NM8's current, forming a super source follower that pushes the LDO's secondary pole outside its bandwidth. The current mirror bias module provides appropriate gate voltages for NM5, NM6, and NM7, with the source output following the gate input signal. NM5 mirrors NM8's current, forming a super source follower that extends the LDO's secondary pole further. The current mirror injection of dynamic currents PM5 and PM7 varies with the load current. When the load current is high, the injected current increases, gm increases, and the LDO's secondary pole is pushed further, improving the LDO's stability. The super source follower structure in the voltage buffer module pushes the LDO's secondary pole outside its bandwidth, effectively reducing circuit noise and interference.

[0024] The dynamic compensation module consists of NM9, PM9, and capacitor C1. Capacitor C1 is connected to the gate and drain of PM9 on one end and the output of the op amp on the other. NM9 mirrors NM1's current to PM9. PM9 and capacitor C1 form a zero point to compensate the LDO's secondary pole. NM9 mirrors NM1's current, and PM9 and C1 form a zero point to compensate the LDO's secondary pole. Because NM9 mirrors the dynamic current that varies with load, the zero point also varies with load, thereby compensating the LDO's secondary pole. PM9 is a diode connection with an equivalent resistance of 1 / gm, which is proportional to current. The equivalent resistance of PM9, in series with capacitor C1, forms a dynamic zero point. Although the LDO's secondary pole remains unchanged, the primary pole changes with load current, indirectly compensating the LDO's secondary pole. Since the secondary pole frequency is farther away from the primary pole frequency, compensating the secondary pole does not require a large capacitor, significantly saving area compared to traditional Miller zeroing resistor compensation. The dynamic compensation module compensates the secondary pole of the LDO through the zero point formed by NM9, PM9 and capacitor C1, further improving the stability and transient response capability of the circuit.

[0025] The feedback control module includes resistors R1 and R2. Resistors R1 and R2 divide the output voltage Vout to generate feedback voltage Vfb, which is fed back to the non-inverting input of the operational amplifier, forming a negative feedback closed loop. R1 connects the output Vout to the load CL, while R2 connects Vfb to ground. This voltage-divider feedback network feeds a portion of the output voltage back to the negative input of the operational amplifier, achieving closed-loop control and ensuring precise control and stability of the output voltage.

[0026] The two mirror units consist of PM5, PM6, and PM7, PM8, which mirror each other. PM5 and PM7 dynamically mirror PM4's current. The gates of PM6 and PM8 are connected to VB1 and VB2, respectively, providing static current for PM6 and PM8. PM5 and PM7 mirror PM4, providing a dynamic mirrored current, while PM8 and PM6 provide a constant static current. When the load current changes, the current of PM0 also changes accordingly. Through the dynamic mirroring effect of PM1, the current of PM4 can reflect the current changes of PM0 in real time. As mirror transistors, the dynamic mirrored current provided by PM5 and PM7 maintains a certain ratio with the current of PM4, thereby achieving rapid response to load current changes. Meanwhile, the static current provided by PM8 and PM6 is used to maintain the basic current requirement of the circuit under stable operating conditions. This combination of dynamic and static currents ensures that the entire circuit maintains output voltage stability and accuracy despite load changes.

[0027] The output driver module also includes NM2, whose source is grounded and whose drain is connected to the current mirror formed by NM0, NM1, PM2, and PM3. Its gate is connected to VB3. NM2 breaks the degeneracy point, ensuring the normal operation of PM2, PM3, NM0, and NM1. VB3, as NM2's gate voltage, is properly set to maintain proper conduction within the circuit, preventing excessive conduction and increased power consumption, while also preventing insufficient conduction and affecting the normal function of the current mirror. This effectively addresses the issue of the current mirror entering an abnormal operating range due to input voltage or load fluctuations under certain extreme conditions, thereby improving circuit reliability and stability. The addition of NM2 also further optimizes the circuit's transient response, enabling faster output current adjustment and maintaining a stable output voltage in the face of sudden load changes.

[0028] The other end of NM2's source is connected to a load capacitor CL, which in turn is connected to the output voltage Vout. Load capacitor CL, along with resistors R1 and R2, forms an RC network. The RC network stabilizes the output voltage Vout and reduces fluctuations. Resistors R1 and R2 are connected in series, with one end connected to the load capacitor CL and the other end connected to ground. By adjusting the resistance values of resistors R1 and R2, the time constant of the RC network can be set, thereby controlling the response speed and stability of the output voltage Vout. In the event of a sudden load change, load capacitor CL can rapidly charge and discharge to smooth fluctuations in the output voltage Vout. The RC network further suppresses changes in the output voltage by adjusting the current, allowing the circuit to maintain a constant output voltage despite load changes, improving the performance of the LDO circuit.

[0029] To further enhance circuit stability, the operational amplifier module also includes a phase compensation capacitor, connected between the output and inverting input of the operational amplifier. This capacitor is used to enhance circuit stability, reduce phase delay, and prevent oscillation. The addition of the phase compensation capacitor effectively improves the frequency response of the operational amplifier, particularly at high frequencies. It can compensate for phase lag caused by parasitic capacitance and inductance within the operational amplifier, increasing the phase margin of the entire circuit. It can also, to a certain extent, suppress high-frequency noise interference, improving the circuit's signal-to-noise ratio and making the LDO circuit's output purer and more stable.

[0030] To protect the circuit from damage, an overcurrent protection module is also included. This module monitors the current of the output driver module and automatically cuts off the output when the current exceeds a set threshold, protecting the circuit and load from damage. It can also further include an overtemperature protection module and a short-circuit protection module to enhance the safety and reliability of the circuit. The overtemperature protection module monitors the operating temperature of the circuit in real time. Once the temperature exceeds a preset safety range, it automatically cuts off the power supply or adjusts the operating status to prevent circuit damage or fire accidents caused by overheating. The short-circuit protection module quickly responds and limits the current when a short circuit is detected at the output end, preventing damage to circuit components caused by excessive short-circuit current. Together, these protection modules ensure stable operation of the circuit under various extreme conditions.

[0031] Example 2, as Figure 3 As shown, the difference from Example 1 is that one end of capacitor C1 is connected to the gate and drain of PM9, and the other end is grounded. By grounding capacitor C1 instead of connecting it to OP, the secondary pole will be further away, and the required C1 capacitance and PM9 current will be smaller, saving area and power. By directly grounding capacitor C1 without connecting it to the operational amplifier OP, it can effectively push the secondary pole to a higher frequency range, further away from the main pole. This not only simplifies the circuit structure, but also reduces mutual interference between components, further improving the stability of the entire power management system. At the same time, since the use of operational amplifiers is reduced, the power consumption and cost of the system are also correspondingly reduced, making this solution more competitive in practical applications.

[0032] Example 3, as Figure 4As shown, the difference from Example 1 lies in removing PM2, PM3, NM2, NM3, and PM4, leaving PM0, PM1, and the gates of NM0 and NM1 interconnected to form a current mirror. Precise calculations and simulations show that removing these components not only does not affect the basic functionality of the circuit, but can actually further improve its efficiency and stability. Removing power management components like PM2 and PM3 reduces circuit complexity and potential points of failure, making the entire device more reliable. This also reduces production costs and improves the product's market competitiveness. While the current mirror is less precise, the circuit is simpler and more convenient, reducing both area and power consumption.

[0033] Example 4, as Figure 5 As shown, the difference from Example 1 is that NM8, NM5, and NM6 are removed, and the gate of NM7 is connected to the output of the operational amplifier, the source is connected to the current mirror bias module, and the drain is grounded. The dynamic super-source structure is removed, which is suitable when the power tube size is not particularly large. The circuit is simpler and more convenient, saving area and power consumption, while avoiding the high-frequency noise problem that may be caused by the dynamic super-source.

[0034] like Figure 6 and 7 As shown in the simulation results, under light load, the phase margin is 65°, which remains within the appropriate range, avoiding the slow frequency response caused by overcompensation; under heavy load, the phase margin is 81.79°, which also remains at a stable level, preventing the oscillation problem that may be caused by undercompensation.

[0035] The above description is only illustrative of the present invention and not restrictive. Those skilled in the art will understand that many modifications, changes or equivalents may be made without departing from the spirit and scope defined by the appended claims, but all of them will fall within the scope of protection of the present invention.

Claims

1. A dynamic pole compensation LDO circuit, characterized by: It includes operational amplifier module, output driver module, current mirror bias module, voltage buffer module, dynamic compensation module and feedback control module. The operational amplifier module includes an operational amplifier, an inverting input terminal of the operational amplifier is connected to a reference voltage Vref, and a non-inverting input terminal is connected to a feedback voltage Vfb. The operational amplifier differentially amplifies the input reference voltage Vref and the feedback voltage Vfb and outputs a driving signal; The output driver module includes a PMOS tube group and an NMOS tube group. The PMOS tube group includes PM0, PM1, PM2, PM3 and PM4. The drain of PM0 is connected to the output voltage Vout. PM1 dynamically mirrors the current of PM0. The sources of PM2 and PM3 are connected to the drains of PM1 and PM0 respectively to receive current signals. PM4 copies the current of PM1. The NMOS transistor group includes NM0, NM1 and NM3. The gates of NM0, NM1 and PM2, PM3 are interconnected to form a current mirror, so that the drain-source voltage VDS of PM1 and PM0 are consistent for current signal transmission. The NM3 copies the current of NM1. The PM4 current is equal to the NM3 current; The current mirror bias module includes two groups of mirror units, which dynamically mirror the current of PM4 to adjust the transconductance gm value of the super source follower; The voltage buffer module includes NM8 and NM5, NM6, and NM7 with a common drain. NM5 mirrors the current of NM8. NM5, NM6, and NM7 form a super source follower to push the secondary pole of the LDO outside the bandwidth. The current mirror bias module provides a suitable gate voltage for NM5, NM6, and NM7, and the source output is a signal that follows the gate input. The dynamic compensation module includes NM9, PM9 and capacitor C1. The NM9 mirrors the current of NM1 to PM9. The PM9 and capacitor C1 form a zero point for compensating the secondary pole of the LDO. The feedback control module includes a resistor R1 and a resistor R2. The resistors R1 and R2 divide the output voltage Vout to generate a feedback voltage Vfb and send it back to the non-inverting input terminal of the operational amplifier to form a negative feedback closed loop.

2. The dynamic pole compensation LDO circuit according to claim 1, wherein: The two groups of mirror units include PM5, PM6 and PM7, PM8 that are mirror images of each other. PM5 and PM7 dynamically mirror the current of PM4. The gates of PM6 and PM8 are connected to VB1 and VB2 respectively, which are used to provide static current for PM6 and PM8.

3. The dynamic pole compensation LDO circuit according to claim 1, wherein: The output driving module further includes NM2, a source of which is grounded, a drain of which is connected to a current mirror formed by NM0, NM1, PM2 and PM3, and a gate of which is connected to VB3, for breaking the degeneracy point of the current mirror.

4. The dynamic pole compensation LDO circuit according to claim 3, wherein: The other end of the source of NM2 is connected to a load capacitor CL, and the other end of the load capacitor CL is connected to the output voltage Vout. The load capacitor CL, the resistor R1, and the resistor R2 form an RC network for filtering high-frequency noise in the output voltage.

5. The dynamic pole compensation LDO circuit according to claim 1, wherein: One end of the capacitor C1 is connected to the gate and drain of PM9, and the other end is connected to the output of the operational amplifier.

6. The dynamic pole compensation LDO circuit according to claim 1, wherein: One end of the capacitor C1 is connected to the gate and drain of PM9, and the other end is grounded.

7. The dynamic pole compensation LDO circuit according to claim 3, wherein: Remove PM2, PM3, NM2, NM3, and PM4, and interconnect the gates of PM0, PM1 and NM0, NM1 to form a current mirror.

8. The dynamic pole compensation LDO circuit according to claim 1, wherein: Remove NM8, NM5, and NM6, so that the gate of NM7 is connected to the output of the operational amplifier, the source is connected to the current mirror bias module, and the drain is grounded.

9. The dynamic pole compensation LDO circuit according to claim 1, wherein: The operational amplifier module further includes a phase compensation capacitor connected between the output terminal and the inverting input terminal of the operational amplifier to improve the stability of the circuit.

10. The dynamic pole compensation LDO circuit according to claim 1, wherein: It also includes an overcurrent protection module, which monitors the current of the output drive module and automatically cuts off the output when the current exceeds a set threshold.

Images