A data management method and system

Abstract

The embodiment of the present application provides a data management method and system. The method comprises the following steps: receiving a first trigger signal and receiving sampling data according to a preset data input channel configuration parameter; storing the received sampling data into a first FIFO memory according to the data input channel configuration parameter, and writing the sampling data in the first FIFO memory into a DDR according to a preset rule; receiving a sampling end signal, reading the sampling data from the DDR and storing the sampling data into a second FIFO memory, and reading the sampling data from the second FIFO memory. The system is used for executing the above method. The method and system provided by the present application realize the high-speed transmission of large data volume buffering and bridging, so that the test system can be used for high-speed test of multi-channel digital IO volume.

Description

Technical Field

[0001] This invention relates to the field of data management technology, and in particular to a data management method and system. Background Technology

[0002] In the field of industrial testing, the most common interface on the object under test is the digital I / O interface. For testing this type of digital I / O interface, the traditional method is to use a multimeter or oscilloscope to acquire the input level and use a signal generator to generate the output excitation signal. This testing method requires manual wiring and related instruments and equipment. When there are many channels under test, the efficiency is low and the workload is large. There are also some automated testing equipment for specific objects under test, but these are generally difficult to be compatible with different objects under test and testing requirements.

[0003] Therefore, proposing a data management method as a bridge to achieve high-speed transmission of large data volumes through caching and bridging, and connecting the data that needs to interact with the object under test to the industrial computer after transfer, so as to realize the management of the object under test by the industrial computer, is an important issue that the industry urgently needs to solve. Summary of the Invention

[0004] To address the shortcomings of existing technologies, embodiments of the present invention provide a data management method and system.

[0005] On one hand, embodiments of the present invention provide a data management method, including:

[0006] A test radiation signal is sent to the first test device; the test radiation signal is a radiation signal with stable performance parameters.

[0007] The first radiation signal received by the first testing device is compared with the test radiation signal to obtain the first radiation signal verification value; the first radiation signal is the radiation signal obtained by the first testing device after receiving the test radiation signal.

[0008] The RE102 radiated emission test results corresponding to the first test equipment are verified based on the first radiated signal verification value.

[0009] On the other hand, embodiments of the present invention provide a data management system, including:

[0010] A data receiving device is used to receive a first trigger signal and receive sampled data according to preset data input channel configuration parameters;

[0011] A data storage device is used to cache the received sampled data into a first FIFO memory according to the data input channel configuration parameters, and write the sampled data in the first FIFO memory into DDR according to a preset rule;

[0012] A data reading device is used to receive a sampling end signal, read the sampled data from the DDR and cache it in a second FIFO memory, and read the sampled data from the second FIFO memory; the second FIFO memory is a memory that has been uploaded in advance via a LOCAL bus.

[0013] The data management method and system provided in this invention receive a first trigger signal and receive sampled data according to preset data input channel configuration parameters; according to the data input channel configuration parameters, the received sampled data is cached in a first FIFO memory, and the sampled data in the first FIFO memory is written to a DDR according to preset rules; a sampling end signal is received, the sampled data is read from the DDR and cached in a second FIFO memory, and the sampled data is read from the second FIFO memory. This achieves high-speed transmission of large data volume caching and bridging, enabling the test system to be used for high-speed testing of multi-channel digital I / O. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 A flowchart illustrating the data management method provided in an embodiment of the present invention;

[0016] Figure 2 This is a schematic diagram of the structure of a data management system provided in an embodiment of the present invention;

[0017] Figure 3 A schematic diagram of the structure of a data management system provided in another embodiment of the present invention;

[0018] Figure 4 This is a schematic diagram of the structure of a data management system provided in another embodiment of the present invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] To address the above technical issues, this invention proposes a data interface system based on the CPCI bus, the AXI bus inside the ZYNQ chip, and an optocoupler-isolated input / output interface, serving as a bridge for bidirectional data flow between an industrial computer and the object under test. A data management method is designed for this data interface, achieving high-speed transmission and bridging of large data volumes, enabling the test system to be used for high-speed testing of multi-channel digital I / O.

[0021] Specifically, an optocoupler isolation interface can be used to connect the digital I / O port of the device under test (DUT) to the I / O port of the ZYNQ chip. The output interface of the DUT is connected to the positive terminal of the LED in the optocoupler chip, and its negative terminal is grounded. This results in an isolated output at the photosensitive sensor's output terminal, which can then be directly connected to the PL pin of the ZYNQ chip. Alternatively, the PS pin of the ZYNQ chip can be connected to the input interface of the DUT after optocoupler isolation. To achieve level matching with the DUT's input, an optocoupler chip with an open-drain photosensitive sensor output is selected. Multiple level switching can be achieved through pull-up resistors and jumpers.

[0022] Furthermore, the functional modules implemented within the ZYNQ chip are divided as follows: multi-channel input data sampling and buffering module, multi-channel output data interrupt handling and timing output module, and CPCI LOCAL bus control and data upload / download module.

[0023] Furthermore, the aforementioned multi-channel input data sampling and caching module requires the use of the PL resources inside the ZYNQ chip. For the data input to the ZYNQ, timed sampling is implemented. The sampling clock is configured according to the sampling time required by the object under test. The sampled data is cached using a FIFO built with on-chip RAM resources. When the amount of data is large enough, the data of each channel is sequentially written to the corresponding partition in the DDR of the ZYNQ chip through burst transmission via the high-speed AXI interface on the ZYNQ chip for storage.

[0024] Furthermore, when the input data is partitioned into DDR, the storage area of ​​each channel should be divided into two regions of the same size for ping-pong operation, so that while the input data is being sampled, the data of the other partition can also be uploaded to the host computer.

[0025] The above-mentioned multi-channel output data interrupt handling and timing output module sampling of the PS resources in ZYNQ are implemented. The program first initializes the MIO port, interrupts and timers used, sets the MIO port to output mode, and determines the timer update interrupt time according to the time accuracy required by the tested object. The PL terminal generates an interrupt to trigger the start of MIO output, and the specific data output by each channel is written by the industrial control computer into the corresponding memory partition in DDR.

[0026] The aforementioned CPCI LOCAL bus control and data upload / download module is implemented using the PL resources in ZYNQ. Since the CPCI interface bridge chip used is PCI9054, the LOCAL interface timing required by the C mode of the PCI9054 needs to be implemented in ZYNQ. The clock frequency is 40MHz, the data bus is 32-bit, and the address bus is 8-bit. DMA mode with fixed addresses is used to transmit the upload and download data streams. Both upload and download use asynchronous FIFOs for data buffering. The clock frequency for processing in the PL is set to 200MHz. Data uploaded to the industrial control computer needs to be read from DDR via the AXI bus, buffered in the FIFO, and when the FIFO is full, the interrupt pin of the PCI9054 is pulled low to generate an interrupt, informing the industrial control computer to read the data in the FIFO. Data being downloaded is written to the FIFO by the industrial control computer via the LOCAL bus for buffering. Simultaneously, once the FIFO is not empty, the data in the FIFO is written to DDR via the AXI bus.

[0027] Furthermore, in addition to transmitting the data streams for uploading and downloading, the LOCAL bus controller also needs to configure the configuration registers in the ZYNQ program. The values ​​of these registers are set by the industrial control computer and written to ZYNQ via the LOCAL bus, after which ZYNQ starts working according to the configuration values.

[0028] In addition, the main clock of the PL section of the system is 200MHz, and the operating frequency of the ARM hard core in the PS section is 666MHz.

[0029] Specifically, Figure 1 The data management method provided in the embodiments of the present invention, such as Figure 1 As shown, this embodiment provides a data management method, including:

[0030] S1. Receive the first trigger signal and receive the sampled data according to the preset data input channel configuration parameters;

[0031] Specifically, the data receiving device receives a first trigger signal and receives sampled data according to preset data input channel configuration parameters. The first trigger signal is a data sampling trigger signal; the data input channel configuration parameters include the number of sampling points, channel enable, trigger mode, and sampling clock frequency, and may also include other performance parameters, which can be set and adjusted according to actual conditions, and are not specifically limited here.

[0032] S2. According to the data input channel configuration parameters, the received sampled data is cached in the first FIFO memory, and the sampled data in the first FIFO memory is written into DDR according to the preset rules;

[0033] Specifically, the data storage device caches the received sampled data into a first FIFO memory according to the data input channel configuration parameters, and writes the sampled data in the first FIFO memory into DDR according to a preset rule.

[0034] S3. Receive the sampling end signal, read the sampling data from the DDR and cache it in the second FIFO memory, and read the sampling data from the second FIFO memory; the second FIFO memory is a memory that has been uploaded in advance via the LOCAL bus.

[0035] Specifically, the data reading device receives a sampling end signal, reads the sampled data from the DDR and caches it in the second FIFO memory, and reads the sampled data from the second FIFO memory; the second FIFO memory is a memory that has been uploaded in advance via the LOCAL bus.

[0036] The data management method provided in this embodiment of the invention receives a first trigger signal and receives sampled data according to preset data input channel configuration parameters; according to the data input channel configuration parameters, the received sampled data is cached in a first FIFO memory, and the sampled data in the first FIFO memory is written to a DDR according to preset rules; a sampling end signal is received, the sampled data is read from the DDR and cached in a second FIFO memory, and the sampled data is read from the second FIFO memory. This achieves high-speed transmission of large data volume caching and bridging, enabling the test system to be used for high-speed testing of multi-channel digital I / O.

[0037] Based on the above embodiments, the preset data input channel configuration parameters further include a preset number of sampling points.

[0038] Based on the above embodiments, further, step S2, which involves writing the sampled data from the first FIFO memory into the DDR according to a preset rule, includes:

[0039] S201. Determine whether the current number of sampling points has reached the preset number of sampling points. If yes, proceed to step S204; otherwise, proceed to step S202.

[0040] S202. Determine whether the first FIFO memory is half full. If so, execute step S203 and return to step S201. Otherwise, continue to receive sampled data and return to step S201.

[0041] S203. Write the sampled data in the first FIFO memory into the corresponding partition of the DDR, and continue to receive sampled data;

[0042] S204. Stop receiving sampling data and output a sampling end signal, write the sampling data in the first FIFO memory to the corresponding partition of the DDR, and perform a ping-pong operation on the sampling data in the DDR.

[0043] Specifically, sampling can be performed according to the sampling clock in the preset data input channel configuration parameters. Each time a point is sampled, it is buffered in the first FIFO memory, and the sampling point counter is incremented. Simultaneously, it is determined whether the sampling point counter has reached the number of sampling points specified in the preset data input channel configuration parameters. If so, the sampling ends, the sampled data from the first FIFO memory is written to the corresponding partition in the DDR, a ping-pong operation is performed to change the storage partition, and a sampling completion signal is given. If the sampling point counter has not reached the number of sampling points specified in the preset data input channel configuration parameters, it is determined whether the first FIFO memory is half-full. If the first FIFO memory is half-full, the sampled data in the first FIFO memory is written to the corresponding partition in the DDR, and sampling data reception continues. If the first FIFO memory is not half-full, sampling data reception continues directly.

[0044] Based on the above embodiments, the step of reading the sampled data from the DDR and buffering it in the second FIFO memory, and then reading the sampled data from the second FIFO memory, further includes:

[0045] S301. The industrial control computer reads the sampled data from the second FIFO memory and determines whether all the sampled data has been read. If so, proceed to step S305; otherwise, proceed to step S302.

[0046] S302. Determine whether the second FIFO memory has cached all the sampled data. If yes, return to step S301; otherwise, proceed to step S303.

[0047] S303. Determine whether the second FIFO memory is full; if yes, proceed to step S304; otherwise, proceed to step S305.

[0048] S304. Pause reading the sampled data from the DDR and buffering it into the second FIFO memory, and return to step S301;

[0049] S305. Continue reading the sampled data from the DDR and buffering it into the second FIFO memory, then return to step S302;

[0050] S306. Output a read interrupt signal to stop reading the sampled data from the second FIFO memory.

[0051] Specifically, the industrial control computer reads the sampled data from the second FIFO memory. Specifically, it can start reading the sampled data from the DDR into the second buffer FIFO memory uploaded via the LOCAL bus, beginning with the first enabled channel. If all the sampled data is read from the second FIFO memory before it becomes full, a read interrupt signal is output directly; otherwise, the same interrupt signal is output after the second FIFO memory is full. The system waits for the industrial control computer to read the uploaded data via DMA mode. During the process of reading the sampled data from the second buffer FIFO memory, as long as the second buffer FIFO memory is not full, sampled data continues to be written into it until all the sampled data has been read by the industrial control computer.

[0052] Based on the above embodiments, the method further includes:

[0053] Receive the second trigger signal and read the data output channel configuration parameters from the DDR;

[0054] According to the data output channel configuration parameters, the sampled data read from the second FIFO memory is output.

[0055] Specifically, the data output device receives a second trigger signal, reads data output channel configuration parameters from the DDR, and outputs the sampled data read from the second FIFO memory according to the data output channel configuration parameters. The second trigger signal is a data output trigger signal, and the data output channel configuration parameters may include the number of transmission points, channel enable, trigger mode, and output time accuracy, and may also include other parameters. These can be set and adjusted according to actual conditions, and are not specifically limited here.

[0056] Based on the above embodiments, the method further includes, before receiving the configuration interrupt signal, S0, setting the configuration parameters of the data output channel.

[0057] Based on the above embodiments, further, setting the configuration parameters of the data output channel includes:

[0058] S001. Receive the data output channel configuration parameters and cache the data output channel configuration parameters in the second FIFO memory;

[0059] S002. Determine whether the data output channel configuration parameters have reached the preset number of transmission points. If yes, proceed to step S005; otherwise, proceed to step S003.

[0060] S003. Determine whether the second FIFO memory is half full. If so, execute step S004 and return to step S002; otherwise, continue to receive the data output channel configuration parameters and return to step S002.

[0061] S004. Write the data output channel configuration parameters into the DDR, and continue to receive the data output channel configuration parameters;

[0062] S005. Stop receiving data output channel configuration parameters and output a configuration completion signal. Write the data output channel configuration parameters in the second FIFO memory to the corresponding partition of the DDR, and write the value of the configuration register used to output sampled data to the corresponding address in the DDR.

[0063] Specifically, the parameter configuration device (such as an industrial control computer) first caches the data output channel configuration parameters in the second FIFO memory and increments a counter. If the second FIFO memory is half full, the data output channel configuration parameters in the second FIFO memory are written to the DDR, and the receiving of data output channel configuration parameters continues; otherwise, the receiving of data output channel configuration parameters continues directly. When the counter reaches the preset number of transmission points, the process of the industrial control computer sending data output channel configuration parameters ends, the data output channel configuration parameters cached in the second FIFO memory are written to the corresponding partition of the DDR, and the value of the configuration register used for outputting sampled data is written to the corresponding address in the DDR.

[0064] The data management method provided in this embodiment of the invention receives a first trigger signal and receives sampled data according to preset data input channel configuration parameters; according to the data input channel configuration parameters, the received sampled data is cached in a first FIFO memory, and the sampled data in the first FIFO memory is written to a DDR according to preset rules; a sampling end signal is received, the sampled data is read from the DDR and cached in a second FIFO memory, and the sampled data is read from the second FIFO memory. This achieves high-speed transmission of large data volume caching and bridging, enabling the test system to be used for high-speed testing of multi-channel digital I / O.

[0065] Figure 2 This is a schematic diagram of the structure of a data management system provided in an embodiment of the present invention, as shown below. Figure 2 As shown, an embodiment of the present invention provides a data management system, including: a data receiving device 201, a data storage device 202, and a data reading device 203, wherein:

[0066] The data receiving device 201 is used to receive the first trigger signal and receive sampled data according to the preset data input channel configuration parameters;

[0067] The data storage device 202 is used to cache the received sampled data into a first FIFO memory according to the data input channel configuration parameters, and write the sampled data in the first FIFO memory into DDR according to a preset rule;

[0068] The data reading device 203 is used to receive a sampling end signal, read the sampling data from the DDR and cache it in the second FIFO memory, and read the sampling data from the second FIFO memory; the second FIFO memory is a memory that has been uploaded in advance via the LOCAL bus.

[0069] The data management system provided in this embodiment of the invention receives a first trigger signal and receives sampled data according to preset data input channel configuration parameters; according to the data input channel configuration parameters, the received sampled data is cached in a first FIFO memory, and the sampled data in the first FIFO memory is written to a DDR according to preset rules; a sampling end signal is received, the sampled data is read from the DDR and cached in a second FIFO memory, and the sampled data is read from the second FIFO memory, thereby realizing high-speed transmission of large data volume caching and bridging, enabling the test system to be used for high-speed testing of multi-channel digital I / O.

[0070] Figure 3 A schematic diagram of the structure of a data management system provided in another embodiment of the present invention is shown below. Figure 3 As shown, the system also includes a data output device 204, used for:

[0071] Receive the second trigger signal and read the data output channel configuration parameters from the DDR;

[0072] According to the data output channel configuration parameters, the sampled data read from the second FIFO memory is output.

[0073] Figure 4 This is a schematic diagram of the structure of a data management system provided in another embodiment of the present invention, as shown below. Figure 4 As shown, the system also includes a parameter configuration device 205, used to set the configuration parameters of the data output channel.

[0074] The data management system provided in this embodiment of the invention receives a first trigger signal and receives sampled data according to preset data input channel configuration parameters; according to the data input channel configuration parameters, the received sampled data is cached in a first FIFO memory, and the sampled data in the first FIFO memory is written to a DDR according to preset rules; a sampling end signal is received, the sampled data is read from the DDR and cached in a second FIFO memory, and the sampled data is read from the second FIFO memory, thereby realizing high-speed transmission of large data volume caching and bridging, enabling the test system to be used for high-speed testing of multi-channel digital I / O.

[0075] The embodiments of the system provided by the present invention can be used to execute the processing flow of the above method embodiments. Its functions will not be repeated here, but can be referred to the detailed description of the above method embodiments.

[0076] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0077] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0078] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data management method characterized by, The method comprises the following steps: S1, receiving a first trigger signal and receiving sampling data according to preset data input channel configuration parameters; S2, storing the received sampling data into a first FIFO memory according to the data input channel configuration parameters, and writing the sampling data in the first FIFO memory into a DDR according to a preset rule; S3, receiving a sampling end signal, reading the sampling data from the DDR and storing it into a second FIFO memory, and reading the sampling data from the second FIFO memory; The second FIFO memory is a memory uploaded in advance through a LOCAL bus; S4, receiving a second trigger signal and reading data output channel configuration parameters from the DDR; S5, outputting the sampling data read from the second FIFO memory according to the data output channel configuration parameters; the data input channel configuration parameters comprise a sampling point number, a channel enablement, a trigger mode and a sampling clock frequency, and the data output channel configuration parameters comprise a transmission point number, a channel enablement, a trigger mode and an output time precision.

2. The method of claim 1, wherein, The preset data input channel configuration parameters comprise a preset sampling point number.

3. The method of claim 2, wherein, The step S2 of writing the sampling data in the first FIFO memory into the DDR according to a preset rule comprises: S201, judging whether the current sampling point number reaches the preset sampling point number, if yes, executing step S204, otherwise executing step S202; S202, judging whether the first FIFO memory is half full, if yes, executing step S203 and returning to step S201, otherwise continuing to receive sampling data and returning to step S201; S203, writing the sampling data in the first FIFO memory into a corresponding partition of the DDR, and continuing to receive sampling data; S204, stopping receiving sampling data and outputting a sampling end signal, writing the sampling data in the first FIFO memory into a corresponding partition of the DDR, and performing a ping-pong operation on the sampling data in the DDR.

4. The method of claim 1, wherein, The step of reading the sampling data from the DDR and storing it into a second FIFO memory, and reading the sampling data from the second FIFO memory comprises: S301, an industrial computer reads the sampling data from the second FIFO memory, and judges whether the sampling data is read completely, if yes, executing step S305, otherwise executing step S302; S302, judging whether the second FIFO memory stores all the sampling data, if yes, returning to step S301, otherwise executing step S303; S303, judging whether the second FIFO memory is full, if yes, executing step S304, otherwise executing step S305; S304, pausing reading the sampling data from the DDR and storing it into the second FIFO memory, and returning to step S301; S305, continuing to read the sampling data from the DDR and storing it into the second FIFO memory, and then returning to step S302; S306, outputting a reading interruption signal, and stopping reading the sample data from the second FIFO memory.

5. The method of claim 1, wherein, Before receiving the configuration interruption signal, the method further comprises: S0, setting the data output channel configuration parameter.

6. The method of claim 5, wherein, The setting of the data output channel configuration parameter comprises: S001, receiving the data output channel configuration parameter and buffering the data output channel configuration parameter to the second FIFO memory; S002, judging whether the data output channel configuration parameter reaches a preset transmission point number, if yes, executing step S005, otherwise, executing step S003, S003, judging whether the second FIFO memory is half full, if yes, executing step S004 and returning to step S002; otherwise, continuing to receive the data output channel configuration parameter and returning to step S002; S004, writing the data output channel configuration parameter to the DDR and continuing to receive the data output channel configuration parameter; S005, stopping receiving the data output channel configuration parameter and outputting a configuration completion signal, writing the data output channel configuration parameter in the second FIFO memory to a corresponding partition of the DDR, and writing a value of a configuration register for outputting the sample data to a corresponding address in the DDR.

7. A system employing the data management method as claimed in claim 1, characterized by, Comprise: data receiving device, for receiving a first trigger signal and receiving sample data according to a preset data input channel configuration parameter; data storage device, for buffering the received sample data to a first FIFO memory according to the data input channel configuration parameter, and writing the sample data in the first FIFO memory to a DDR according to a preset rule; data reading device, for receiving a sample end signal, reading the sample data from the DDR and buffering to a second FIFO memory, and reading the sample data from the second FIFO memory; the second FIFO memory is a memory uploaded in advance through a LOCAL bus.

8. The system of claim 7, wherein, The system further comprises data output device, for: receiving a second trigger signal, reading a data output channel configuration parameter from the DDR; outputting the sample data read from the second FIFO memory according to the data output channel configuration parameter.

9. The system of claim 8, wherein, The system further comprises parameter configuration device, for setting the data output channel configuration parameter.

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