A method, system, device and storage medium for debugging firmware of a PCIe board card

Abstract

The application provides a PCIe board card firmware debugging method, system, device and storage medium, the method comprises the following steps: setting a PCIe debugging service on the host side, and setting a PCIe debugging program on the PCIe board card side; based on the PCIe debugging service, a first command package is organized in a preset format, and the first command package is submitted to a host double rate synchronous dynamic random access memory; in response to an interrupt signal received by a board card double rate synchronous dynamic random access memory, a command is acquired from the host double rate synchronous dynamic random access memory and executed, a second command package is organized according to the execution result, and the second command package is returned to the host double rate synchronous dynamic random access memory; and in response to a signal that a completion interrupt is received, the second command package is read from the host double rate synchronous dynamic random access memory, and the execution result is displayed. The application can complete the debugging of the PCIe board card firmware in-band without other interfaces.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of board card debugging, more particularly, and particularly refers to a PCIe board card firmware debugging method, system, device and storage medium. BACKGROUND

[0002] With the development of various acceleration technologies, more and more complex computing tasks (such as data storage, image processing and display, etc.) are stripped from CPU and taken over by special computing acceleration cards, so that the board card firmware logic of the computing acceleration card is becoming more and more complex, and the debugging requirements for the firmware are becoming higher and higher. Most of the computing acceleration cards are connected with the host through the PCIe (Peripheral Component Interface Express, bus and interface standard) interface, and there is no ready-made firmware debugging means. The current board card firmware debugging still relies on traditional means, such as external connection of serial port, JTAG (Joint Test Action Group, Joint Test Action Group) and other interfaces for debugging. However, when the board card is formed, it is not convenient to externally connect these debugging interfaces, and it is not friendly to the secondary development of the board card firmware. In the firmware debugging, the common requirements are Shell access, log grabbing and file system access (downloading and uploading files). Therefore, a debugging method that can meet the above debugging requirements without using cables other than PCIe has become an urgent need for PCIe board card firmware debugging. SUMMARY

[0003] Therefore, the purpose of the embodiments of the present application is to provide a PCIe board card firmware debugging method, system, computer device and computer readable storage medium. The present application does not need to externally connect other interfaces, and can complete the shell access, log grabbing and file transfer requirements through the PCIe protocol in-band. The embodiments of the present application can be integrated into any qualified PCIe device, and the host software can be adapted to various operating systems, greatly reducing the large amount of additional work for firmware debugging, thereby improving the efficiency of firmware debugging.

[0004] Based on the above purpose, an aspect of an embodiment of the present application provides a PCIe board card firmware debugging method, comprising the following steps: setting a PCIe debugging service on a host side and setting a PCIe debugging program on a PCIe board card side; organizing a first command package in a preset format based on the PCIe debugging service and submitting the first command package into a host double-rate synchronous dynamic random memory; in response to an interrupt signal being received by a board card double-rate synchronous dynamic random memory, obtaining a command from the host double-rate synchronous dynamic random memory and performing the command, organizing a second command package in a command format according to an execution result, and returning the second command package to the host double-rate synchronous dynamic random memory; and in response to a signal of a completion interrupt being received, reading the second command package from the host double-rate synchronous dynamic random memory and displaying the execution result.

[0005] In some embodiments, the obtaining a command from the host double-rate synchronous dynamic random memory and performing the command comprises: in response to the command being a log grabbing, carrying a log generated by the board card firmware to a log page applied by the host.

[0006] In some embodiments, the obtaining a command from the host double-rate synchronous dynamic random memory and performing the command comprises: in response to the command being a file uploading, opening a file according to a file path in the command, reading the file into a page applied by the host, and judging whether the current reading reaches the end of the file; and in response to the current reading reaching the end of the file, closing the file.

[0007] In some embodiments, the obtaining a command from the host double-rate synchronous dynamic random memory and performing the command comprises: in response to the command being a file downloading, opening or creating a file according to a file path in the command, carrying corresponding data in the command to a memory in the board card, and writing the data into the file according to an offset bit.

[0008] Another aspect of an embodiment of the present application provides a PCIe board card firmware debugging system, comprising: a setting module configured to set a PCIe debugging service on a host side and set a PCIe debugging program on a PCIe board card side; a host module configured to organize a first command package in a preset format based on the PCIe debugging service and submit the first command package into a host double-rate synchronous dynamic random memory; a board card module configured to, in response to an interrupt signal being received by a board card double-rate synchronous dynamic random memory, obtain a command from the host double-rate synchronous dynamic random memory and perform the command, organize a second command package in a command format according to an execution result, and return the second command package to the host double-rate synchronous dynamic random memory; and a display module configured to, in response to a signal of a completion interrupt being received, read the second command package from the host double-rate synchronous dynamic random memory and display the execution result.

[0009] In some embodiments, the board card module is configured to, in response to a command for log grabbing, carry the log generated by the board card firmware to a log page applied by the host.

[0010] In some embodiments, the board card module is configured to, in response to a command for file pulling up, open a file according to a file path in the command, read the file to a page applied by the host, and determine whether the current reading reaches the end of the file; and in response to the current reading reaching the end of the file, close the file.

[0011] In some embodiments, the board card module is configured to, in response to a command for file pulling down, open or create a file according to a file path in the command, carry corresponding data in the command to the board card memory, and write to the file according to an offset bit.

[0012] In still another aspect, the present application provides a computer device, comprising: at least one processor; and a memory storing computer instructions executable on the processor, the instructions being executed by the processor to implement the steps of the above method.

[0013] In yet another aspect, the present application provides a computer readable storage medium storing a computer program executable by a processor to implement the steps of the above method.

[0014] The present application has the following beneficial technical effects: the present application does not need external interfaces, and can complete shell access, log grabbing and file transmission requirements in-band through PCIe protocol; the embodiments of the present application can be integrated into any PCIe device meeting the conditions, and the host software can also be adapted to various operating systems, greatly reducing a large amount of additional work for firmware debugging, thereby improving the efficiency of firmware debugging. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other embodiments can also be obtained from these drawings without creative labor.

[0016] Figure 1 The schematic diagram of the embodiments of the PCIe board card firmware debugging method provided by the present application;

[0017] Figure 2 The architecture diagram of the system of the PCIe board card firmware debugging provided by the present application;

[0018] Figure 3 This is an initialization flowchart of an embodiment of the present invention;

[0019] Figure 4 This is a flowchart illustrating the execution of Shell commands according to an embodiment of the present invention.

[0020] Figure 5 This is a schematic diagram of the Shell command format according to an embodiment of the present invention;

[0021] Figure 6 This is a flowchart of the Log capture process according to an embodiment of the present invention;

[0022] Figure 7 This is a schematic diagram of the Log capture command format according to an embodiment of the present invention;

[0023] Figure 8 This is a schematic diagram of the command format for obtaining file size according to an embodiment of the present invention;

[0024] Figure 9 This is a schematic diagram of the file pull-up command format according to an embodiment of the present invention;

[0025] Figure 10 This is a flowchart illustrating the file pull-up process according to an embodiment of the present invention;

[0026] Figure 11 This is a flowchart illustrating the file download process according to an embodiment of the present invention.

[0027] Figure 12 This is a schematic diagram of the file download command format according to an embodiment of the present invention;

[0028] Figure 13 A schematic diagram of an embodiment of the PCIe board firmware debugging system provided by the present invention;

[0029] Figure 14 A schematic diagram of the hardware structure of an embodiment of a computer device for PCIe board firmware debugging provided by the present invention;

[0030] Figure 15 This is a schematic diagram of an embodiment of a computer storage medium for debugging PCIe board firmware provided by the present invention. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to specific examples and the accompanying drawings.

[0032] It should be noted that all the expressions of "first" and "second" in the embodiments of the present application are used to distinguish two same name different entities or different parameters, and the "first" and "second" are only for the convenience of description, and should not be understood as the limitation of the embodiments of the present application, and the subsequent embodiments will not be described one by one.

[0033] The first aspect of the embodiments of the present application provides an embodiment of a method for debugging PCIe board card firmware. Figure 1 The embodiment of the method for debugging PCIe board card firmware provided by the present application is shown. As shown in the figure, Figure 1 The embodiment of the present application includes the following steps:

[0034] S1, setting PCIe debugging service on the host side, and setting PCIe debugging program on the PCIe board card side;

[0035] S2, organizing a first command package according to a preset format based on the PCIe debugging service, and submitting the first command package to the host double rate synchronous dynamic random access memory;

[0036] S3, in response to the board card double rate synchronous dynamic random access memory receiving an interrupt signal, obtaining a command from the host double rate synchronous dynamic random access memory and executing, organizing a second command package according to the command format, and returning the second command package to the host double rate synchronous dynamic random access memory; and

[0037] S4, in response to receiving a signal of completing interrupt, reading the second command package from the host double rate synchronous dynamic random access memory, and displaying the execution result.

[0038] Setting PCIe debugging service on the host side, and setting PCIe debugging program on the PCIe board card side. Figure 2 The architecture diagram of the system for debugging PCIe board card firmware provided by the present application is shown, and the Figure 2 The embodiments of the present application are described. The system architecture mainly includes three parts: PCIe Debug Service (PCIe debugging service), PCIe board card hardware and PCIe DebugDaemon (PCIe debugging program). The PCIe debugging service runs on the host, directly provides the above-mentioned service for the user, translates the user's instruction into a specific command format, and delivers it to the board card through PCIe; PCIe board card hardware: in addition to providing basic PCIe functions (such as DMA, sending interrupt to host, etc.), a separate BAR space needs to be provided, and when the BAR is updated, the board card firmware is reminded; the PCIe debugging program runs on the board card firmware, is responsible for responding to the request sent by the host, and realizes the corresponding function.

[0039] Specifically, the host side includes a PCIe debugging service and a host DDR (Double Data Rate). The PCIe debugging service runs on the host, is responsible for providing a debugging service interface, encapsulating a debugging protocol, communicating with a board card, and completing various debugging functions. The host DDR includes a Command RingBuffer, a Command Return RingBuffer, and File / Log Pages. The Command RingBuffer is used for the host (the PCIe Debug Service) to issue a command, the host places command information in the ringbuffer, and writes a command trigger register located on the board card BAR to notify the board card to move the command from the host. The Command Return RingBuffer is used for the board card to notify the host of return information, and the process is as follows: the board card moves the command return information to the ringbuffer through the PCIe protocol, and notifies the host of the arrival of the command return through a PCIe interrupt. Whether it is the Command RingBuffer or the Command Return RingBuffer, only short key information is carried, and a large amount of data, such as files and logs, is directly moved by the board card to the host memory page through the PCIe.

[0040] The board card side includes a PCIe debugging program and a board card DDR. The PCIe debugging program runs on the board card, is responsible for processing a shell command execution, log capture, and file transmission, and other debugging requests sent by the host through the protocol. The board card DDR includes a PCIe BAR, a LogBuffer, and a File Buffer. The PCIe BAR includes Device info and BAR Register. The Device info is mainly used to identify whether the PCIe board card supports the debugging protocol provided by the application, and is used to find the BAR supporting the debugging protocol. The BAR Register includes a host Ringbuffer address, length configuration, and a Command Trigger Register provided for the host. The Log Buffer is used to temporarily store Log information. The File Buffer is used to temporarily store files required for debugging reading and writing.

[0041] Initialization can be performed before formal debugging. Figure 3 The initialization flowchart of the embodiment of the application is as follows: Figure 3As shown, the initialization mainly includes: the PCIe Debug Service running on the host side acquires a PCIe device list through a command or function provided by a host operating system; a PCIe device list is traversed, and for each traversed PCIe device, each BAR of the device is scanned (whether a debugging protocol is supported is read); when a device supporting the debugging protocol is found, a Command RingBuffer and a Command Return RingBuffer are initialized in the host memory, and the first address and length information of the two RingBuffers are configured to the BAR register of the board card; the board card PCIe module generates an interrupt to the board card firmware, and the firmware is well recorded.

[0042] The PCIe Debug Service organizes a first command packet in a preset format based on the PCIe Debug Service, and submits the first command packet to the host double-rate synchronous dynamic random access memory.

[0043] In response to the board card double-rate synchronous dynamic random access memory receiving an interrupt signal, a command is acquired from the host double-rate synchronous dynamic random access memory and executed, a second command packet is organized in a command format according to an execution result, and the second command packet is returned to the host double-rate synchronous dynamic random access memory.

[0044] Figure 4 A Shell command execution flowchart of an embodiment of the present application is shown in FIG. 3. Figure 5 A Shell command format schematic diagram of an embodiment of the present application is shown in FIG. 4. The main process of Shell command execution is that the host composes a data packet in a format shown in FIG. 4, submits the data packet to the Command RingBuffer, and writes the Command Trigger register located on the board card PCIe BAR. After the board card receives the BAR Change interrupt, the shell command is carried from the host Command RingBuffer, and is executed in the board card firmware. The execution result is fed back to the Command Return RingBuffer, and an interrupt is triggered to remind the host that the command execution is completed. Figure 5

[0045] In some embodiments, the acquiring a command from the host double-rate synchronous dynamic random access memory and executing includes: in response to the command being a log grabbing, carrying a log generated by the board card firmware to a log page applied for by the host.

[0046] Figure 6 A Log grabbing flowchart of an embodiment of the present application is shown in FIG. 6. Figure 7 A Log grabbing command format schematic diagram of an embodiment of the present application is shown in FIG. 7. The main process of Log grabbing is that the host applies for a memory page, composes a data packet in a format shown in FIG. 7, submits the data packet to the Command RingBuffer, and writes the Command Trigger register located on the board card PCIe BAR. After the board card receives the BAR Change interrupt, the Log grabbing command is carried from the host Command RingBuffer, and is executed in the board card firmware. The execution result is fed back to the Command Return RingBuffer, and an interrupt is triggered to remind the host that the command execution is completed. Figure 7 ​The shown format constitutes a data packet, is submitted to a Command RingBuffer, and is written to a Command Trigger register located on a board card PCIe BAR. It is worth noting that the host can issue multiple Log acquisition commands; and after the Log is acquired, the command is issued again to achieve the effect of continuously acquiring the Log.

[0047] In some embodiments, the acquiring and executing the command from the host double-rate synchronous dynamic random access memory comprises: in response to the command being file pull-up, opening a file according to a file path in the command, reading the file into a page applied by the host, and judging whether the current reading reaches the end of the file; and in response to the current reading reaching the end of the file, closing the file.

[0048] Figure 8 The format of the file size acquisition command of the embodiment of the application is shown in the figure; Figure 9 The format of the file pull-up command of the embodiment of the application is shown in the figure; Figure 10 The file pull-up flowchart of the embodiment of the application is shown in the figure. The main steps of the file pull-up are that the host first acquires the size of the file to be pulled up according to the command format shown in the figure, and applies a memory page according to the file size; Figure 8 The command format shown in the figure is used to organize the command, which is submitted to a Command RingBuffer, and is written to a Command Trigger register located on a board card PCIe BAR. Figure 9

[0049] In some embodiments, the acquiring and executing the command from the host double-rate synchronous dynamic random access memory comprises: in response to the command being file pull-up, opening a file according to a file path in the command, reading the file into a page applied by the host, and judging whether the current reading reaches the end of the file; and in response to the current reading reaching the end of the file, closing the file.

[0050] Figure 11 The file pull-up flowchart of the embodiment of the application is shown in the figure. The main steps of the file pull-up are that the host first acquires the size of the file to be pulled up according to the command format shown in the figure, and applies a memory page according to the file size; Figure 12 The format of the file pull-up command of the embodiment of the application is shown in the figure; Figure 12 The command format shown in the figure is used to organize the command, which is submitted to a Command RingBuffer, and is written to a Command Trigger register located on a board card PCIe BAR.

[0051] In response to receiving a signal of a completion interrupt, reading the second command packet from the host double-rate synchronous dynamic random access memory, and displaying the execution result.

[0052] ​The application provides a general PCIe board card firmware debugging method, which effectively meets the shell access, log capture and file transmission requirements in the board card firmware development process. The application can complete the above functions through the PCIe protocol in-band without external other interfaces. The application can be integrated into any qualified PCIe device, and the host software can be adapted to various operating systems. A large amount of additional work for firmware debugging is greatly reduced, thereby improving the efficiency of firmware debugging.

[0053] It should be particularly pointed out that each step in each embodiment of the PCIe board card firmware debugging method can be crossed, replaced, added, deleted and reduced, and therefore, the reasonable permutation and combination transformation of the PCIe board card firmware debugging method should also belong to the protection scope of the application, and the protection scope of the application should not be limited to the embodiments.

[0054] Based on the above purpose, a second aspect of the embodiment of the application provides a PCIe board card firmware debugging system. As shown in the figure, Figure 13 The system 200 includes the following modules: a setting module configured to set a PCIe debugging service on the host side and set a PCIe debugging program on the PCIe board card side; a host module configured to organize a first command package in a preset format based on the PCIe debugging service and submit the first command package to a host double-rate synchronous dynamic random access memory; a board card module configured to respond to an interrupt signal received by a board card double-rate synchronous dynamic random access memory, acquire a command from the host double-rate synchronous dynamic random access memory and perform the command, organize a second command package in a command format according to the execution result, and return the second command package to the host double-rate synchronous dynamic random access memory; and a display module configured to respond to a signal of a completion interrupt, read the second command package from the host double-rate synchronous dynamic random access memory, and display the execution result.

[0055] In some embodiments, the board card module is configured to, in response to the command being log capture, carry logs generated by a board card firmware to a log page applied by a host.

[0056] In some embodiments, the board card module is configured to, in response to the command being file pull-up, open a file according to a file path in the command, read the file to a page applied by the host, and determine whether the current reading reaches the end of the file; and in response to the current reading reaching the end of the file, close the file.

[0057] In some embodiments, the board card module is configured to, in response to the command being file pull-down, open or create a file according to a file path in the command, carry corresponding data in the command to a board card memory, and write the data to the file according to an offset.

[0058] To achieve the above object, in a third aspect, the present application provides a computer device, comprising: at least one processor; and a memory storing computer instructions executable on the processor, the instructions being executed by the processor to implement the following steps: S1, setting a PCIe debugging service on a host side and setting a PCIe debugging program on a PCIe board card side; S2, organizing a first command package in a preset format based on the PCIe debugging service and submitting the first command package into a host double-rate synchronous dynamic random access memory; S3, in response to an interrupt signal being received by a board card double-rate synchronous dynamic random access memory, obtaining a command from the host double-rate synchronous dynamic random access memory and performing the command, organizing a second command package in a command format according to an execution result, and returning the second command package to the host double-rate synchronous dynamic random access memory; and S4, in response to a signal of a completion interrupt being received, reading the second command package from the host double-rate synchronous dynamic random access memory and displaying the execution result.

[0059] In some embodiments, the obtaining the command from the host double-rate synchronous dynamic random access memory and performing the command comprises: in response to the command being a log grabbing, carrying a log generated by a board card firmware into a log page applied for by a host.

[0060] In some embodiments, the obtaining the command from the host double-rate synchronous dynamic random access memory and performing the command comprises: in response to the command being a file pulling up, opening a file according to a file path in the command, reading the file into a page applied for by the host, and judging whether a current reading reaches an end of the file; and in response to the current reading reaching the end of the file, closing the file.

[0061] In some embodiments, the obtaining the command from the host double-rate synchronous dynamic random access memory and performing the command comprises: in response to the command being a file pulling down, opening or creating a file according to a file path in the command, carrying corresponding data in the command into a memory in a board card, and writing the data into the file according to an offset bit.

[0062] As shown in Figure 14 , it is a hardware structure schematic diagram of one embodiment of the computer device for PCIe board card firmware debugging provided by the present application.

[0063] As shown in Figure 14 , the device includes a processor 301 and a memory 302.

[0064] The processor 301 and the memory 302 can be connected through a bus or other means, Figure 14 for example, through a bus connection.

[0065] The memory 302, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules corresponding to the PCIe board firmware debugging method in this embodiment. The processor 301 executes various server functions and data processing by running the non-volatile software programs, instructions, and modules stored in the memory 302, thereby implementing the PCIe board firmware debugging method.

[0066] Memory 302 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created using methods for debugging PCIe board firmware. Furthermore, memory 302 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 302 may optionally include memory remotely located relative to processor 301, and these remote memories may be connected to the local module via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0067] The computer instructions 303 corresponding to one or more PCIe board firmware debugging methods are stored in memory 302. When executed by processor 301, the PCIe board firmware debugging method in any of the above method embodiments is executed.

[0068] Any embodiment of the computer device that performs the above-described PCIe board firmware debugging method can achieve the same or similar effects as any of the aforementioned method embodiments.

[0069] The present invention also provides a computer-readable storage medium storing a computer program that, when executed by a processor, performs a method for debugging PCIe board firmware.

[0070] like Figure 15 The diagram shown is a schematic representation of an embodiment of the computer storage medium for debugging the aforementioned PCIe board firmware provided by the present invention. Figure 15 Taking the computer storage medium shown as an example, the computer-readable storage medium 401 stores a computer program 402 that, when executed by a processor, performs the above method.

[0071] Finally, it needs to be explained that all or part of the processes in the above-mentioned embodiment methods can be implemented by a computer program to instruct relevant hardware to complete, and the program of the PCIe board card firmware debugging method can be stored in a computer readable storage medium. When the program is executed, it can include the processes of the above-mentioned embodiment methods. The storage medium of the program can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc. The above-mentioned computer program embodiments can achieve the same or similar effects as the corresponding any method embodiments.

[0072] The above is the exemplary embodiment disclosed by the present application, but it should be noted that various changes and modifications can be made without departing from the scope of the embodiments disclosed by the present application defined by the claims. The functions, steps and / or acts of the method claims described in the embodiments disclosed herein need not be performed in any particular order. In addition, although the elements of the embodiments disclosed by the present application can be described or claimed in individual form, they can also be understood as plural unless explicitly limited to singular.

[0073] It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that "and / or" as used herein refers to any and all possible combinations of one or more of the associated listed items.

[0074] The above-mentioned embodiment number of the embodiments disclosed by the present application is only for description, not representing the advantages and disadvantages of the embodiments.

[0075] It can be understood by those skilled in the art that all or part of the above-mentioned embodiments can be completed by hardware, or by a program to instruct relevant hardware, and the program can be stored in a computer readable storage medium. The above-mentioned storage medium can be a read-only memory, a disk or an optical disk, etc.

[0076] Those skilled in the art should understand that the above discussion of any embodiment is only exemplary and is not intended to imply that the scope of the embodiments disclosed by the present application (including claims) is limited to these examples; under the idea of the embodiments of the present application, the above embodiments or technical features in different embodiments can also be combined, and there are many other changes of different aspects of the embodiments of the present application as above. In order to be brief, they are not provided in details. Therefore, any omissions, modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the embodiments of the present application shall be included in the protection scope of the embodiments of the present application.

Claims

1. A method for debugging firmware on a PCIe board, characterized in that, Includes the following steps: Configure PCIe debugging service on the host side and PCIe debugging program on the PCIe board side; Based on the PCIe debugging service, the first command packet is organized according to a preset format and submitted to the host double-rate synchronous dynamic random access memory; In response to the board's Double Data Rate Synchronous Dynamic Random Access Memory (DRAM) receiving an interrupt signal, a command is retrieved from the host's DRAM and executed. Specifically, if the command is a file pull-up, the file is opened according to the file path specified in the command, the file is read into the page requested by the host, and it is determined whether the current read has reached the end of the file. In response to the current read reaching the end of the file, the file is closed. In response to the command to download the file, the file is opened or created according to the file path in the command, the data corresponding to the command is moved to the board memory, and written to the file according to the offset; the execution result is organized into a second command packet according to the command format, and the second command packet is returned to the host double-rate synchronous dynamic random access memory; and In response to receiving a completion interrupt signal, the second command packet is read from the host double-rate synchronous dynamic random access memory, and the execution result is displayed.

2. The method according to claim 1, characterized in that, The step of retrieving and executing commands from the host's double-rate synchronous dynamic random access memory includes: In response to the command to capture logs, the logs generated by the board firmware are moved to the log page requested by the host.

3. A system for debugging PCIe board firmware, characterized in that, include: The configuration module is used to set up PCIe debugging services on the host side and PCIe debugging programs on the PCIe board side. The host module is configured to organize a first command packet according to a preset format based on the PCIe debugging service, and submit the first command packet to the host double-rate synchronous dynamic random access memory. The board module is configured to, in response to an interrupt signal received by the board's Double Data Rate Synchronous Dynamic Random Access Memory (DRAM), retrieve and execute a command from the host's DRAM; wherein, in response to a file pull-up command, the module opens a file according to the file path in the command, reads the file into the page requested by the host, and determines whether the current read has reached the end of the file; and In response to the current read reaching the end of the file, the file is closed. In response to the command to download the file, the file is opened or created according to the file path in the command, the data corresponding to the command is moved to the board memory, and written to the file according to the offset; the execution result is organized into a second command packet according to the command format, and the second command packet is returned to the host double-rate synchronous dynamic random access memory; and The display module is configured to read the second command packet from the host double-rate synchronous dynamic random access memory in response to receiving a completion interrupt signal, and display the execution result.

4. The system according to claim 3, characterized in that, The board module is configured for: In response to the command to capture logs, the logs generated by the board firmware are moved to the log page requested by the host.

5. A computer device, characterized in that, include: At least one processor; as well as A memory storing computer instructions executable on the processor, which, when executed by the processor, implement the steps of the method according to any one of claims 1-2.

6. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1-2.

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