Key exchange or public key encryption optimization method and system based on Mersenne number

Abstract

The present invention discloses a key exchange or public key cryptographic encryption optimization method and system based on Mersenne numbers, comprising the following steps: in an application scenario of key exchange or public key cryptographic calculation, selecting or constructing a modulus of a modulo operation mod, replacing the modulo operation mod with a first modulo operation or a second modulo operation according to the modulus; when the selected modulus is a Mersenne number, or the modulus in the constructed algorithm is just a Mersenne number, replacing the modulo operation mod with a first modulo operation; when the selected or constructed modulus is a positive integer similar in form to a Mersenne number, replacing the modulo operation mod with a second modulo operation. The present invention can utilize the mathematical characteristics of Mersenne numbers to optimize modular addition, modular multiplication, and modular exponentiation operations, significantly reduce the complexity of calculation, and improve the speed of key exchange and public key cryptographic encryption and decryption.

Description

Technical Field

[0001] The present invention relates to the technical field of information security encryption authentication, and in particular to a key exchange or public key cryptographic encryption optimization method and system based on Mersenne numbers. Background Art

[0002] In today's world where information technology is developing rapidly, information security protection plays a vital role. In e-commerce and APP applications involving personal information, encryption and authentication security protection methods are often needed, such as key exchange, public key encryption and decryption, etc. The following are examples:

[0003] 1. Key Exchange

[0004] An example of a key exchange algorithm is the DHM (Diffie-Hellman-Merkle) algorithm (formerly known as the DH algorithm). This algorithm is based on the discrete logarithm problem and is a classic algorithm that pioneered the public key cryptography system. DHM key exchange does not require a complete public key cryptography (a pair of public key and private key) to encrypt and transmit the session key K. As long as the two parties negotiate a session key K, it will be sufficient.

[0005] After the key exchange, the obtained K is used as the key to perform the decryption algorithm between parties A and B using a single-key algorithm such as AES, because the DHM algorithm itself can only exchange keys and cannot directly encrypt and decrypt plaintext.

[0006] The general process of DHM+AES algorithm encrypted transmission is: Party A and Party B each secretly generate a random number, then exchange information through the DHM algorithm, combine the two random numbers to form a random key K, which is used as the session key for AES encryption and decryption, and then the two parties use the AES algorithm for encrypted communication.

[0007] 2. Public Key Cryptography

[0008] Public key cryptography is widely used, including digital signatures and session key exchange. For example, the PGP (Pretty Good Privacy) protocol supports RSA+AES encryption protocol, where RSA is a public key cryptography and AES is a single key cryptography. The encrypted communication process of the two is similar to the communication process of the aforementioned DHM key exchange, except that the DHM algorithm is replaced by the RSA algorithm, the number of interactions is one less than the DHM algorithm, and the encryption and decryption is a complete random key K, rather than the negotiated K value.

[0009] The general process of RSA+AES algorithm encrypted transmission is: Party A randomly generates a session key K, then encrypts K with Party B's public key of RSA, transmits it to Party B, Party B decrypts K with its own private key, and then both parties can use the session key K for AES encrypted communication.

[0010] The reason why the AES algorithm is used for actual content encryption communication instead of directly using the RSA algorithm for encryption communication (which is possible in principle) is that the RSA algorithm is much slower than AES. It only takes a short time to encrypt a random key K, but it will be very time-consuming to encrypt the plaintext of the entire communication process.

[0011] In addition to the RSA algorithm (based on the prime factorization problem), there are other public key cryptographic algorithms, such as the Elgamal algorithm (based on the discrete logarithm problem).

[0012] A common shortcoming of the key exchange and public key cryptographic algorithms such as DHM, RSA, and Elgamal is that they are slow in calculation speed. An important reason for the slow speed is that these encryption and decryption algorithms based on mathematical problems involve long integer operations (the length of long integers is usually more than 1024 bits in binary), which can only be realized through multiple complex operations using general 32-bit and 64-bit computers (Michael Welschenbach. Cryptography - C and C++ Implementation of Encryption Methods (Second Edition) [M]. Electronic Industry Press, 2003.).

[0013] A key operation in these calculations is modulo (i.e., integer division to get the remainder), and the operator is represented by mod. Modulo operations involve complex long integer division, which takes a lot of time. Modulo operations are also common operations that must be performed once in almost every step of the calculation. However, none of the existing algorithms mention Mersenne numbers, such as modular addition, modular multiplication, and modular exponentiation operations.

[0014] Modular addition: Y = A + B mod M

[0015] Modular multiplication: Y = A*B mod M

[0016] Modular power: Y = A B mod M

[0017] Among them, M is called the modulus, which is the divisor in the modulo (integer division remainder) operation. It is this mod operation that significantly slows down the calculation speed, especially the modular exponentiation operation. Assuming that A, B, and M are all 1024-bit integers, then a modular exponentiation operation requires a maximum of 2048 mod operations (including 1024 base squares and 1024 iterative multiplications). Therefore, how to improve the calculation speed becomes an important issue.

[0018] Brief Introduction of Existing Related Technologies

[0019] 1. Hardware parallel acceleration

[0020] Without changing the algorithm, hardware is directly used to increase the parallelism of the calculation, thereby achieving the acceleration effect. For example, array multipliers, FPGA customized acceleration circuits (such as dividers), ASIC dedicated circuits (such as RSA acceleration chips), etc. are used.

[0021] The disadvantage of this hardware method is that since the algorithm has not been simplified, the hardware is complex, costly, and consumes a lot of power. In addition, when the encryption algorithm software is ported to a platform without hardware acceleration, it can only be calculated by pure software, so the acceleration effect disappears.

[0022] 2. Software algorithm optimization, taking the Montgomery algorithm as an example

[0023] The Montgomery algorithm is an optimization of modular exponentiation operations. The main idea is to reduce division operations and thus reduce time consumption.

[0024] Although software optimization algorithms like the Montgomery algorithm can improve speed, the algorithms are relatively complex and not conducive to hardware implementation (hardware acceleration). Even if implemented in hardware, the circuits are inevitably complex and the cost is high.

[0025] Regarding Mersenne numbers, Mersenne numbers are of the form 2 n -1, which has some favorable mathematical properties. If a Mersenne number is prime, it is called a Mersenne prime. Let P = 2 n -1 is the Mersenne number. For all key exchange and public key cryptographic algorithms based on the discrete logarithm problem, such as DHM and Elgamal algorithm, if the Mersenne prime number M is used as the modulus, or in other algorithms such as RSA that do not use prime numbers as the modulus, the Mersenne number M is constructed as the modulus, then the modular addition, modular multiplication, and modular exponentiation operations in the calculation process do not require division, and a new fast method can be used. Summary of the invention

[0026] The purpose of the present invention is to overcome the shortcomings of existing encryption calculations in speed, provide a key exchange or public key cryptographic encryption optimization method and system based on Mersenne numbers, and provide a corresponding key exchange or public key cryptographic encryption calculation core circuit logic system based on Mersenne numbers, so as to utilize the mathematical properties of Mersenne numbers, optimize modular exponentiation operations, significantly reduce the complexity of calculations, improve calculation speed, simplify circuit design in hardware, improve performance and reduce power consumption.

[0027] The present invention is achieved by at least one of the following technical solutions.

[0028] The key exchange or public key cryptographic encryption optimization method based on Mersenne number comprises the following steps: in the application scenario of key exchange or public key cryptographic calculation, the modulus of the modulus operation mod is selected or constructed, and the modulus operation mod is replaced with the first modulus operation mod1 or the second modulus operation mod2 according to the modulus; when the selected modulus is the Mersenne number M=2 n -1, or when the modulus in the constructed algorithm happens to be a Mersenne number, the modulo operation mod is replaced by the first modulo operation mod1, where n is a positive integer;

[0029] When the selected or constructed modulus is a positive integer K=2 with a form similar to that of a Mersenne number n When -L is used, the modulo operation mod is replaced by the second modulo operation mod2.

[0030] Furthermore, application scenarios include algorithms based on discrete logarithm problems, algorithms based on prime factorization problems, algorithms based on discrete elliptic curve problems, and other algorithms with modular addition, modular multiplication, and modular exponentiation as the main operations.

[0031] Furthermore, the first modulo operation mod1 is a fast modulo operation without division.

[0032] Furthermore, the first modulo operation mod1 is as follows:

[0033] Let the modulus M be the Mersenne number, that is, M = 2 n -1, the result of the first modulo operation mod1 is the same as the result of the original modulo operation mod:

[0034] Modular addition: Y = A + B mod1 M = A + B mod(2 n -1), where A and B represent two addends of modular addition operation;

[0035] Modular multiplication: Y = A*B mod1 M = A*B mod(2 n -1), where A and B represent two multipliers of modular multiplication operation;

[0036] Modular power: Y = A B mod1 M=A B mod(2 n -1), where A represents the base of the modular exponentiation operation and B represents the exponent of the modular exponentiation operation.

[0037] Furthermore, the operation flow of the first modulo operation mod1 includes the following steps:

[0038] Step S101, taking an n-digit positive integer A and an n-digit positive integer B;

[0039] Step S102, determine whether it is a modular addition operation or a modular multiplication operation, and go to steps S103 and S104 respectively;

[0040] Step S103, calculate the addition result before modulo taking Y0=A+B, and go to step S105;

[0041] Step S104, calculating the multiplication result before modulo taking Y0=A*B;

[0042] Step S105, split Y0 into lower n bits Y1 and upper n bits Y2;

[0043] Step S106, calculate Y=Y1+Y2;

[0044] Step S107, determine whether Y=M, if not, go to step S109, where the modulus M is the Mersenne number;

[0045] Step S108, handle the overflow situation, set Y=0;

[0046] Step S109: The process ends, and Y is the result of the mod1 operation.

[0047] Furthermore, the second modulo operation mod2 is a fast modulo operation without division.

[0048] Furthermore, the second modulo operation mod2 is as follows:

[0049] The modulus is a positive integer K = 2 n -L, where L is a very small positive integer, usually L<2 6 =64, the calculation does not involve division:

[0050] Modular addition: Y = A + B mod2 K = A + B mod(2 n -L), where A and B represent two addends of modular addition operation;

[0051] Modular multiplication: Y = A*B mod2 K = A*B mod(2 n -L), where A and B represent two multipliers of modular multiplication operation;

[0052] Modular power: Y = A B mod2 K=A B mod(2 n -L), where A represents the base of the modular exponentiation operation and B represents the exponent of the modular exponentiation operation.

[0053] Furthermore, the operation flow of the second modulo operation mod2 includes the following steps:

[0054] Step S201: Take an n-digit positive integer A, an n-digit positive integer B, and a 6-digit positive integer L;

[0055] Step S202: Determine whether it is a modular addition operation or a modular multiplication operation, and go to Step S203 and Step S204 respectively;

[0056] Step S203: Calculate the addition operation result Y0 = A + B before taking the modulus, and go to Step S205;

[0057] Step S204: Calculate the multiplication operation result Y0 = A * B before taking the modulus;

[0058] Step S205: Split Y0 into the lower n bits Y1 and the higher n bits Y2;

[0059] Step S206: Calculate Y = Y1 + Y2 * L;

[0060] Step S207: If Y < K, go to Step S209, where the modulus K is a positive integer similar in form to a Mersenne number;

[0061] Step S208: Handle the overflow situation, let Y0 = Y - K, and in hardware implementation, let Y0 = Y + L - 2 n and then go to Step S205;

[0062] Step S209: The process ends, and Y is the result of the mod2 operation.

[0063] Furthermore, it includes one or more fast modular operation logic circuit components C1 that can support the first modular operation mod1; the fast modular operation logic circuit component C1 includes:

[0064] An n-bit register RegA for temporarily storing the input number A;

[0065] An n-bit register RegB for temporarily storing the input number B;

[0066] An n-bit adder ADD1 for adding two numbers and outputting an n-bit integer and a carry flag C;

[0067] An n-bit multiplier MUL for multiplying two numbers and outputting a 2n-bit integer;

[0068] A 2n-bit register RegY0 for temporarily storing intermediate data;

[0069] An n-bit adder ADD2 for completing the fast modular calculation and outputting an n-bit integer and a carry flag C;

[0070] A logic gate circuit including n AND gates and 1 NOT gate;

[0071] n-bit register RegY, used to temporarily store the output number Y;

[0072] Bits 0 to n-1 of the registers RegA and RegB are respectively output to two input terminals of an n-bit adder ADD1;

[0073] Bits 0 to n-1 of registers RegA and RegB are output to two input terminals of an n-bit multiplier MUL respectively;

[0074] The adder ADD1 outputs to bits 0 to n-1 of register RegY0, and the carry flag C is output to the nth bit of RegY0;

[0075] The multiplier MUL outputs bits 0 to 2n-1 of register RegY0;

[0076] The lower n bits and the upper n bits of the register RegY0 are output to the two input terminals of the n-bit adder ADD2 respectively;

[0077] The adder ADD2 outputs to one input of n AND gates, the carry flag C outputs to a NOT gate, and the NOT gate outputs to another input of n AND gates;

[0078] The n AND gates output bits 0 to n-1 of register RegY.

[0079] Furthermore, it includes one or more fast modulo operation logic circuit components C2, which can support the second modulo operation mod2; the fast modulo operation logic circuit component C2 includes:

[0080] The n-bit register RegA is used to temporarily store the input number A;

[0081] n-bit register RegB, used to temporarily store input number B;

[0082] n-bit adder ADD1, used to add two numbers, outputs an n-bit integer and a carry flag C;

[0083] The n-bit multiplier MUL1 is used to multiply two numbers and output a 2n-bit integer;

[0084] 2n-bit register RegY0, used to temporarily store intermediate data;

[0085] The L-bit register RegL is used to temporarily store the input number L;

[0086] The n-bit multiplier MUL2 is used for calculating the correction value in the modulo calculation;

[0087] The n+6-bit adder ADD2 is used to complete the fast modulo calculation and output an n+6-bit integer and a carry flag C(n..n+5). That is, if the nth to n+5th bits output all 0s and there is no higher carry, then C(n..n+5)=0, otherwise C(n..n+5)=1;

[0088] Logic gate circuit, with 1 NOT gate;

[0089] n+6-bit demultiplexer DMUX, one-to-two output;

[0090] n-bit register RegY, used to temporarily store the output number Y;

[0091] The n-bit adder ADD3 is used for overflow processing of the lower n bits;

[0092] Bits 0 to n-1 of the registers RegA and RegB are respectively output to two input terminals of an n-bit adder ADD1;

[0093] Bits 0 to n-1 of registers RegA and RegB are output to two input terminals of n-bit multiplier MUL1 respectively;

[0094] The adder ADD1 outputs to bits 0 to n-1 of register RegY0, and the carry flag C is output to the nth bit of RegY0;

[0095] The multiplier MUL1 outputs bits 0 to 2n-1 of register RegY0;

[0096] The lower n bits of register RegY0 are output to the lower n bits of one input terminal of n+6-bit adder ADD2;

[0097] The high n bits of register RegY0 are output to an input terminal of n-bit multiplier MUL2;

[0098] The register RegL outputs the lower 6 bits to the other input terminal of the n-bit multiplier MUL2;

[0099] The multiplier MUL2 outputs to the other input terminal of the n+6-bit adder ADD2;

[0100] The adder ADD2 outputs to the n+6-bit demultiplexer DMUX, the flag bit C(n..n+5) is output to a NOT gate, and the NOT gate outputs to the one-or-the-other selection terminal of the demultiplexer DMUX;

[0101] When the input of the selection terminal is 0, the lower n bits of one path in the demultiplexer DMUX are output to one input terminal of the adder ADD3, and the nth to n+5th bits of the same path are output to the nth to n+5th bits of the register RegY0. When the input of the selection terminal is 1, the lower n bits of the other path are output to the 0th to n-1th bits of the register RegY.

[0102] Register RegL outputs bits 0 to 5 to the other input terminal of adder ADD3;

[0103] Adder ADD3 outputs bits 0 to n-1 of register RegY0.

[0104] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0105] The method of the present invention can greatly reduce the time complexity of modular operations by using Mersenne numbers or approximate Mersenne numbers as moduli, thereby optimizing modular addition, modular multiplication and modular exponentiation operations, and improving the speed of key exchange and public key encryption and decryption.

[0106] The system of the present invention is a fast key exchange and public key cryptographic calculation core circuit logic system based on Mersenne numbers, and an improved logic system, which can simplify circuit design, improve performance and reduce power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0107] Figure 1 The present invention is a key exchange or public key encryption optimization method based on Mersenne numbers, and a flow chart of the first modulo operation mod1 with Mersenne numbers as the modulus;

[0108] Figure 2 This is a flow chart of the second modulo operation mod2 with the approximate Mersenne number as the modulus of the present invention;

[0109] Figure 3 Schematic diagram of the first modulo operation C1 circuit with Mersenne number as modulus according to the present invention;

[0110] Figure 4 FIG. 2 is a schematic diagram of a second modulo operation circuit C2 using an approximate Mersenne number as a modulus according to the present invention. DETAILED DESCRIPTION

[0111] The following is a further detailed description of one specific implementation method based on the Mersenne number (mod1 / C1) and another improved specific implementation method based on the approximate Mersenne number (mod2 / C2) of the present invention in conjunction with the embodiments and drawings, but the embodiments of the present invention are not limited thereto.

[0112] A key exchange or public key cryptographic encryption optimization method based on Mersenne numbers, comprising selecting or constructing a modulus of a modulus operation mod in an application scenario of key exchange or public key cryptographic calculation, replacing the modulus operation mod with a first modulus operation mod1 or a second modulus operation mod2 according to the modulus; when the selected modulus is a Mersenne number M=2 n-1, or when the modulus in the constructed algorithm happens to be a Mersenne number, the modulo operation mod is replaced by the first modulo operation mod1, where n is a positive integer;

[0113] When the selected or constructed modulus is a positive integer K=2 with a form similar to that of a Mersenne number n When -L is used, the modulo operation mod is replaced by the second modulo operation mod2.

[0114] Example 1

[0115] A key exchange or public key cryptographic encryption optimization method based on Mersenne numbers, the method comprising a combination of the following implementations:

[0116] In key exchange or public key cryptography related calculations, this embodiment chooses to use the Elgamal algorithm, and the DHM algorithm may also be selected.

[0117] In the Elgamal algorithm used, a Mersenne prime number M = 2 is selected n -1 as the modulus of the modulus operation mod, where n is a positive integer and can make M a prime number, for example n = 1279;

[0118] In the corresponding modular addition, modular multiplication, and modular exponentiation operations, the original modular operation mod is replaced by a specific first modular operation mod1 without division, where the first modular operation mod1 is expressed as follows:

[0119] Modular addition: Y = A + B mod1 M = A + B mod(2 n -1),

[0120] Modular multiplication: Y = A*B mod1 M = A*B mod(2 n -1),

[0121] Modular power: Y = A B mod1 M=A B mod(2 n -1), and the modular exponentiation operation is essentially split into multiple rounds of modular multiplication operation iterations, so only the first modular operation mod1 of modular addition and modular multiplication operations needs to be considered;

[0122] The implementation of the first modulo operation mod1, according to a specific calculation process, the division becomes addition, and its calculation process is as follows (see attached Figure 1 shown):

[0123] Step S101, taking an n-digit positive integer A and an n-digit positive integer B;

[0124] Step S102, determine whether it is a modular addition operation or a modular multiplication operation, and go to step S103 and step S104 respectively;

[0125] Step S103, calculate the addition result before modulo taking Y0=A+B, and go to step S105;

[0126] Step S104, calculating the multiplication result before modulo taking Y0=A*B;

[0127] Step S105, split Y0 into two parts: lower n bits (Y1) and higher n bits (Y2);

[0128] Step S106, calculate Y=Y1+Y2;

[0129] Step S107, determine whether Y=M, if not, go to step S109;

[0130] Step S108, handle the overflow situation, set Y=0;

[0131] Step S109: The process ends, and Y is the result of the mod1 operation.

[0132] Example 2

[0133] A system for implementing a key exchange or public key cryptographic encryption optimization method based on Mersenne numbers includes one or more fast modulo operation logic circuit components C1, capable of supporting a first modulo operation mod1;

[0134] The logic circuit component C1 includes the following components (such as the attached Figure 3 shown):

[0135] n-bit register RegA (301), used to temporarily store input number A;

[0136] n-bit register RegB (302), used to temporarily store input number B;

[0137] n-bit adder ADD1 (303), used for adding two numbers, outputting an n-bit integer and a carry flag C;

[0138] An n-bit multiplier MUL (304), used for multiplying two numbers and outputting a 2n-bit integer;

[0139] 2n-bit register RegY0 (305), used for temporarily storing intermediate data;

[0140] An n-bit adder ADD2 (306) is used to complete a fast modulo calculation and output an n-bit integer and a carry flag C;

[0141] A logic gate circuit, comprising n AND gates (308) and one NOT gate (307);

[0142] The n-bit register RegY (309) is used to temporarily store the output number Y.

[0143] Example 3

[0144] A Mersenne number-based key exchange or public key cryptographic encryption optimization method, comprising a combination of the following implementations:

[0145] In key exchange or public key cryptographic calculation, this embodiment chooses to use the RSA algorithm;

[0146] In the RSA algorithm used, the product K of two prime numbers is constructed, and K is exactly 2 n -L is used as the modulus of the modulus operation mod, where n is a positive integer and L is a very small positive integer, L<2 6 =64;

[0147] In the corresponding modular addition, modular multiplication, and modular exponentiation operations, the original modulo operation mod is replaced by a specific fast modulo operation mod2 without division, wherein the second modulo operation mod2 is expressed as follows:

[0148] Modular addition: Y = A + B mod2 K = A + B mod(2 n -L),

[0149] Modular multiplication: Y = A*B mod2 K = A*B mod(2 n -L),

[0150] Modular power: Y = A B mod2 K=A B mod(2 n -L), and the modular exponentiation operation is essentially split into multiple rounds of modular multiplication operations, so only the mod2 implementation of modular addition and modular multiplication operations needs to be considered;

[0151] The second modulo operation mod2 is implemented according to a specific calculation process, where division becomes addition and multiplication. The calculation process is as follows (see attached). Figure 2 shown):

[0152] Step S201, take an n-digit positive integer A, an n-digit positive integer B, and a 6-digit positive integer L;

[0153] Step S202, determine whether it is a modular addition operation or a modular multiplication operation, and go to steps S203 and S204 respectively;

[0154] Step S203, calculate the addition result Y0=A+B before taking the modulo, and go to step S205;

[0155] Step S204: Calculate the multiplication result Y0 = A * B before taking the modulus;

[0156] Step S205: Split Y0 into two parts: the lower n bits (Y1) and the higher n bits (Y2);

[0157] Step S206: Calculate Y = Y1 + Y2 * L;

[0158] Step S207: If Y < K, go to Step S209;

[0159] Step S208: Handle the overflow situation. In pure software implementation, let Y0 = Y - K, and in hardware implementation, let Y0 = Y + L - 2 n , then go to Step S205;

[0160] Step S209: The process ends, and Y is the result of the mod2 operation.

[0161] A system for optimizing key exchange or public key cryptography encryption based on Mersenne numbers, including one or more fast modulus operation logic circuit components C2 that can support the second modulus operation mod2;

[0162] The logic circuit component C2 includes the following devices (as shown in the appendix Figure 4 ):

[0163] An n-bit register RegA (401) for temporarily storing the input number A;

[0164] An n-bit register RegB (402) for temporarily storing the input number B;

[0165] An n-bit adder ADD1 (403) for adding two numbers and outputting an n-bit integer and a carry flag C;

[0166] An n-bit multiplier MUL1 (404) for multiplying two numbers and outputting a 2n-bit integer;

[0167] A 2n-bit register RegY0 (405) for temporarily storing intermediate data;

[0168] An L-bit register RegL (406) for temporarily storing the input number L;

[0169] An n-bit multiplier MUL2 (407) for calculating the correction value in modulus calculation;

[0170] An n + 6-bit adder ADD2 (408) for completing the fast modulus calculation and outputting an n + 6-bit integer and a carry flag C(n..n + 5), that is, if the output of bits n to n + 5 is all 0 and there is no higher carry, then C(n..n + 5) = 0, otherwise C(n..n + 5) = 1;

[0171] Logic gate circuit, with 1 NOT gate (410);

[0172] n+6-bit demultiplexer DMUX (409), one-to-two output;

[0173] n-bit register RegY (411), used to temporarily store the output number Y;

[0174] The n-bit adder ADD3 (412) is used for overflow processing of the lower n bits.

[0175] The above embodiments are preferred implementation modes of the present invention, but the implementation modes of the present invention are not limited to the above embodiments. Any other changes, modifications, substitutions, combinations, and simplifications made without departing from the spirit and principle of the present invention shall be equivalent replacement modes and shall be included in the protection scope of the present invention.

Claims

1. A system for optimizing key exchange or public key cryptography based on Mersenne numbers, characterized in that: It includes one or more fast modulo operation logic circuit components C1, capable of supporting a first modulo operation mod1, and one or more fast modulo operation logic circuit components C2, capable of supporting a second modulo operation mod2; The fast modulo operation logic circuit component C1 comprises: The n-bit register RegA is used to temporarily store the input number A; n-bit register RegB, used to temporarily store input number B; n-bit adder ADD1, used to add two numbers, outputs an n-bit integer and a carry flag C; The n-bit multiplier MUL is used to multiply two numbers and output a 2n-bit integer; 2n-bit register RegY0, used to temporarily store intermediate data; The n-bit adder ADD2 is used to complete the fast modulo calculation and output an n-bit integer and a carry flag C; Logic gate circuit, including n AND gates and 1 NOT gate; n-bit register RegY, used to temporarily store the output number Y; Bits 0 to n-1 of the registers RegA and RegB are respectively output to two input terminals of an n-bit adder ADD1; Bits 0 to n-1 of registers RegA and RegB are output to two input terminals of an n-bit multiplier MUL respectively; The adder ADD1 outputs to bits 0 to n-1 of register RegY0, and the carry flag C is output to the nth bit of RegY0; The multiplier MUL outputs bits 0 to 2n-1 of register RegY0; The lower n bits and the upper n bits of the register RegY0 are output to the two input terminals of the n-bit adder ADD2 respectively; The adder ADD2 outputs to one input of n AND gates, the carry flag C outputs to a NOT gate, and the NOT gate outputs to another input of n AND gates; The n AND gates output bits 0 to n-1 of register RegY; The fast modulo operation logic circuit component C2 comprises: The n-bit register RegA is used to temporarily store the input number A; n-bit register RegB, used to temporarily store input number B; n-bit adder ADD1, used to add two numbers, outputs an n-bit integer and a carry flag C; The n-bit multiplier MUL1 is used to multiply two numbers and output a 2n-bit integer; 2n-bit register RegY0, used to temporarily store intermediate data; The L-bit register RegL is used to temporarily store the input number L; The n-bit multiplier MUL2 is used for calculating the correction value in the modulo calculation; The n+6-bit adder ADD2 is used to complete the fast modulo calculation and output an n+6-bit integer and a carry flag C, that is, if the nth to n+5th bits output all 0s and there is no higher carry, then C=0, otherwise C=1; Logic gate circuit, with 1 NOT gate; n+6-bit demultiplexer DMUX, one-to-two output; n-bit register RegY, used to temporarily store the output number Y; The n-bit adder ADD3 is used for overflow processing of the lower n bits; Bits 0 to n-1 of the registers RegA and RegB are respectively output to two input terminals of an n-bit adder ADD1; Bits 0 to n-1 of registers RegA and RegB are output to two input terminals of n-bit multiplier MUL1 respectively; The adder ADD1 outputs to bits 0 to n-1 of register RegY0, and the carry flag C is output to the nth bit of RegY0; The outputs of multiplier MUL1 are sent to bits 0 to 2n - 1 of register RegY0. The lower n bits of register RegY0 are sent to the lower n bits of one input terminal of n + 6-bit adder ADD2. The upper n bits of register RegY0 are sent to one input terminal of n-bit multiplier MUL2. Register RegL is sent to the lower 6 bits of the other input terminal of n-bit multiplier MUL2. Multiplier MUL2 is sent to the other input terminal of n + 6-bit adder ADD2. Adder ADD2 is sent to n + 6-bit demultiplexer DMUX, flag bit C is sent to one NOT gate, and the output of the NOT gate is sent to the two-to-one selection terminal of demultiplexer DMUX. When the input of the selection terminal is 0, the lower n bits of one path of demultiplexer DMUX are sent to one input terminal of adder ADD3, and bits n to n + 5 of the same path are sent to bits n to n + 5 of register RegY0. When the input of the selection terminal is 1, the lower n bits of the other path are sent to bits 0 to n - 1 of register RegY. Register RegL is sent to bits 0 to 5 of the other input terminal of adder ADD3. Adder ADD3 is sent to bits 0 to n - 1 of register RegY0. The encryption optimization method of the system of the key exchange or public key cryptography encryption optimization method based on Mersenne numbers includes the following steps: In the application scenario of key exchange or public key cryptography, the modulus of the modulus operation mod is selected or constructed, and the modulus operation mod is replaced with the first modulus operation mod1 or the second modulus operation mod2 according to the modulus; when the selected modulus is the Mersenne number M=2 n -1, or when the modulus in the constructed algorithm happens to be a Mersenne number, the modulo operation mod is replaced by the first modulo operation mod1, where n is a positive integer; When the selected or constructed modulus is a positive integer K=2 with a form similar to Mersenne numbers n -L, replace the modulo operation mod with the second modulo operation mod2; The first modulo operation mod1 is as follows: Let the modulus M be the Mersenne number, that is, M=2 n -1, where n is a positive integer, the result of the first modulo operation mod1 is the same as the result of the original modulo operation mod: Modular addition: Y = A+B mod1 M = A+B mod (2 n -1), where A and B represent the two addends of the modular addition operation; Modular multiplication: Y = A*B mod1 M = A*B mod (2 n -1), where A and B represent the two multipliers of modular multiplication operation; Modular exponentiation: Y = A B mod1 M = A B mod (2 n -1), where A represents the base of modular exponentiation and B represents the exponent of modular exponentiation; The operation process of the first modulo operation mod1 includes the following steps: Step S101: Take n-bit positive integer A and n-bit positive integer B. Step S102: Determine whether it is a modulo addition operation or a modulo multiplication operation, and go to steps S103 and S104 respectively. Step S103: Calculate the addition operation result Y0 = A + B before taking the modulus, and go to step S105. Step S104: Calculate the multiplication operation result Y0 = A * B before taking the modulus. Step S105: Split Y0 into lower n bits Y1 and upper n bits Y2. Step S106: Calculate Y = Y1 + Y2. Step S107: Determine whether Y = M. If not, go to step S109, where the modulus M is a Mersenne number. Step S108: Handle the overflow situation, and set Y = 0. Step S109: The process ends, and Y is the result of the mod1 operation. The second modulo operation mod2 is as follows: The modulus is a positive integer K=2 n -L, where n is a positive integer, L is a positive integer, and L<2 6 , the second modulo operation mod2 does not include the division operation process: Modular addition: Y = A+B mod2 K = A+B mod (2 n -L), where A and B represent two addends of the modular addition operation; Modular multiplication: Y = A*B mod2 K = A*B mod (2 n -L), where A and B represent the two multipliers of the modular multiplication operation; Modular exponentiation: Y = A B mod2 K = A B mod (2 n -L), where A represents the base of modular exponentiation and B represents the exponent of modular exponentiation; The operation process of the second modulo operation mod2 includes the following steps: Step S201: Take n-bit positive integer A, n-bit positive integer B, and 6-bit positive integer L. Step S202: Determine whether it is a modulo addition operation or a modulo multiplication operation, and go to steps S203 and S204 respectively. Step S203: Calculate the addition operation result Y0 = A + B before taking the modulus, and go to step S205. Step S204: Calculate the multiplication operation result Y0 = A * B before taking the modulus. Step S205: Split Y0 into lower n bits Y1 and upper n bits Y2. Step S206: Calculate Y = Y1 + Y2 * L. Step S207: If Y < K, go to step S209, where the modulus K is a positive integer similar in form to a Mersenne number. Step S208: handle overflow, set Y0=YK, and in hardware implementation, set Y0=Y+L-2 n , then go to step S205; Step S209: The process ends, and Y is the result of the mod2 operation.

2. The system of key exchange or public key encryption optimization method based on Mersenne numbers according to claim 1, characterized in that: Application scenarios include algorithms based on the discrete logarithm problem, algorithms based on the prime factorization problem, algorithms based on the discrete elliptic curve problem, and other algorithms with modular addition, modular multiplication, and modular exponentiation as the main operations.

3. The system of key exchange or public key encryption optimization method based on Mersenne numbers according to claim 1, characterized in that: The first modulo operation mod1 is a fast modulo operation without division.

4. The system of key exchange or public key encryption optimization method based on Mersenne numbers according to claim 1, characterized in that: The second modulo operation mod2 is a fast modulo operation without division.

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