Method and device for processing excitation signal, electronic device, and storage medium

Abstract

The embodiments of the present invention disclose a method and device for processing an excitation signal, an electronic device, and a storage medium, which relate to the field of integrated circuit verification technology and can improve the adaptability of the excitation signal to different circuit modules being verified, thereby greatly improving the verification efficiency of different circuit modules being verified. The method includes: storing the original excitation signal under each clock cycle in a cache area in sequence to obtain a cached excitation signal; the cached excitation signal is divided into at least one signal segment according to the change of the logic level; in response to the presence of at least one complete segment in the signal segment, the first logic level of the cached excitation signal of any of the complete segments belongs to a preset regulated level type, and the number of clock cycles for which the first logic level lasts is less than or equal to a preset cycle threshold, adjusting the first logic level to a second logic level to obtain a processed signal; and generating a target excitation signal based on the processed signal.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit verification, and in particular to a method and device for processing an excitation signal, an electronic device, and a storage medium. Background Art

[0002] In the integrated circuit field, chip designs must be verified on a verification platform before tape-out to ensure their correctness. During verification, the verification platform must provide various stimuli to the circuit modules being verified. Depending on the circuit module being verified, these stimuli may have different pulse types (e.g., positive pulses, negative pulses), different pulse widths, and different delay requirements.

[0003] However, even for a well-designed excitation signal, the excitation signal may change due to temperature, interference, and other reasons. For example, due to temperature increase, the CPU (Central Processing Unit) frequency may increase, which may cause the frequency of the excitation signal to increase and the pulse width to narrow. Due to interference, the level jitter may also cause overly narrow pulses. In this case, if the circuit module to be verified is required to respond to each pulse, the circuit module may respond too frequently and will not produce an output signal with practical effect, thereby increasing the power consumption of the circuit module and invalid responses. To this end, overly narrow pulses can be filtered. However, the circuit modules to be verified are diverse, and the pulse type, pulse width, and delay requirements of the required excitation pulses are also different. Therefore, in the related art, corresponding simulation reference models can only be developed for each circuit module to be verified for verification, which is inefficient.

[0004] There is no effective solution in the related art to improve the verification efficiency of different circuit modules to be verified. Summary of the Invention

[0005] In view of this, an embodiment of the present invention provides a method and device for processing an excitation signal, an electronic device, and a storage medium, which can effectively improve the adaptability of the excitation signal to different verified circuit modules and greatly improve the verification efficiency of different verified circuit modules.

[0006] In a first aspect, an embodiment of the present invention provides a method for processing an excitation signal, comprising: sequentially storing an original excitation signal in each clock cycle into a buffer to obtain a buffered excitation signal, the buffer being used to store the buffered excitation signal for a preset number of clock cycles; dividing the buffered excitation signal into at least one signal segment based on changes in logic level, wherein the buffered excitation signals within the same signal segment are continuous and have the same logic level; in response to the presence of at least one complete segment in the signal segment, the first logic level of the buffered excitation signal in any of the complete segments belonging to a preset regulated level type, and the number of clock cycles for which the first logic level persists is less than or equal to a preset cycle threshold, adjusting the first logic level to a second logic level to obtain a processed signal, wherein the complete segment is a signal segment in which the start and end points of the buffered excitation signal continuously at the same logic level are both stored in the buffer; the regulated level type includes at least one of a high level and a low level, and the second logic level is different from the first logic level; the preset cycle threshold is less than the preset number of clock cycles; and at least one of the preset cycle threshold, the preset number of clock cycles, and the regulated level type is configurable; and generating a target excitation signal based on the processed signal.

[0007] Optionally, in response to the presence of at least one complete segment in the signal segment, the first logic level of the cached excitation signal of any of the complete segments belongs to a preset regulated level type, and the number of clock cycles for which the first logic level persists is less than or equal to a preset cycle threshold, adjusting the first logic level to a second logic level to obtain a processed signal includes: determining the logic level of the current original excitation signal to be stored in the cache area in the current clock cycle; obtaining the logic level of the cached excitation signal stored in the cache area in the previous clock cycle of the current clock cycle to obtain a previous cached excitation signal, the previous cached excitation signal belonging to the first signal segment, and the cached excitation signal in the first signal segment is at the first logic level; if the logic level of the current original excitation signal is not equal to the first logic level, determining that the first signal segment is the complete segment, and further determining whether the number of clock cycles for which the first logic level persists is less than or equal to the preset cycle threshold; if the number of clock cycles for which the first logic level persists is less than or equal to the preset cycle threshold, adjusting the first logic level of the cached excitation signal in the first signal segment to the second logic level to obtain the processed signal.

[0008] Optionally, the method further includes: when the logic level of the current original excitation signal is equal to the first logic level, determining that the first signal segment is an incomplete segment, and adding 1 to the number of clock cycles in which the first logic level lasts in the first signal segment.

[0009] Optionally, after storing the original excitation signal under each clock cycle into the cache area in sequence and obtaining the cached excitation signal, the first logic level in the first signal segment is adjusted to the second logic level, and before obtaining the processed signal, the method also includes: determining the level type of the first logic level of the cached excitation signal in the first signal segment.

[0010] Optionally, determining the level type of the first logic level of the cache excitation signal in the first signal segment includes: determining the logic level of the cache excitation signal of a second signal segment that is adjacent to the first signal segment and stored in the cache area before the cache excitation signal of the first signal segment; and determining the level type of the first logic level corresponding to the first signal segment based on the logic level of the cache excitation signal of the second signal segment.

[0011] Optionally, in response to the presence of at least one complete segment in the signal segment, the first logic level of the cache excitation signal of any complete segment belongs to a preset regulated level type, and the number of clock cycles for which the first logic level persists is less than or equal to a preset cycle threshold, the first logic level is adjusted to a second logic level to obtain a processed signal, including: regularly detecting whether the cache excitation signal of each signal segment in the cache area, except for the signal segments where the cache excitation signals that first enter and last enter the cache area are located, is at the first logic level, wherein the detection interval of the regular detection is less than the preset number of clock cycles; determining the number of clock cycles for which the cache excitation signal of each signal segment that is at the first logic level persists; adjusting the first logic level of the cache excitation signal in the signal segment where the number of clock cycles is less than or equal to the preset cycle threshold to the second logic level, to obtain the processed signal.

[0012] Optionally, the regulated level type and the preset period threshold have a corresponding relationship, and the preset period thresholds corresponding to different regulated level types are equal or different.

[0013] Optionally, the cache area includes at least one of the following: a first-in-first-out cache area and a shift register.

[0014] Optionally, adjusting the first logic level to a second logic level to obtain a processed signal includes: adjusting the first logic level of the cache excitation signal in the complete segment to the second logic level by performing a logical operation on the cache excitation signal stored in the cache area and preset data.

[0015] Optionally, before adjusting the first logic level of the cache excitation signal in the complete segment to the second logic level by performing a logical operation on the cache excitation signal stored in the cache area and the preset data, the method also includes: determining the cache position of the complete segment in the cache area; and constructing the preset data based on the cache position.

[0016] Optionally, constructing the preset data according to the cache position includes: performing a left shift operation and / or a right shift operation on the all-1 data corresponding to the cache area size according to the cache position to obtain the preset data.

[0017] Optionally, before storing the original excitation signal under each clock cycle into the cache area in sequence, the method further includes: receiving a parameter configuration instruction; and configuring the preset number of clock cycles, the regulated level type and the preset cycle threshold according to the parameter configuration instruction.

[0018] In a second aspect, an embodiment of the present invention further provides an excitation signal processing device, comprising: a storage unit, for storing the original excitation signal under each clock cycle into a cache area in sequence to obtain a cached excitation signal, wherein the cached excitation signal is used to store the cached excitation signal of a preset number of clock cycles; the cached excitation signal is divided into at least one signal segment according to the change of the logic level, and the cached excitation signals in the same signal segment are continuous and have the same logic level; an adjustment unit, for responding to the presence of at least one complete segment in the signal segment, the first logic level of the cached excitation signal of any complete segment belongs to a preset regulated level type, and the first logic level The number of clock cycles that the level continues is less than or equal to the preset cycle threshold, the first logic level is adjusted to the second logic level, and a processed signal is obtained, wherein the complete segment is a signal segment in which the starting point and the end point of the cache excitation signal that are continuously at the same logic level are both stored in the cache area; the regulated level type includes at least one of a high level and a low level, and the second logic level is different from the first logic level; the preset cycle threshold is less than the preset number of clock cycles; at least one of the preset cycle threshold, the preset number of clock cycles, and the regulated level type is configurable; a generating unit is used to generate a target excitation signal according to the processed signal.

[0019] Optionally, the adjustment unit includes: a first determination module, used to determine the logic level of the current original excitation signal to be stored in the cache area in the current clock cycle; an acquisition module, used to acquire the logic level of the cache excitation signal stored in the cache area in the previous clock cycle of the current clock cycle, and obtain the previous cache excitation signal, the previous cache excitation signal belongs to the first signal segment, and the cache excitation signal in the first signal segment is at the first logic level; a second determination module, used to determine that the first signal segment is the complete segment when the logic level of the current original excitation signal is not equal to the first logic level, and further determine whether the number of clock cycles for which the first logic level lasts is less than or equal to a preset cycle threshold; a first adjustment module, used to adjust the first logic level of the cache excitation signal in the first signal segment to the second logic level when the number of clock cycles for which the first logic level lasts is less than or equal to the preset cycle threshold, so as to obtain the processed signal.

[0020] Optionally, the device further includes: a counting unit, configured to determine that the first signal segment is an incomplete segment when the logic level of the current original excitation signal is equal to the first logic level, and to add 1 to the number of clock cycles in which the first logic level lasts in the first signal segment.

[0021] Optionally, the adjustment unit also includes a third determination module, which is used to determine the level type of the first logic level of the cached excitation signal in the first signal segment after storing the original excitation signal under each clock cycle in the cache area in sequence to obtain the cached excitation signal, and before adjusting the first logic level in the first signal segment to the second logic level to obtain the processed signal.

[0022] Optionally, the third determination module is specifically used to: determine the logic level of the cache excitation signal of the second signal segment that is adjacent to the first signal segment and stored in the cache area before the cache excitation signal of the first signal segment; and determine the level type of the first logic level corresponding to the first signal segment based on the logic level of the cache excitation signal of the second signal segment.

[0023] Optionally, the adjustment unit includes: a detection module for periodically detecting whether the cache excitation signal of each signal segment in the cache area, except for the signal segments where the cache excitation signals that first enter and last enter the cache area are located, is at the first logic level, wherein the detection interval of the periodic detection is less than the preset number of clock cycles; a fourth determination module for determining the number of clock cycles for which the cache excitation signal of each signal segment is at the first logic level; and a second adjustment module for adjusting the first logic level of the cache excitation signal in the signal segment where the number of clock cycles is less than or equal to the preset cycle threshold to the second logic level to obtain the processed signal.

[0024] Optionally, the regulated level type and the preset period threshold have a corresponding relationship, and the preset period thresholds corresponding to different regulated level types are equal or different.

[0025] Optionally, the cache area includes at least one of the following: a first-in-first-out cache area and a shift register.

[0026] Optionally, the adjustment unit is specifically configured to adjust the first logic level of the cache excitation signal in the complete segment to the second logic level by performing a logic operation on the cache excitation signal stored in the cache area and preset data.

[0027] Optionally, the device also includes: a determination unit for determining the cache position of the complete segment in the cache area before adjusting the first logic level of the cache excitation signal in the complete segment to the second logic level by performing a logical operation on the cache excitation signal stored in the cache area and the preset data; and a construction unit for constructing the preset data according to the cache position.

[0028] Optionally, the construction unit is specifically configured to perform a left shift operation and / or a right shift operation on the all-1 data corresponding to the cache area size according to the cache position to obtain the preset data.

[0029] Optionally, the device also includes: a receiving unit, used to receive a parameter configuration instruction before storing the original excitation signal under each clock cycle into the cache area in sequence; a configuration unit, used to configure the preset number of clock cycles, the regulated level type and the preset cycle threshold according to the parameter configuration instruction.

[0030] In a third aspect, an embodiment of the present invention further provides an electronic device, comprising: a housing, a processor, a memory, a circuit board, and a power supply circuit, wherein the circuit board is placed inside the space enclosed by the housing, and the processor and the memory are arranged on the circuit board; a power supply circuit for supplying power to various circuits or devices of the above-mentioned electronic device; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, and is used to execute the excitation signal processing method provided by any embodiment of the present invention.

[0031] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, which stores one or more programs, and the one or more programs can be executed by one or more processors to implement the excitation signal processing method provided by any embodiment of the present invention.

[0032] The excitation signal processing method and apparatus, electronic device, and storage medium provided by the embodiments of the present invention can sequentially store the original excitation signal in each clock cycle into a buffer to obtain a buffered excitation signal. The buffered excitation signal is divided into at least one signal segment based on changes in logic level, and the buffered excitation signals within the same signal segment are continuous and have the same logic level. In response to the signal segment including at least one complete segment, the first logic level of the buffered excitation signal in any of the complete segments belongs to a preset regulated level type, and the number of clock cycles for which the first logic level persists is less than or equal to a preset cycle threshold, the first logic level is adjusted to a second logic level to obtain a processed signal, and a target excitation signal is generated based on the processed signal. In this way, since at least one of the preset cycle threshold, the preset number of clock cycles, and the regulated level type can be configured according to the needs of different circuit modules to be verified when processing the buffered excitation signal in the buffer, and the excitation signal is adjusted accordingly based on the configuration, the adaptability of the excitation signal to different circuit modules to be verified is effectively improved, and the verification efficiency of different circuit modules to be verified is greatly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0034] Figure 1 A flow chart of a method for processing an excitation signal provided by an embodiment of the present invention;

[0035] Figure 2 is a schematic diagram of a signal segment in a buffer area in an embodiment of the present invention;

[0036] Figure 3 A schematic diagram of the input buffer, processing, and output buffer of the excitation signal in an embodiment of the present invention;

[0037] Figure 4 Another schematic diagram of the input buffer, processing, and output buffer of the excitation signal in an embodiment of the present invention;

[0038] Figure 5 A detailed flow chart of a method for processing an excitation signal provided by an embodiment of the present invention;

[0039] Figure 6 A simulation waveform diagram of the excitation signal processing method provided by an embodiment of the present invention;

[0040] Figure 7 Another simulation waveform diagram of the method for processing an excitation signal provided by an embodiment of the present invention;

[0041] Figure 8 Another simulation waveform diagram of the method for processing an excitation signal provided by an embodiment of the present invention;

[0042] Figure 9 A schematic structural diagram of an excitation signal processing device provided by an embodiment of the present invention;

[0043] Figure 10 A schematic structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0044] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0045] It should be understood that the embodiments described are only a portion of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative work are within the scope of protection of the present invention.

[0046] In a first aspect, an embodiment of the present invention provides a method for processing an excitation signal, which can effectively improve the adaptability of the excitation signal to different circuit modules to be verified, thereby greatly improving the verification efficiency of different circuit modules to be verified.

[0047] like Figure 1 As shown, an embodiment of the present invention provides a method for processing an excitation signal, comprising:

[0048] S11, sequentially storing the original excitation signal under each clock cycle into a buffer area to obtain a buffered excitation signal, wherein the buffer area is used to store the buffered excitation signal for a preset number of clock cycles; the buffered excitation signal is divided into at least one signal segment according to changes in logic levels, and the buffered excitation signals within the same signal segment are continuous and have the same logic level;

[0049] In order to verify the circuit module to be verified, an excitation signal can be provided to the circuit module to be verified in a verification environment, and the response of the circuit module to the excitation signal can be recorded. The excitation signal can be generated by an excitation source and input to the input end of the circuit module to be verified according to a clock beat. An excitation signal can be provided to the circuit module to be verified in each clock cycle. The excitation signals provided to the circuit module to be verified in each clock cycle can be the same or different, and can be specifically set according to the verification needs. For example, in one embodiment of the present invention, a circuit module has three input ports, and the three parallel excitation signals provided in the first clock cycle are logic levels "1", "0", and "1", the three parallel excitation signals provided in the second clock cycle are logic levels "0", "1", and "1", and the three parallel excitation signals provided in the third clock cycle are also logic levels "0", "1", and "1".

[0050] In an embodiment of the present invention, in order to avoid the circuit module being verified from frequently generating invalid responses after an overly narrow excitation signal pulse is input into the circuit module, the original excitation signal provided by the excitation source can be stored in a cache area in turn in each clock cycle to obtain a corresponding cached excitation signal so that the cached excitation signal can be further processed.

[0051] Specifically, the buffer area can be a region in a memory, or a register, etc., for storing the original excitation signal as a cached excitation signal. The buffer area can have a storage space of a preset size. After the cached excitation signal in the buffer area is processed, it can be used by subsequent steps or output from the buffer area, thereby freeing up storage space for the newly input original excitation signal. Therefore, the storage space of the buffer area does not need to be large, as long as it can meet the time required for processing the cached excitation signal. For example, in one embodiment of the present invention, the buffer area can be used to store a cached excitation signal of 8 clock cycles. In another embodiment of the present invention, the buffer area can be used to store a cached excitation signal of 16 clock cycles, etc.

[0052] Optionally, in different verification environments, or for different circuit modules to be verified, the specific buffer size can be set or adjusted as needed.

[0053] After the original stimulus signals of multiple clock cycles are sequentially stored in the buffer area, a cache stimulus signal of multiple clock cycles can be formed in the buffer area. The cache stimulus signal can be further divided into one or more signal segments according to the change of the logic level of the cache stimulus signal. For example, Figure 2 As shown, the logic level of the cache excitation signal corresponding to clock cycle A is the same as that of the cache excitation signal corresponding to its adjacent clock cycle A+1, both are logic 1, then the cache excitation signal corresponding to A and the cache excitation signal corresponding to A+1 belong to the same signal segment L1, and the logic level of the cache excitation signal corresponding to clock cycle A+2 and the cache excitation signal corresponding to its adjacent clock cycle A+3 are different, then the cache excitation signal corresponding to A+2 and the cache excitation signal corresponding to A+3 belong to two different signal segments.

[0054] S12, in response to the presence of at least one complete segment in the signal segment, the first logic level of the cached excitation signal of any of the complete segments being of a preset regulated level type, and the number of clock cycles for which the first logic level persists being less than or equal to a preset cycle threshold, adjusting the first logic level to a second logic level to obtain a processed signal, wherein the complete segment is a signal segment in which the start point and end point of the cached excitation signal continuously at the same logic level are both stored in the cache area; the regulated level type includes at least one of a high level and a low level, and the second logic level is different from the first logic level; the preset cycle threshold is less than the preset number of clock cycles; and at least one of the preset cycle threshold, the preset number of clock cycles, and the regulated level type is configurable;

[0055] Each signal segment may include 0, 1 or more complete segments. The complete segment is a signal segment in which the start and end points of the cached excitation signal that are continuously at the same logic level are both stored in the cache area. In other words, a complete segment is a signal segment in which both the start and end points are stored in the cache area. The start and end points correspond to a level jump of the cached excitation signal, for example, Figure 2 As shown, signal segment L2 is a complete segment. In contrast, if the buffer only stores the starting point of the cached excitation signal in the signal segment, only stores the ending point of the cached excitation signal, or neither the starting point nor the ending point is stored, then the signal segment is an incomplete segment. Because signals may be output from the buffer or new signals may enter the buffer, whether the two signal segments at the two ends of the buffer are complete segments needs to be determined based on other conditions, such as signals that have already been output from the buffer or signals that are about to be input into the buffer.

[0056] In one embodiment of the present invention, if no complete segment exists in the buffer, it indicates that only one or two signal segments are currently stored in the buffer. If only one signal segment is stored, the logic levels of the cached excitation signals stored in the buffer are all equal, and the number of clock cycles for which the corresponding logic level persists in the signal segment exceeds a preset cycle threshold. Therefore, no filtering is required. If two signal segments are stored, the system can continue to wait for subsequent input to detect whether a complete segment has arrived.

[0057] If there is at least one complete segment in each signal segment, it can be further determined whether to process the cached excitation signal of the complete segment. The current logic level of the cached excitation signal in the complete segment is a first logic level, and the level type of the first logic level can be either a high level or a low level. Regardless of whether the level type of the first logic level is a high level or a low level, as long as the first logic level belongs to the preset regulated level type, the cached excitation signal in the complete segment may become the object of adjustment. As for whether to adjust the cached excitation signal in the complete segment, it can be further detected whether the number of clock cycles in which the first logic level in the complete segment lasts is less than or equal to a preset cycle threshold. If the number of clock cycles that the first logic level lasts is less than or equal to the preset cycle threshold, it means that the duration of the first logic level is too short and it is a narrow pulse. Therefore, the narrow pulse can be filtered out by processing the cached excitation signal in the complete segment. For example, the narrow pulse can be filtered out by adjusting the first logic level to the second logic level, wherein the first logic level is different from the second logic level. For example, if the first logic level is high, the second logic level is low, and if the first logic level is low, the second logic level is high, and so on.

[0058] Optionally, in an embodiment of the present invention, the regulated level types may include high level (i.e., only filtering out too narrow high levels), low level (i.e., only filtering out too narrow low levels), high level and low level (i.e., both too narrow high levels and too narrow low levels must be filtered out), which can be set and adjusted as needed.

[0059] S13: Generate a target excitation signal according to the processed signal.

[0060] In this step, there are many methods for generating a target excitation signal based on the processed signal. For example, the processed signal in the buffer area can be directly output as the target excitation signal, or a new target excitation signal can be generated based on the processed signal in the buffer area, etc. The embodiments of the present invention are not limited to this.

[0061] It should be noted that since the cached excitation signal is stored in the cache area and output from the cache area in sequence according to the clock beat, the larger the cache area, the longer the cached excitation signal is stored in the cache area, that is, the obtained target excitation signal has a greater delay relative to the original excitation signal. Therefore, the delay of the target excitation signal can be adjusted by adjusting the cache area size to meet the different delay requirements of different circuit modules for the excitation signal.

[0062] The method for processing an excitation signal provided by an embodiment of the present invention can sequentially store the original excitation signal under each clock cycle into a buffer area to obtain a cached excitation signal, wherein the cached excitation signal is divided into at least one signal segment based on the change of the logic level, and the cached excitation signals within the same signal segment are continuous and have the same logic level. In response to the signal segment including at least one complete segment, the first logic level of the cached excitation signal in any of the complete segments belongs to a preset regulated level type, and the number of clock cycles for which the first logic level persists is less than or equal to a preset cycle threshold, the first logic level is adjusted to a second logic level to obtain a processed signal, and a target excitation signal is generated based on the processed signal. In this way, since at least one of the preset cycle threshold, the preset number of clock cycles, and the regulated level type can be configured according to the needs of different circuit modules to be verified when processing the cached excitation signal in the buffer area, and the excitation signal is adjusted accordingly based on the configuration, the adaptability of the excitation signal to different circuit modules to be verified is effectively improved, and the verification efficiency of different circuit modules to be verified is greatly improved.

[0063] Optionally, in order to provide appropriate excitation signals for different verified circuits, in one embodiment of the present invention, before step S11 sequentially stores the original excitation signal under each clock cycle into the cache area, the excitation signal processing method provided by the embodiment of the present invention may further include: receiving a parameter configuration instruction; and configuring the preset number of clock cycles, the regulated level type, and the preset cycle threshold according to the parameter configuration instruction. In this way, according to the specific needs of the verified circuit module, the cached excitation signal with a clock cycle number that is too small for the verified circuit module and a logic level that belongs to the regulated level type can be adjusted, thereby filtering out pulses that are too narrow and of the regulated level type, thereby efficiently providing appropriate excitation pulses for various verified circuit modules.

[0064] After completing the parameter configuration, in step S11, when the original excitation signal is stored in the buffer area, the buffer area used to store the cached excitation signal can be various memories or registers with a first-in-first-out function, for example, the buffer area can include a first-in-first-out buffer area, a shift register, etc. Optionally, the first-in-first-out of the excitation signal in the buffer area can be such that it enters the buffer area from a lower address end and exits the buffer area from a higher address end, or it can enter the buffer area from a higher address end and exit the buffer area from a lower address end, and this is not limited in the embodiments of the present invention.

[0065] After the original excitation signal is stored in the buffer area and the cached excitation signal is obtained, in step S12, the signal segment in the buffer area is mainly screened and operated. For example, the screening condition can be: a complete segment in the signal segment, the first logic level of the cached excitation signal of the complete segment belongs to the preset regulated level type, and the number of clock cycles for which the first logic level lasts is less than or equal to the preset cycle threshold. Among them, the regulated level type and the preset cycle threshold can have a corresponding relationship, and the preset cycle thresholds corresponding to different regulated level types can be equal or different. For example, in one embodiment of the present invention, the preset cycle threshold corresponding to the low level is 2, that is, the low level with a continuous number of clock cycles less than or equal to 2 needs to be processed, and the preset cycle threshold corresponding to the high level is 3, that is, the high level with a continuous number of clock cycles less than or equal to 3 needs to be processed.

[0066] In an embodiment of the present invention, when processing the cached excitation signal to filter out narrow pulses, a variety of processing strategies can be adopted. The filtering operation can be performed when the original excitation signal is stored in the cache area, or the filtering operation can be performed when the cached excitation signal is located in the middle position of the cache area. As long as the filtering operation can be completed before the cached excitation signal is output from the cache area, the embodiments of the present invention do not limit this.

[0067] Specifically, in one embodiment of the present invention, in response to the presence of at least one complete segment in the signal segment, the first logic level of the buffered excitation signal in any of the complete segments belongs to a preset regulated level type, and the number of clock cycles for which the first logic level persists is less than or equal to a preset cycle threshold, adjusting the first logic level to a second logic level to obtain the processed signal may specifically include:

[0068] determining a logic level of a current original stimulus signal to be stored in the buffer area within a current clock cycle;

[0069] Obtaining a logic level of a cache excitation signal stored in the cache area in a clock cycle previous to the current clock cycle to obtain a previous cache excitation signal, wherein the previous cache excitation signal belongs to a first signal segment, and the cache excitation signal in the first signal segment is at the first logic level;

[0070] When the logic level of the current original excitation signal is not equal to the first logic level, determining that the first signal segment is the complete segment, and further determining whether the number of clock cycles during which the first logic level lasts is less than or equal to a preset cycle threshold;

[0071] When the number of clock cycles during which the first logic level lasts is less than or equal to the preset cycle threshold, the first logic level of the buffered excitation signal in the first signal segment is adjusted to the second logic level to obtain the processed signal.

[0072] That is, in this embodiment, when the original excitation signal is about to be stored in the buffer, it is first determined whether the logic level of the original excitation signal is equal to the logic level of the cached excitation signal that was just stored in the buffer in the previous clock cycle. If they are not equal, it means that the last signal segment in the buffer has ended and the signal segment in the buffer is complete. If they are equal, it means that the last signal segment in the buffer is still continuing and the signal segment in the buffer is incomplete. In one embodiment of the present invention, when the logic level of the current original excitation signal is equal to the first logic level, the first signal segment can be determined to be an incomplete segment, and the number of clock cycles in which the first logic level in the first signal segment lasts is increased by 1, thereby counting the number of clock cycles in which the first signal segment lasts. In this way, a similar examination is performed on each original excitation signal that is about to be stored in the buffer, so that the complete segment in the buffer can be discovered at the first time and processed in a timely manner.

[0073] For example, if Figure 3 As shown, in one embodiment of the present invention, the cache excitation signals input into the cache area in each clock cycle are 00111111, respectively, where the left end corresponds to a later input time and the right end corresponds to an earlier input time. The preset cycle threshold is 2, and the regulated level type is a low level, that is, the low level with a clock cycle number less than or equal to 2 is to be filtered out.

[0074] Optionally, if the logic level of the current original excitation signal to be stored in the cache area in the current clock cycle is low (logic 0), since the cache excitation signal input into the cache area in the previous clock cycle is logic 0, the two are equal, indicating that the signal segment 00 in the cache area has not yet ended, then after the current original excitation signal is stored in the cache area, the cache area becomes 00011111. The number of clock cycles that the low level 0 in the 00 signal segment lasts can be added by 1, for example, the number of clock cycles can be changed from 2 to 3.

[0075] Optional, such as Figure 4 As shown, if the logic level of the current original excitation signal to be stored in the buffer area in the current clock cycle is high (logic 1), since the cache excitation signal input into the buffer area in the previous clock cycle is logic 0, the two are not equal, indicating that the 00 signal segment on the left side of the buffer area has finished input and is a complete segment. Moreover, since in the 00 signal segment on the left side, the logic level 0 belongs to the regulated level type, the number of clock cycles of 00's continuous low level 2 is equal to the preset cycle threshold 2. Therefore, the 00 signal segment on the left side can be processed, and its low level 0 is adjusted to the high level 1 to obtain the processed signal. After adjustment, the signal in the buffer area is 11111111, thereby effectively filtering out the too narrow low level (or negative pulse).

[0076] In order to accurately adjust the first logic level corresponding to the cached excitation signal in the first signal segment, in one embodiment of the present invention, the original excitation signal in each clock cycle is sequentially stored in the cache area. After obtaining the cached excitation signal, the first logic level in the first signal segment is adjusted to the second logic level. Before obtaining the processed signal, the excitation signal processing method provided by the embodiment of the present invention may further include: determining the level type of the first logic level of the cached excitation signal in the first signal segment, so that the first logic level can be adjusted to the second logic level according to the level type of the first logic level. For example, if the first logic level is a low level, it can be adjusted to a high level when the level adjustment is performed; if the first logic level is a high level, it can be adjusted to a low level when the level adjustment is performed.

[0077] In a specific implementation, determining the level type of the first logic level of the cached excitation signal in the first signal segment may include: determining the logic level of the cached excitation signal in a second signal segment that is adjacent to the first signal segment and stored in the cache area before the cached excitation signal in the first signal segment; and determining the level type of the first logic level corresponding to the first signal segment based on the logic level of the cached excitation signal in the second signal segment. It is understood that because the first signal segment is adjacent to the second signal segment, the level of the excitation signal in the first signal segment is different from the level of the excitation signal in the second signal segment. For example, the level type of the first logic level may be opposite to the logic level of the cached excitation signal in the second signal segment.

[0078] For example, in one embodiment of the present invention, the cached excitation signal in the buffer is 11000000, with the left side corresponding to a later input time and the right side corresponding to an earlier input time. The first signal segment is 11, and the second signal segment is 000000. The second signal segment is stored in the buffer before the first signal segment. Since the second signal segment is no longer the signal segment that most recently entered the buffer, this indicates that the signal in the second signal segment can be used for valid output. Therefore, the first logic level corresponding to the first signal segment can be determined based on the logic level of the cached excitation signal in the second signal segment. Therefore, the logic level of the cached excitation signal in the second signal segment can also be referred to as the reference level. For example, in this embodiment, if the logic level of the cached excitation signal in the second signal segment is 0, the first logic level corresponding to the first signal segment is 1. In subsequent steps, if the first logic level needs to be adjusted to the second logic level, that is, the high level of the excitation signal in the first signal segment is adjusted to a low level, i.e., 11000000 in the buffer is adjusted to 00000000.

[0079] The above-mentioned method of determining the level type of the first logic level can be applied to the processing of various types of regulated levels. Specifically, in the embodiment of the present invention, the regulated level type can be a high level, a low level, or a high level and a low level.

[0080] For example, in one embodiment of the present invention, the regulated level type is a high level, which means that the excitation signal that can be effectively outputted is a low level regardless of the pulse width. If the second signal segment is a low level, that is, the reference level is a low level at this time, then it can be determined that the first signal segment is a high level, which is exactly the level type that needs to be adjusted; if the second signal segment is a high level, then the first signal segment is a low level, and at this time the cached excitation signal of the first signal segment does not need to be adjusted.

[0081] Optionally, in another embodiment of the present invention, if the regulated level type is a low level, the excitation signal that can be effectively output is a high level regardless of the pulse width. If the second signal segment is a high level, that is, the reference level is a high level at this time, it can be determined that the first signal segment is a low level, which is exactly the level type that needs to be adjusted; if the second signal segment is a low level, the first signal segment is a high level, and at this time the cached excitation signal of the first signal segment does not need to be adjusted.

[0082] Alternatively, in another embodiment of the present invention, the regulated level type is a high level and a low level, and both the high level and the low level may be effectively output. Then, the effective level of the signal segment closest to the first signal segment is the current reference level, and the first logic level of the cached excitation signal in the first signal segment is opposite to the current reference level. For example, in one embodiment of the present invention, the buffer area has input at the left end and output at the right end. At a certain moment, the cached excitation signal in the buffer area is 01111000. Assuming that the original excitation signal to be stored in the buffer area in the current clock cycle is 1, the first signal segment 0 at the leftmost end is a complete segment, the second signal segment is 1111, and the current reference level is the high level of the second signal segment. Since the first logic level is opposite to the current reference level, it can be determined that the first logic level is a low level. In subsequent steps, if it is necessary to adjust the first logic level to the second logic level, that is, adjust the low level of the excitation signal in the first signal segment to a high level, that is, adjust 01111000 in the buffer area to 11111000.

[0083] The above embodiment describes in detail the situation where signal processing is performed when the original excitation signal is stored in the buffer area to filter out excessively narrow pulses, but the embodiments of the present invention are not limited to this. In other embodiments of the present invention, the cached excitation signal in the buffer area can also be processed at other times to filter out excessively narrow pulses.

[0084] Specifically, in one embodiment of the present invention, in step S12, in response to the first logic level of the buffered excitation signal of any of the complete segments belonging to a preset regulated level type and the number of clock cycles for which the first logic level persists being less than or equal to a preset cycle threshold, adjusting the first logic level to a second logic level to obtain the processed signal may specifically include:

[0085] Periodically detecting whether the cache excitation signal in each signal segment of the cache area, except for the signal segments where the cache excitation signal first enters the cache area and the signal segments where the cache excitation signal last enters the cache area, is at the first logic level, wherein a detection interval of the periodic detection is less than the preset number of clock cycles;

[0086] determining the number of clock cycles during which the buffer excitation signal of each of the signal segments at the first logic level persists;

[0087] The first logic level of the buffered excitation signal in the signal segment where the number of clock cycles is less than or equal to the preset cycle threshold is adjusted to the second logic level to obtain the processed signal.

[0088] That is to say, in this embodiment, the logic level of the original excitation signal that is about to enter the buffer zone in the current clock cycle is no longer detected, but the object of signal processing is located in each signal segment in the middle position of the buffer zone. Since the signal segments in the buffer zone are complete segments except for the signal segments where the cached excitation signals that enter the buffer zone first and last are located, the signal segments in the middle positions are complete segments. Therefore, by periodically detecting whether the cached excitation signals of each signal segment in these middle positions are at the first logic level, the signal segments that may need to be adjusted can be found in the buffer zone. Furthermore, the number of clock cycles that the cached excitation signal of each signal segment at the first logic level lasts can be determined. If the number of clock cycles is less than the preset cycle threshold, it means that the number of clock cycles that the cached excitation signal in the corresponding signal segment lasts is too small, which is an overly narrow pulse and can be filtered out.

[0089] If it is determined that the buffered excitation signal in a complete segment needs to be processed, then when specifically performing signal adjustment, adjusting the first logic level to a second logic level to obtain a processed signal may include: adjusting the first logic level of the buffered excitation signal in the complete segment to the second logic level by performing a logical operation on the buffered excitation signal stored in the buffer area and preset data. For example, if the buffered excitation signal in the buffer area is 00110111 and needs to be adjusted to 00111111, this can be achieved by performing an exclusive OR operation on 00110111 and the preset data 00001000.

[0090] Different complete segments are adjusted, and the corresponding preset data are also different. In order to determine the preset data, in one embodiment of the present invention, before adjusting the first logic level of the cached excitation signal in the complete segment to the second logic level by performing a logical operation on the cached excitation signal stored in the cache area and the preset data, the excitation signal processing method provided by the embodiment of the present invention may also include: determining the cache position of the complete segment in the cache area; and constructing the preset data according to the cache position. For example, in the aforementioned embodiment, it is necessary to adjust the cached excitation signal 00110111 in the cache area to 00111111, that is, to adjust the 5th bit from the left of the cached excitation signal, and adjust the 0 of the 5th bit from the left to 1. Therefore, the operation rule of the XOR operation that needs to be performed can be used to construct the preset data as 00001000.

[0091] Furthermore, to construct the preset data, in one embodiment of the present invention, the all-one data corresponding to the size of the cache area can be left-shifted and / or right-shifted according to the cache location to obtain the preset data. During the left-shift and right-shift operations, the trailing zeros can be padded. For example, to obtain the preset data 00001000, the all-one data 11111111 can be right-shifted by 7 bits to obtain 00000001, and then left-shifted by 3 bits to obtain 00001000.

[0092] The method for processing an excitation signal provided by the embodiment of the present invention is described in detail below through specific embodiments.

[0093] like Figure 5 As shown, the method for processing the excitation signal provided by the embodiment of the present invention may include:

[0094] S201, configuring signal processing parameters according to verification requirements of the circuit module to be verified;

[0095] Among them, the signal processing parameters may include a mode parameter MODE, that is, the type of regulated level. For example, when MODE=0, the regulated level is a high level, that is, narrow high pulses need to be filtered out; when MODE=1, the regulated level is a low level, that is, narrow low pulses need to be filtered out; when MODE=2, the regulated level is a high level and a low level, that is, narrow high pulses and narrow low pulses need to be filtered out.

[0096] The signal processing parameters may also include a buffer size. Optionally, the buffer size may be expressed as a power of 2, for example, 2 3, Indicates that the buffer size is 8, that is, it can store data for up to 8 clock cycles, 2 4, Indicates that the buffer size is 16, which means that a maximum of 16 clock cycles of data can be stored.

[0097] The signal processing parameters may also include a pulse width threshold. Optionally, the pulse width threshold may also be expressed as an exponential power of 2, for example, 2 1, Indicates that the pulse width threshold is 2 clock cycles.

[0098] S202, determining the logic level of the current original excitation signal to be stored in the buffer area in the current clock cycle;

[0099] S203, obtaining a logic level of a cache excitation signal stored in the cache area in a clock cycle previous to the current clock cycle to obtain a previous cache excitation signal; the previous cache excitation signal belongs to a first signal segment, and the cache excitation signal in the first signal segment is at the first logic level;

[0100] S204: Whether the logic level of the current original excitation signal is equal to the first logic level, if so, executing step S205; if not, executing step S206;

[0101] S205 , determining that the first signal segment is an incomplete segment, adding 1 to the number of clock cycles during which the first logic level lasts in the first signal segment, storing the current original excitation signal in a buffer, and jumping to step S202 ;

[0102] S206: Determine whether the first signal segment is the complete segment, and further determine whether the number of clock cycles during which the first logic level persists is less than or equal to a preset cycle threshold; if so, execute step S207; if not, jump to step S202;

[0103] S207, adjusting the first logic level of the cached excitation signal in the first signal segment to the second logic level to obtain a processed signal, and storing the current original excitation signal in a cache area;

[0104] S208: Generate a target excitation signal according to the processed signal, and jump to step S202.

[0105] Exemplarily, the code for implementing the excitation signal processing method provided by the embodiment of the present invention may be as follows:

[0106]

[0107]

[0108]

[0109]

[0110]

[0111] For example, the simulation diagrams of the signals obtained according to the above code can be as follows: Figures 6 to 8 As shown. Among them, Figure 6 The figure shows the schematic diagram of mode 0, which filters out narrow high pulses. Figure 7 The figure shows the schematic diagram of mode 1, which filters out narrow low pulses. Figure 8 The figure shows the schematic diagram of mode 2, which filters out narrow high pulses and narrow low pulses. It should be noted that since the buffer area stores 8 clock cycles of the cached excitation signal, Figures 6 to 8 In the figure, the output signal oSig is delayed by 8 clock cycles compared to the input signal iSig, which is indicated by the double arrows in the figure. When comparing the pulses before and after filtering, the corresponding signals should be compared.

[0112] By encapsulating the excitation signal processing method provided by the embodiment of the present invention to form a relatively independent function or module, it not only has high versatility and strong configurability, but also enhances the robustness of the simulation reference model, greatly improving the verification work efficiency.

[0113] In a second aspect, an embodiment of the present invention further provides an excitation signal processing device, which can effectively improve the adaptability of the excitation signal to different circuit modules to be verified, thereby greatly improving the verification efficiency of different circuit modules to be verified.

[0114] like Figure 9 As shown, the excitation signal processing device provided by the embodiment of the present invention may include:

[0115] The storage unit 31 is used to sequentially store the original excitation signal in each clock cycle into a buffer area to obtain a buffered excitation signal. The buffer area is used to store the buffered excitation signal for a preset number of clock cycles. The buffered excitation signal is divided into at least one signal segment according to the change of the logic level. The buffered excitation signals in the same signal segment are continuous and have the same logic level.

[0116] an adjustment unit 32 for adjusting the first logic level to a second logic level to obtain a processed signal in response to at least one complete segment existing in the signal segment, the first logic level of the cached excitation signal in any of the complete segments belonging to a preset regulated level type, and the number of clock cycles for which the first logic level persists being less than or equal to a preset cycle threshold, wherein the complete segment is a signal segment in which both the start point and the end point of the cached excitation signal continuously at the same logic level are stored in the cache area; the regulated level type includes at least one of a high level and a low level, and the second logic level is different from the first logic level; the preset cycle threshold is less than the preset number of clock cycles; and at least one of the preset cycle threshold, the preset number of clock cycles, and the regulated level type is configurable;

[0117] The generating unit 33 is configured to generate a target excitation signal according to the processed signal.

[0118] The excitation signal processing device provided by an embodiment of the present invention is capable of sequentially storing the original excitation signal under each clock cycle into a buffer area to obtain a cached excitation signal, wherein the cached excitation signal is divided into at least one signal segment based on the change of the logic level, and the cached excitation signals within the same signal segment are continuous and have the same logic level. In response to the signal segment including at least one complete segment, the first logic level of the cached excitation signal in any of the complete segments belongs to a preset regulated level type, and the number of clock cycles for which the first logic level persists is less than or equal to a preset cycle threshold, the first logic level is adjusted to a second logic level to obtain a processed signal, and a target excitation signal is generated based on the processed signal. In this way, since, when processing the cached excitation signal in the buffer area, at least one of the preset cycle threshold, the preset number of clock cycles, and the regulated level type can be configured according to the needs of different circuit modules to be verified, and the excitation signal is adjusted accordingly based on the configuration, the adaptability of the excitation signal to different circuit modules to be verified is effectively improved, and the verification efficiency of different circuit modules to be verified is greatly improved.

[0119] Optionally, the adjustment unit 32 may include:

[0120] A first determining module is used to determine the logic level of the current original excitation signal to be stored in the buffer area in the current clock cycle;

[0121] an acquisition module, configured to acquire a logic level of a cache excitation signal stored in the cache area in a clock cycle previous to the current clock cycle, to obtain a previous cache excitation signal, wherein the previous cache excitation signal belongs to a first signal segment, and the cache excitation signal in the first signal segment is at the first logic level;

[0122] a second determining module, configured to, if the logic level of the current original excitation signal is not equal to the first logic level, determine that the first signal segment is the complete segment, and further determine whether the number of clock cycles during which the first logic level persists is less than or equal to a preset cycle threshold;

[0123] The first adjustment module is configured to adjust the first logic level of the cached excitation signal in the first signal segment to the second logic level to obtain the processed signal when the number of clock cycles during which the first logic level lasts is less than or equal to the preset cycle threshold.

[0124] Optionally, the device may further include:

[0125] The counting unit is configured to determine that the first signal segment is an incomplete segment when the logic level of the current original excitation signal is equal to the first logic level, and add 1 to the number of clock cycles in which the first logic level lasts in the first signal segment.

[0126] Optionally, the adjustment unit 32 may also include a third determination module for determining the level type of the first logic level of the cached excitation signal in the first signal segment after storing the original excitation signal under each clock cycle in the cache area in sequence to obtain the cached excitation signal, and before adjusting the first logic level in the first signal segment to the second logic level to obtain the processed signal.

[0127] Optionally, the third determining module may be specifically configured to:

[0128] determining a logic level of a cache excitation signal of a second signal segment adjacent to the first signal segment and stored in the cache area before the cache excitation signal of the first signal segment;

[0129] The level type of the first logic level corresponding to the first signal segment is determined according to the logic level of the buffered excitation signal in the second signal segment.

[0130] Optionally, the adjustment unit 32 may include:

[0131] a detection module, configured to periodically detect whether the cache excitation signal in each signal segment of the cache area, excluding the signal segments containing the cache excitation signal that first enters the cache area and the cache excitation signal that last enters the cache area, is at the first logic level, wherein a detection interval of the periodic detection is less than the preset number of clock cycles;

[0132] a fourth determining module, configured to determine the number of clock cycles during which the buffered excitation signal of each signal segment at the first logic level lasts;

[0133] The second adjustment module is configured to adjust the first logic level of the cache excitation signal in the signal segment where the number of clock cycles is less than or equal to the preset cycle threshold to the second logic level to obtain the processed signal.

[0134] Optionally, the regulated level type and the preset period threshold have a corresponding relationship, and the preset period thresholds corresponding to different regulated level types are equal or different.

[0135] Optionally, the cache area includes at least one of the following: a first-in-first-out cache area and a shift register.

[0136] Optionally, the adjustment unit 32 may be specifically configured to adjust the first logic level of the cached excitation signal in the complete segment to the second logic level by performing a logic operation on the cached excitation signal stored in the cache area and preset data.

[0137] Optionally, the device may further include:

[0138] a determining unit, configured to determine a cache position of the complete segment in the cache area before adjusting the first logic level of the cache excitation signal in the complete segment to the second logic level by performing a logic operation on the cache excitation signal stored in the cache area and preset data;

[0139] A construction unit is configured to construct the preset data according to the cache location.

[0140] Optionally, the construction unit may be specifically configured to perform a left shift operation and / or a right shift operation on the all-1 data corresponding to the cache size according to the cache position to obtain the preset data.

[0141] Optionally, the device may further include:

[0142] The receiving unit is used to receive a parameter configuration instruction before sequentially storing the original stimulus signal in each clock cycle into the buffer area;

[0143] A configuration unit is used to configure the preset number of clock cycles, the regulated level type and the preset cycle threshold according to the parameter configuration instruction.

[0144] In a third aspect, an embodiment of the present invention further provides an electronic device that can effectively improve the adaptability of an excitation signal to different circuit modules to be verified, thereby greatly improving the verification efficiency of different circuit modules to be verified.

[0145] like Figure 10 As shown, the electronic device provided by an embodiment of the present invention may include: a shell 51, a processor 52, a memory 53, a circuit board 54 and a power supply circuit 55, wherein the circuit board 54 is placed inside the space enclosed by the shell 51, and the processor 52 and the memory 53 are arranged on the circuit board 54; the power supply circuit 55 is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory 53 is used to store executable program code; the processor 52 runs the program corresponding to the executable program code by reading the executable program code stored in the memory 53, so as to execute the excitation signal processing method provided by any of the aforementioned embodiments.

[0146] The specific execution process of the above steps by the processor 52 and the steps further executed by the processor 52 by running the executable program code can be found in the description of the above embodiment and will not be repeated here.

[0147] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, which stores one or more programs, and the one or more programs can be executed by one or more processors to implement any of the excitation signal processing methods provided in the aforementioned embodiments, thereby also achieving the corresponding technical effects, which have been described in detail above and will not be repeated here.

[0148] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0149] Each embodiment in this specification is described in a related manner. The same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the differences from other embodiments.

[0150] In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0151] For the convenience of description, the above device is described as being divided into various units / modules based on their functions. Of course, when implementing the present invention, the functions of each unit / module can be implemented in the same or multiple software and / or hardware.

[0152] Those skilled in the art will appreciate that all or part of the processes in the above-described method embodiments can be implemented by instructing related hardware through a computer program. The program can be stored in a computer-readable storage medium, and when executed, the program can include the processes in the above-described method embodiments. The storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

[0153] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A method for processing an excitation signal, characterized in that: include: The original excitation signal under each clock cycle is sequentially stored in a buffer area to obtain a buffered excitation signal, wherein the buffer area is used to store the buffered excitation signal of a preset number of clock cycles; The buffer excitation signal is divided into at least one signal segment according to the change of the logic level, and the buffer excitation signals in the same signal segment are continuous and have the same logic level; In response to the presence of at least one complete segment in the signal segment, the first logic level of the cached excitation signal of any of the complete segments belongs to a preset regulated level type, and the number of clock cycles for which the first logic level persists is less than or equal to a preset cycle threshold, the first logic level is adjusted to a second logic level to obtain a processed signal, wherein the complete segment is a signal segment in which the start and end points of the cached excitation signal continuously at the same logic level are both stored in the cache area; the regulated level type includes at least one of a high level and a low level, and the second logic level is different from the first logic level; if the number of clock cycles for which the first logic level persists is less than or equal to the preset cycle threshold, it is a narrow pulse, and the narrow pulse is filtered out by processing the cached excitation signal in the complete segment; the preset cycle threshold is less than the preset number of clock cycles; the preset cycle threshold, the preset number of clock cycles, and the regulated level type are configurable; A target excitation signal is generated according to the processed signal.

2. The method according to claim 1, characterized in that In response to the presence of at least one complete segment in the signal segments, the first logic level of the buffered excitation signal in any of the complete segments belongs to a preset regulated level type, and the number of clock cycles for which the first logic level persists is less than or equal to a preset cycle threshold, adjusting the first logic level to a second logic level to obtain a processed signal includes: determining a logic level of a current original stimulus signal to be stored in the buffer area within a current clock cycle; Obtaining a logic level of a cache excitation signal stored in the cache area in a clock cycle previous to the current clock cycle to obtain a previous cache excitation signal, wherein the previous cache excitation signal belongs to a first signal segment, and the cache excitation signal in the first signal segment is at the first logic level; When the logic level of the current original excitation signal is not equal to the first logic level, determining that the first signal segment is the complete segment, and further determining whether the number of clock cycles during which the first logic level lasts is less than or equal to a preset cycle threshold; When the number of clock cycles during which the first logic level lasts is less than or equal to the preset cycle threshold, the first logic level of the buffered excitation signal in the first signal segment is adjusted to the second logic level to obtain the processed signal.

3. The method according to claim 2, characterized in that The method further comprises: When the logic level of the current original excitation signal is equal to the first logic level, the first signal segment is determined to be an incomplete segment, and the number of clock cycles in which the first logic level lasts in the first signal segment is increased by 1.

4. The method according to claim 2, characterized in that After sequentially storing the original stimulus signal in each clock cycle into a buffer area to obtain the buffered stimulus signal, and before adjusting the first logic level in the first signal segment to the second logic level to obtain the processed signal, the method further includes: A level type of the first logic level at which the buffer excitation signal is located in the first signal section is determined.

5. The method according to claim 4, characterized in that The determining the level type of the first logic level of the buffered excitation signal in the first signal segment includes: determining a logic level of a cache excitation signal of a second signal segment adjacent to the first signal segment and stored in the cache area before the cache excitation signal of the first signal segment; The level type of the first logic level corresponding to the first signal segment is determined according to the logic level of the buffered excitation signal in the second signal segment.

6. The method according to claim 1, characterized in that In response to the presence of at least one complete segment in the signal segments, the first logic level of the buffered excitation signal in any of the complete segments belongs to a preset regulated level type, and the number of clock cycles for which the first logic level persists is less than or equal to a preset cycle threshold, adjusting the first logic level to a second logic level to obtain a processed signal includes: Periodically detecting whether the cache excitation signal in each signal segment of the cache area, except for the signal segments where the cache excitation signal first enters the cache area and the signal segments where the cache excitation signal last enters the cache area, is at the first logic level, wherein a detection interval of the periodic detection is less than the preset number of clock cycles; determining the number of clock cycles during which the buffer excitation signal of each of the signal segments at the first logic level persists; The first logic level of the buffered excitation signal in the signal segment where the number of clock cycles is less than or equal to the preset cycle threshold is adjusted to the second logic level to obtain the processed signal.

7. The method according to claim 1, characterized in that The regulated level types have a corresponding relationship with the preset period thresholds, and the preset period thresholds corresponding to different regulated level types are equal or different.

8. The method according to claim 1, characterized in that The buffer area includes at least one of the following: a first-in-first-out buffer area and a shift register.

9. The method according to any one of claims 1 to 8, characterized in that The adjusting the first logic level to a second logic level to obtain a processed signal includes: The first logic level of the buffered excitation signal in the complete section is adjusted to the second logic level by performing a logic operation on the buffered excitation signal stored in the buffer area and preset data.

10. The method according to claim 9, characterized in that Before adjusting the first logic level of the buffered excitation signal in the complete segment to the second logic level by performing a logic operation on the buffered excitation signal stored in the buffer area and preset data, the method further includes: Determining a cache location of the complete segment in the cache area; The preset data is constructed according to the cache location.

11. The method according to claim 10, characterized in that The constructing the preset data according to the cache location includes: According to the cache position, a left shift operation and / or a right shift operation is performed on the all-1 data corresponding to the cache area size to obtain the preset data.

12. The method according to any one of claims 1 to 8, characterized in that Before sequentially storing the original excitation signal in each clock cycle into the buffer area, the method further includes: Receive parameter configuration instructions; According to the parameter configuration instruction, the preset number of clock cycles, the regulated level type and the preset cycle threshold are configured.

13. A device for processing an excitation signal, characterized in that: include: A storing unit, configured to sequentially store the original excitation signal under each clock cycle into a buffer area to obtain a buffered excitation signal, wherein the buffer area is configured to store the buffered excitation signal for a preset number of clock cycles; The buffer excitation signal is divided into at least one signal segment according to the change of the logic level, and the buffer excitation signals in the same signal segment are continuous and have the same logic level; an adjustment unit for adjusting the first logic level to a second logic level in response to at least one complete segment existing in the signal segment, the first logic level of the cached excitation signal in any of the complete segments belonging to a preset regulated level type, and the number of clock cycles for which the first logic level persists being less than or equal to a preset cycle threshold, to obtain a processed signal, wherein the complete segment is a signal segment in which the start and end points of the cached excitation signal continuously at the same logic level are both stored in the cache area; the regulated level type includes at least one of a high level and a low level, and the second logic level is different from the first logic level; if the number of clock cycles for which the first logic level persists is less than or equal to the preset cycle threshold, it is a narrow pulse, and the narrow pulse is filtered out by processing the cached excitation signal in the complete segment; the preset cycle threshold is less than the preset number of clock cycles; the preset cycle threshold, the preset number of clock cycles, and the regulated level type are configurable; A generating unit is configured to generate a target excitation signal according to the processed signal.

14. The device according to claim 13, characterized in that The adjustment unit includes: A first determining module is used to determine the logic level of the current original excitation signal to be stored in the buffer area in the current clock cycle; an acquisition module, configured to acquire a logic level of a cache excitation signal stored in the cache area in a clock cycle previous to the current clock cycle, to obtain a previous cache excitation signal, wherein the previous cache excitation signal belongs to a first signal segment, and the cache excitation signal in the first signal segment is at the first logic level; a second determining module, configured to, if the logic level of the current original excitation signal is not equal to the first logic level, determine that the first signal segment is the complete segment, and further determine whether the number of clock cycles during which the first logic level persists is less than or equal to a preset cycle threshold; The first adjustment module is configured to adjust the first logic level of the cached excitation signal in the first signal segment to the second logic level to obtain the processed signal when the number of clock cycles during which the first logic level lasts is less than or equal to the preset cycle threshold.

15. The device according to claim 14, characterized in that The device further comprises: The counting unit is configured to determine that the first signal segment is an incomplete segment when the logic level of the current original excitation signal is equal to the first logic level, and add 1 to the number of clock cycles in which the first logic level lasts in the first signal segment.

16. The device according to claim 14, characterized in that The adjustment unit also includes a third determination module, which is used to determine the level type of the first logic level of the cached excitation signal in the first signal segment after storing the original excitation signal under each clock cycle in the cache area in sequence to obtain the cached excitation signal and before adjusting the first logic level in the first signal segment to the second logic level to obtain the processed signal.

17. The device according to claim 16, characterized in that The third determining module is specifically configured to: determining a logic level of a cache excitation signal of a second signal segment adjacent to the first signal segment and stored in the cache area before the cache excitation signal of the first signal segment; The level type of the first logic level corresponding to the first signal segment is determined according to the logic level of the buffered excitation signal in the second signal segment.

18. The device according to claim 13, characterized in that The adjustment unit includes: a detection module, configured to periodically detect whether the cache excitation signal in each signal segment of the cache area, excluding the signal segments containing the cache excitation signal that first enters the cache area and the cache excitation signal that last enters the cache area, is at the first logic level, wherein a detection interval of the periodic detection is less than the preset number of clock cycles; a fourth determining module, configured to determine the number of clock cycles during which the buffered excitation signal of each signal segment at the first logic level lasts; The second adjustment module is configured to adjust the first logic level of the cache excitation signal in the signal segment where the number of clock cycles is less than or equal to the preset cycle threshold to the second logic level to obtain the processed signal.

19. The device according to claim 13, characterized in that The regulated level types have a corresponding relationship with the preset period thresholds, and the preset period thresholds corresponding to different regulated level types are equal or different.

20. The device according to claim 13, wherein The buffer area includes at least one of the following: a first-in-first-out buffer area and a shift register.

21. The device according to any one of claims 13 to 20, characterized in that The adjustment unit is specifically configured to adjust the first logic level of the buffered excitation signal in the complete segment to the second logic level by performing a logic operation on the buffered excitation signal stored in the buffer area and preset data.

22. The device according to claim 21, characterized in that Also includes: a determining unit, configured to determine a cache position of the complete segment in the cache area before adjusting the first logic level of the cache excitation signal in the complete segment to the second logic level by performing a logic operation on the cache excitation signal stored in the cache area and preset data; A construction unit is configured to construct the preset data according to the cache location.

23. The device according to claim 22, characterized in that The construction unit is specifically configured to perform a left shift operation and / or a right shift operation on the all-1 data corresponding to the size of the cache area according to the cache position to obtain the preset data.

24. The device according to any one of claims 13 to 20, characterized in that Also includes: The receiving unit is used to receive a parameter configuration instruction before sequentially storing the original stimulus signal in each clock cycle into the buffer area; A configuration unit is used to configure the preset number of clock cycles, the regulated level type and the preset cycle threshold according to the parameter configuration instruction.

25. An electronic device, characterized in that: The electronic device includes: a shell, a processor, a memory, a circuit board and a power supply circuit, wherein the circuit board is placed inside the space enclosed by the shell, and the processor and the memory are arranged on the circuit board; the power supply circuit is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory is used to store executable program code; the processor runs the program corresponding to the executable program code by reading the executable program code stored in the memory, and is used to execute the excitation signal processing method described in any one of claims 1 to 12.

26. A computer-readable storage medium, characterized in that The computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the method for processing an excitation signal according to any one of claims 1 to 12.

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