Oscillator layout

Abstract

An embodiment of the present invention provides an oscillator layout, including: a first row of layout areas, which are sequentially arranged side by side with a second B layout area, a second A layout area, a third B layout area, and a third A layout area; a second row of layout areas, which are sequentially arranged side by side with a first A layout area, a first B layout area, a fourth A layout area, and a fourth B layout area; wherein, the inputs and outputs of the first A layout area, the second A layout area, the third A layout area, and the fourth A layout area form a first ring topology structure, the inputs and outputs of the first B layout area and the third B layout area form a second ring topology structure, the inputs and outputs of the second B layout area and the fourth B layout area form a third ring topology structure, and both the second ring topology structure and the third ring topology structure are electrically connected to the first ring topology structure.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductors, and in particular to an oscillator layout. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory device commonly used in computers. It consists of many repeated memory cells. In DRAM I / O circuits, a high-speed clock signal with a specific frequency is required for reading, writing, and clock calibration.

[0003] A ring oscillator can be used to generate a high-speed clock signal within the DRAM to meet these requirements. The layout for a ring oscillator includes multiple layers of metal interconnects. The metals in different layers have different orientations, materials, and electrical properties. Furthermore, the electrical properties of the connecting holes between different metal layers vary, leading to different parasitic parameters. Therefore, the layout must consider requirements such as symmetry, matching, and minimal parasitic loading to improve the oscillator's electrical performance. Summary of the Invention

[0004] An embodiment of the present invention provides an oscillator layout, which improves the symmetry of the layout and reduces parasitic parameters.

[0005] To solve the above problems, an embodiment of the present invention provides an oscillator layout, comprising: an A layout area, wherein the A layout area includes a first A layout area, a second A layout area, a third A layout area, and a fourth A layout area; a B layout area, wherein the B layout area includes a first B layout area, a second B layout area, a third B layout area, and a fourth B layout area, and the A layout area and the B layout area are both layouts of inverters; a first row layout area, wherein the second B layout area, the second A layout area, the third B layout area, and the third A layout area are arranged side by side in sequence; a second row layout area, wherein the first The A layout area, the first B layout area, the fourth A layout area, and the fourth B layout area are arranged side by side in sequence; wherein, the inputs and outputs of the first A layout area, the second A layout area, the third A layout area, and the fourth A layout area constitute a first ring topology structure, the inputs and outputs of the first B layout area and the third B layout area constitute a second ring topology structure, the inputs and outputs of the second B layout area and the fourth B layout area constitute a third ring topology structure, and the second ring topology structure and the third ring topology structure are both electrically connected to the first ring topology structure.

[0006] In addition, the area of the A layout area is larger than the area of the B layout area.

[0007] In addition, the heights of the A-layout area and the B-layout area are the same, and the length of the A-layout area is greater than the length of the B-layout area.

[0008] In addition, the output of the second A-layout area is electrically connected to the input of the third A-layout area and has a second-third length, the output of the fourth A-layout area is electrically connected to the input of the first A-layout area and has a fourth-first length, and the second-third length is equal to the fourth-first length.

[0009] In addition, the output of the first A-layout area is electrically connected to the input of the second A-layout area and has a first-second height, the output of the third A-layout area is electrically connected to the input of the fourth A-layout area and has a third-fourth height, and the first-second height is equal to the third-fourth height.

[0010] In addition, the output of the fourth A-layout area is electrically connected to the input of the third B-layout area and has a fourth-third height, the output of the second A-layout area is electrically connected to the input of the first B-layout area and has a second-first height, and the fourth-third height is equal to the second-first height.

[0011] In addition, the output of the third A-layout area is electrically connected to the input of the second B-layout area and has a first-three-two length, the output of the first A-layout area is electrically connected to the input of the fourth B-layout area and has a second-one-four length, and the first-three-two length is equal to the second-one-four length.

[0012] In addition, the output of the second B-layout area is electrically connected to the input of the second A-layout area and has a first-two-two length; the output of the third B-layout area is electrically connected to the input of the third A-layout area and has a first-three-three length; the output of the first B-layout area is electrically connected to the input of the first A-layout area and has a second-one-one length; the output of the fourth B-layout area is electrically connected to the input of the fourth A-layout area and has a second-four-four length; the first-two-two length, the first-three-three length, the second-one-one length, and the second-four-four length are all equal.

[0013] In addition, the third row of layout areas is arranged side by side in sequence by the third B-layout area, the third A-layout area, the fourth B-layout area, and the fourth A-layout area; the fourth row of layout areas is arranged side by side in sequence by the second A-layout area, the second B-layout area, the first A-layout area, and the first B-layout area.

[0014] In addition, the output of the second A layout region in the first row layout region is electrically connected to the input of the third A layout region in the first row layout region and has a second-three length; the output of the fourth A layout region in the second row layout region is electrically connected to the input of the first A layout region in the second row layout region and has a fourth-one length; the output of the third A layout region in the third row layout region is electrically connected to the input of the fourth A layout region in the third row layout region and has a third-four length; the output of the first A layout region in the fourth row layout region is electrically connected to the input of the second A layout region in the fourth row layout region and has a first-two length; wherein, the second-three length, the fourth-one length, the third-four length, and the first-two length are all equal.

[0015] In addition, the output of the third A layout region in the first row layout region is electrically connected to the input of the fourth A layout region in the second row layout region and has a third-four height; the output of the first A layout region in the second row layout region is electrically connected to the input of the second A layout region in the first row layout region and has a first-two height; the output of the fourth A layout region in the third row layout region is electrically connected to the input of the first A layout region in the fourth row layout region and has a fourth-one height; the output of the second A layout region in the fourth row layout region is electrically connected to the input of the third A layout region in the third row layout region and has a second-three height; wherein, the third-four height, the first-two height, the fourth-one height, and the second-three height are all equal.

[0016] In addition, the output of the second B layout region of the first row layout region is electrically connected to the input of the second A layout region of the first row layout region and has a first 22 length; the output of the third B layout region of the first row layout region is electrically connected to the input of the third A layout region of the first row layout region and has a first 33 length; the output of the first B layout region of the second row layout region is electrically connected to the input of the first A layout region of the second row layout region and has a second 11 length; the output of the fourth B layout region of the second row layout region is electrically connected to the input of the fourth A layout region of the second row layout region and has a second 44 length; the output of the third B layout region of the third row layout region is electrically connected to the input of the third A layout region of the third row layout region and has a third 33 length; the output of the fourth B layout region of the third row layout region is electrically connected to the input of the fourth A layout region of the third row layout region and has a third 44 length; the output of the second B layout region of the fourth row layout region is electrically connected to the input of the second A layout region of the fourth row layout region and has a fourth 22 length; the output of the first B layout region of the fourth row layout region is electrically connected to the input of the first A layout region of the fourth row layout region and has a fourth 11 length; wherein, the first 22 length, the first 33 length, the second 11 length, the second 44 length, the third 33 length, the third 44 length, the fourth 22 length, and the fourth 11 length are all equal.

[0017] In addition, the output of the third A layout region of the first row layout region is electrically connected to the input of the second B layout region of the first row layout region and has a first 32 length; the output of the first A layout region of the second row layout region is electrically connected to the input of the fourth B layout region of the second row layout region and has a second 14 length; the output of the fourth A layout region of the third row layout region is electrically connected to the input of the third B layout region of the third row layout region and has a third 43 length; the output of the second A layout region of the fourth row layout region is electrically connected to the input of the first B layout region of the fourth row layout region and has a fourth 21 length; wherein, the first 32 length, the second 14 length, the third 43 length, and the fourth 21 length are all equal.

[0018] Compared with the prior art, the technical solutions provided by the embodiments of the present invention have the following advantages:

[0019] The embodiments of the present invention provide an oscillator layout with superior structural performance. Considering the requirements of symmetry, matching, and minimum parasitic parameters in the layout of the A layout region, the B layout region, and the traces, the oscillator layout can meet the requirements of high frequency and high symmetry in oscillator design, thereby further improving the oscillator performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplary illustrations do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, unless otherwise stated, the drawings in the figures do not constitute a scale limitation.

[0021] Figure 1 Schematic diagram of an oscillator corresponding to the oscillator layout provided by an embodiment of the present invention;

[0022] Figure 2 Schematic diagram of the circuit structure of an oscillator corresponding to the oscillator layout provided by an embodiment of the present invention;

[0023] Figure 3 Layout schematic diagram of the oscillator layout provided by an embodiment of the present invention;

[0024] Figure 4 Schematic diagram of area A layout and area B layout;

[0025] Figures 5 to 8 Routing schematic diagram of the oscillator layout provided by an embodiment of the present invention;

[0026] Figure 9 Schematic diagram of an oscillator corresponding to the oscillator layout provided by another embodiment of the present invention;

[0027] Figure 10 Layout schematic diagram of the oscillator layout provided by another embodiment of the present invention;

[0028] Figures 11 to 14 Routing schematic diagram of the oscillator layout provided by another embodiment of the present invention. Detailed implementation manners

[0029] In the layout design of an oscillator, different placement positions in the layout result in different connection methods, which cause different parasitic parameters, thus affecting the characteristics of the oscillator. Especially for high-speed oscillators, even a small difference can have a significant impact.

[0030] In addition, the current oscillator layouts all include multi-layer metal interconnections. Different routing directions and lengths of different layers of metal will also cause different parasitic parameters of the oscillator, affecting the electrical characteristics of the oscillator.

[0031] To solve the above problems, an embodiment of the present invention provides an oscillator layout with optimized layout to improve the problems caused by different parasitic parameters.

[0032] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will elaborate on each embodiment of the present invention with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in the embodiments of the present invention, many technical details are provided to help readers better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0033] Figure 1 The schematic diagram of the oscillator corresponding to the oscillator layout provided by an embodiment of the present invention Figure 2 The circuit structure diagram of the oscillator corresponding to the oscillator layout provided by an embodiment of the present invention Figure 3 The layout diagram of the oscillator layout provided by an embodiment of the present invention.

[0034] With reference to Figures 1 to 3 , in this embodiment, the oscillator layout includes: an A layout area, which includes a first A layout area 1A, a second A layout area 2A, a third A layout area 3A, and a fourth A layout area 4A; a B layout area, which includes a first B layout area 1B, a second B layout area 2B, a third B layout area 3B, and a fourth B layout area 4B, and both the A layout area and the B layout area are the layouts of inverters; a first row layout area 10, which is arranged in parallel in sequence by the second B layout area 2B, the second A layout area 2A, the third B layout area 3B, and the third A layout area 3A; a second row layout area 20, which is arranged in parallel in sequence by the first A layout area 1A, the first B layout area 1B, the fourth A layout area 4A, and the fourth B layout area 4B; wherein, the inputs and outputs of the first A layout area 1A, the second A layout area 2A, the third A layout area 3A, and the fourth A layout area 4A form a first ring topology, the inputs and outputs of the first B layout area 1B and the third B layout area 3B form a second ring topology, the inputs and outputs of the second B layout area 2B and the fourth B layout area 4B form a third ring topology, and both the second ring topology and the third ring topology are electrically connected to the first ring topology.

[0035] The following will elaborate on the oscillator layout provided by this embodiment with reference to the accompanying drawings.

[0036] The A layout area is the layout of the first inverter, and the B layout area is the layout of the second inverter. The first ring topology, the second ring topology, and the third ring topology form a ring oscillator, and the first ring topology is the outer ring topology, while the second ring topology and the third ring topology are the inner ring topologies.

[0037] As Figure 1 and Figure 2As shown, the oscillator includes a plurality of a unit modules and a plurality of b unit modules. Each a unit module includes at least one first inverter 11, and each b unit module includes at least one second inverter 12. In this embodiment, it is taken as an example that each a unit module includes one first inverter and each b unit module includes one second inverter for illustration.

[0038] Each a unit module corresponds to a corresponding A layout area and is numbered in ascending order from 1 according to natural numbers. The plurality of a unit modules are divided into a first a unit module 1a, a second a unit module 2a, a third a unit module 3a, and a fourth a unit module 4a; each a unit module corresponds to the first A layout area 1A, the second A layout area 2A, the third A layout area 3A, and the fourth A layout area 4A respectively.

[0039] Each b unit module corresponds to a corresponding B layout area and is numbered in ascending order from 1 according to natural numbers. The plurality of b unit modules are divided into a first b unit module 1b, a second b unit module 2b, a third b unit module 3b, and a fourth b unit module 4b; and each b unit module corresponds to the first B layout area 1B, the second B layout area 2B, the third B layout area 3B, and the fourth B layout area 4B respectively.

[0040] Specifically, in this embodiment, the oscillator includes 4 a unit modules and 4 b unit modules; the output of each b unit module is electrically connected to the input of the a unit module with the corresponding number; for example, the output of the first b unit module 1b is electrically connected to the input of the first a unit module 1a, the output of the second b unit module 2b is electrically connected to the input of the second a unit module 2a, the output of the third b unit module 3b is electrically connected to the input of the third a unit module 3a, and the output of the fourth b unit module 4b is electrically connected to the input of the fourth a unit module 4a. In addition, the output of each a unit module is electrically connected to the input of the b unit module with the previous number; for example, the output of the first a unit module 1a is electrically connected to the input of the fourth b unit module 4b, the output of the second a unit module 2a is electrically connected to the input of the first b unit module 1b, the output of the third a unit module 3a is electrically connected to the input of the second b unit module 2b, and the output of the fourth a unit module 4a is electrically connected to the input of the third b unit module 3b. In addition, the output of each a unit module is electrically connected to the input of the a unit module with the next number; for example, the output of the first a unit module 1a is electrically connected to the input of the second a unit module 2a, the output of the second a unit module 2a is electrically connected to the input of the third a unit module 3a, and the output of the fourth a unit module 4a is electrically connected to the input of the first a unit module 1a.

[0041] More specifically, the oscillator has the following four nodes:

[0042] The first and second node net-12 is electrically connected to the output of the first a-unit module 1a, the input of the second a-unit module 2a, the input of the fourth b-unit module 4b, and the output of the second b-unit module 2b.

[0043] The second and third node net-23 is electrically connected to the output of the second a-unit module 2a, the input of the third a-unit module 3a, the input of the first b-unit module 1b, and the output of the third b-unit module 3b.

[0044] The third and fourth node net-34 is electrically connected to the output of the third a-unit module 3a, the input of the fourth a-unit module 4a, the input of the second b-unit module 2b, and the output of the fourth b-unit module 4b.

[0045] The fourth and first node nte-41 is electrically connected to the output of the fourth a-unit module 4a, the input of the first a-unit module 1a, the output of the first b-unit module 1b, and the input of the third b-unit module 3b.

[0046] Continue to refer to Figure 1 、 Figure 2 and Figure 3 The first a-unit module 1a, the first and second node net-12, the second a-unit module 2a, the second and third node net-23, the third a-unit module 3a, the third and fourth node net-34, the fourth a-unit module 4a, and the fourth and first node net-41 form a first ring topology. The first b-unit module 1b, the fourth and first node net-41, the third b-unit module 3b, and the second and third node net-23 form a second ring topology. The second b-unit module 2b, the first and second node net-12, the fourth b-unit module 4b, and the third and fourth node net-34 form a third ring topology.

[0047] In this embodiment, the area of the A layout region is larger than the area of the B layout region. Thus, the signal transmission rate of the first inverter 11 is greater than that of the second inverter 12. Correspondingly, the first ring topology propagates the oscillation signal at a first transmission speed, and the second ring topology and the third ring topology propagate the oscillation signal at a second transmission speed, and the second transmission rate is less than the first transmission speed. Herein, the transmission speed refers to the speed of the oscillation signal from a high level to a low level or from a low level to a high level. The slower the transmission speed, the longer the transmission time, the longer the period of the oscillation signal, and the lower the frequency.

[0048] To further improve the symmetry of the oscillator layout, in this embodiment, the A layout region and the B layout region have the same height, and the length of the A layout region is greater than the length of the B layout region. It can be understood that in other embodiments, it can also be set that the length of the A layout region is the same as the length of the B layout region, and the height of the A layout region is greater than the height of the B layout region.

[0049] It should be noted that in other embodiments, the area of the A layout region may also be the same as the area of the B layout region.

[0050] Figure 4 The left figure in the middle is a schematic diagram of the B layout region, including the input B-in and output B-out of the B layout region; the right figure is a schematic diagram of the A layout region, including the input A-in and output A-out of the A layout region. It should be noted that since the size of the A layout region is relatively large, in order to improve the wiring rationality and further improve the symmetry of the layout, in this embodiment, the A layout region can be provided with 2 inputs A-in, and one input A-in is located at the middle position between the output A-out and the other input A-in.

[0051] Figures 5 to 8 This is the wiring schematic diagram of the oscillator layout in this embodiment.

[0052] As Figure 5 shown, Figure 5 it shows the wiring trajectory of the first and second nodes net-12 in the oscillator layout: the output 1A-out (abbreviation 1AO) of the first A layout region 1A, which is also the output 2B-out (abbreviation 2BO) of the second B layout region 2B, enters the input 2A-in (abbreviation 2AI) of the second A layout region 2A, and at the same time enters the input 4B-in (abbreviation 4BI) of the fourth B layout region 4B. This signal flow path is expressed as 1AO - 2BO → 2AI - 4BI.

[0053] As Figure 6 shown, Figure 6 it shows the wiring trajectory of the second and third nodes net-23 in the oscillator layout: the output (abbreviation 2AO) of the second A layout region 2A-out, which is also the output 3B-out (abbreviation 3BO) of the third B layout region 3B, enters the input 3A-in (abbreviation 3AI) of the third A layout region 3A, and at the same time enters the input 1B-in (abbreviation 1BI) of the first B layout region 1B. This signal flow path is expressed as 2AO - 3BO → 3AI - 1BI.

[0054] As Figure 7 shown, Figure 7 it shows the wiring trajectory of the third and fourth nodes net-34 in the oscillator layout: the output 3A-out (abbreviation 3AO) of the third A layout region 3A, which is also the output 4B-out (abbreviation 4BO) of the fourth B layout region 4B, enters the input 4A-in (abbreviation 4AI) of the fourth A layout region 4A, and at the same time enters the input 2B-in (abbreviation 2BI) of the second B layout region 2B. This signal flow path is expressed as 3AO - 4BO → 4AI - 2BI.

[0055] AsFigure 8 As shown Figure 8 Figure 8 shows the routing track of the fourth-first node net-41 in the oscillator layout: the output 4A-out (abbreviated as 4AO) of the fourth A layout area 4A, which is also the output 1B-out (abbreviated as 1BO) of the first B layout area 1B, enters the input 1A-in (abbreviated as 1AI) of the first A layout area 1A and simultaneously enters the input 3B-in (abbreviated as 3BI) of the third B layout area 3B. This signal flow path is expressed as 4AO-1BO→1AI-3BI.

[0056] In this embodiment, by making a reasonable layout of each A layout area and B layout area, the layout and wiring are reasonable. From the schematic diagram, the lengths of the incoming and outgoing lines of each unit module are the same.

[0057] Referring to Figure 6 , the output 2A-out of the second A layout area 2A is electrically connected to the input 3A-in of the third A layout area 3A with a second-third length L23; referring to Figure 8 , the output 4A-out of the fourth A layout area 4A is electrically connected to the input 1A-in of the first A layout area 1A with a fourth-first length L41, and the second-third length L23 is equal to the fourth-first length L41.

[0058] For the first row layout area 10 and the second row layout area 20, the horizontal routing from the output of the A layout area to the input of another A layout area has the same path, avoiding the difference in parasitic parameters caused by the difference in horizontal routing.

[0059] Referring to Figure 5 , the output 1A-out of the first A layout area 1A is electrically connected to the input 2A-in of the second A layout area 2A with a first-second height H12; referring to Figure 7 , the output 3A-out of the third A layout area 3A is electrically connected to the input 4A-in of the fourth A layout area 4A with a third-fourth height H34, and the first-second height Hl2 is equal to the third-fourth height H34.

[0060] In this way, the vertical routing from the output of each A layout area to the input of another A layout area has the same path, avoiding the difference in parasitic parameters caused by the difference in vertical routing length.

[0061] Referring to Figure 8 , the output 4A-out of the fourth A layout area 4A is electrically connected to the input 3B-in of the third B layout area 3B with a fourth-third height H43; referring to Figure 6 , the output 2A-out of the second A layout area 2A is electrically connected to the input 1B-in of the first B layout area 1B with a second-first height H21, and the fourth-third height H43 is equal to the second-first height H21.

[0062] In this way, the output 2A-out of the second A layout area 2A of the first row layout area 10 to the input 1B-in of the first B layout area 1B of the second row layout area 20 is a vertical routing, and the output 4A-out of the fourth A layout area 4A of the second row layout area 20 to the input 3B-in of the third B layout area 3B of the first row layout area 10 is another vertical routing, and the two vertical routings have the same path, avoiding the difference in parasitic parameters caused by the difference in the length of the vertical routings.

[0063] refer to Figure 7 , the output 3A-out of the third A layout area 3A is electrically connected to the input 2B-in of the second B layout area 2B with a first thirty-second length L132; Figure 5 The output 1A-out of the first A layout area 1A is electrically connected to the input 4B-in of the fourth B layout area 4B and has a second-fourth length L214, and the first-three-second length L132 is equal to the second-fourth length L214.

[0064] In this way, for the first row of layout area 10: the output 3A-out of the third A layout area 3A to the input 2B-in of the second B layout area 2B has a horizontal routing; for the second row of layout area 20: the output 1A-in of the first A layout area 1A to the input 4B-in of the fourth B layout area 4B has another horizontal routing, and the two horizontal routings have the same path length, thereby avoiding the difference in parasitic parameters caused by the difference in horizontal length.

[0065] refer to Figure 5 , the output 2B-out of the second B layout area 2B is electrically connected to the input 2A-in of the second A layout area 2A and has a first-second-second length; Figure 6 , the output 3B-out of the third B layout area 3B is electrically connected to the input 3A-in of the third A layout area 3A and has a first three three length; Figure 7 , the output 1B-out of the first B layout area 1B is electrically connected to the input 1A-in of the first A layout area 1A and has a second length; Figure 8 The output 4B-out of the fourth B layout area 4B is electrically connected to the input 4A-in of the fourth A layout area 4A and has a length of 244; the length of 122, the length of 133, the length of 211 and the length of 244 are all equal.

[0066] The 122nd length, the 133rd length, the 211th length, and the 244th length are all the lengths of the horizontal lines.

[0067] It should be noted that the aforementioned equality does not necessarily mean that they must be completely identical. Equality is also referred to as being within the error range allowed by the circuit in layout design. The error range can be, for example, 1%, 3%, or 5%, but is not limited thereto.

[0068] In the oscillator layout, the horizontal traces can be defined as metal layer 1, and the vertical traces can be positioned as metal layer 2, and the resistivity of metal layer 1 and metal layer 2 is different. In this embodiment, the lengths of the aforementioned horizontal traces are all equal, and the heights of the vertical traces are all equal. Therefore, the adverse effects caused by different resistivities are avoided, so that the parasitic resistances and parasitic capacitances on each pair of symmetric traces are equal or approximately equal.

[0069] In the technical solution of the oscillator layout provided in this embodiment, the requirements of symmetry, matching, and minimum parasitic load are comprehensively considered in the layout and wiring topology diagram, so that the layout can meet the high-frequency and high-symmetry requirements of the circuit design. For example, when the output signal frequency of the oscillator reaches 3.2 GHz or 4.8 GHz or higher frequencies, and the duty cycle of the output signal is close to 50%, the symmetry, parasitic resistance, and parasitic capacitance of the layout all play a crucial role in the performance of the oscillator.

[0070] Another embodiment of the present invention also provides an oscillator layout. The oscillator layout area is substantially the same as that of the previous embodiment. The main differences include that it further includes a third row layout area, which is sequentially arranged side by side with the third B layout area, the third A layout area, the fourth B layout area, and the fourth A layout area; and a fourth row layout area, which is sequentially arranged side by side with the second A layout area, the second B layout area, the first A layout area, and the first B layout area. The oscillator layout provided in another embodiment of the present invention will be described in detail below with reference to the accompanying drawings. For the same or corresponding parts as those in the previous embodiment, reference can be made to the description of the previous embodiment, and details will not be repeated below.

[0071] Figure 9 It is the schematic diagram of the oscillator corresponding to the oscillator layout provided in another embodiment of the present invention. Figure 10 It is the layout schematic diagram of the oscillator layout provided in another embodiment of the present invention.

[0072] Combined with reference to Figure 9 and Figure 10, in this embodiment, the oscillator layout area includes: A layout area, and the A layout area includes a first A layout area 1A, a second A layout area 2A, a third A layout area 3A, and a fourth A layout area 4A; B layout area, and the B layout area includes a first B layout area 1B, a second B layout area 2B, a third B layout area 3B, and a fourth B layout area 4B, and both the A layout area and the B layout area are layouts of inverters; The first row layout area 10 is formed by arranging the second B layout area 2B, the second A layout area 2A, the third B layout area 3B, and the third A layout area 3A side by side in sequence; The second row layout area 20 is formed by arranging the first A layout area 1A, the first B layout area 1B, the fourth A layout area 4A, and the fourth B layout area 4B side by side in sequence; Among them, the inputs and outputs of the first A layout area 1A, the second A layout area 2A, the third A layout area 3A, and the fourth A layout area 4A form a first ring topology structure, the inputs and outputs of the first B layout area 1B and the third B layout area 3B form a second ring topology structure, the inputs and outputs of the second B layout area 2B and the fourth B layout area 4B form a third ring topology structure, and both the second ring topology structure and the third ring topology structure are electrically connected to the first ring topology structure.

[0073] It further includes: The third row layout area 30 is formed by arranging the third B layout area 3B, the third A layout area 3A, the fourth B layout area 4B, and the fourth A layout area 4A side by side in sequence; The fourth row layout area 40 is formed by arranging the second A layout area 2A, the second B layout area 2B, the first A layout area 1A, and the first B layout area 1B side by side in sequence.

[0074] The oscillator layout will be described below with reference to the accompanying drawings.

[0075] As Figure 9 shown, each a unit module corresponds to the corresponding A layout area, and is numbered in positive order from 1 according to natural numbers. A plurality of a unit modules are divided into a first a unit module 2*1a, a second a unit module 2*2a, a third a unit module 2*3a, and a fourth a unit module 2*4a; And the first a unit module 2*1a corresponds to two first A layout areas 1A, the second a unit module 2*2a corresponds to two second A layout areas 2A, the third a unit module 2*3a corresponds to two third A layout areas 3A, and the fourth a unit module 2*4a corresponds to two fourth A layout areas 4A.

[0076] Each b unit module corresponds to a corresponding B layout area, and is numbered in ascending order from 1 according to natural numbers. A plurality of b unit modules are divided into a first b unit module, a second b unit module, a third b unit module, and a fourth b unit module. Moreover, the first b unit module 2*1b corresponds to two first B layout areas 1B, the second b unit module 2*2b corresponds to two second B layout areas 2B, the third b unit module 2*3b corresponds to two third B layout areas 3B, and the fourth b unit module 2*4b corresponds to two fourth B layout areas 4B.

[0077] The A layout area defines a first inverter, and the B layout area defines a second inverter. The oscillator includes a plurality of a unit modules and a plurality of b unit modules. Each a unit module includes two first inverters 11 connected in parallel, and each b unit module includes two second inverters 12 connected in parallel. For each a unit module, the inputs of the two first inverters 11 are connected, and the outputs of the two first inverters 11 are connected. For each b unit module, the inputs of the two second inverters 12 are connected, and the outputs of the two second inverters 12 are connected.

[0078] In this way, it is beneficial to control the wire connection lengths between the layout areas in the oscillator layout design to be similar or equal, so that the oscillator layout has good symmetry and balance, so that each key node of the oscillator in the layout has a high load matching degree, and further the delay of each stage of the inverter is equal. In addition, it is also beneficial to make the wire connection lengths between the layout areas shorter, thereby reducing the parasitic resistance and parasitic capacitance of the wire connections, so that the oscillator has good performance.

[0079] The oscillator has a first-second node net-12, a second-third node net-23, a third-fourth node net-34, and a fourth-first node nte-41. For a detailed description of these four nodes, reference can be made to the foregoing embodiments.

[0080] In this embodiment, the area of the A layout area is larger than the area of the B layout area. Further, the A layout area and the B layout area have the same height, and the length of the A layout area is greater than the length of the B layout area.

[0081] Figures 11 to 14 It is a wiring schematic diagram of the oscillator layout.

[0082] Reference Figure 12 , the output 2A-out of the second A layout area 2A in the first row of layout areas 10 is electrically connected to the input 3A-in of the third A layout area 3A in the first row of layout areas 10, having a second-third length L23; reference Figure 14 , the output 4A-out of the fourth A layout area 4A in the second row of layout areas 20 is electrically connected to the input 1A-in of the first A layout area 1A in the second row of layout areas 20, having a fourth-first length L41; reference Figure 13, the output 3A-out of the third A layout area 3A in the third row layout area 30 is electrically connected to the input 4A-in of the fourth A layout area 4A in the third row layout area 30, having a third-fourth length L34; reference Figure 11 , the output 1A-out of the first A layout area 1A in the fourth row layout area 40 is electrically connected to the input 2A-in of the second A layout area 2A in the fourth row layout area 40, having a first-second length L12; wherein, the second-third length L23, the fourth-first length L41, the third-fourth length L34, and the first-second length L12 are all equal.

[0083] reference Figure 13 , the output 3A-out of the third A layout area 3A in the first row layout area 10 is electrically connected to the input 4A-in of the fourth A layout area 4A in the second row layout area 20, having a third-fourth height H34; reference Figure 11 , the output 1A-out of the first A layout area 1A in the second row layout area 20 is electrically connected to the input 2A-in of the second A layout area 2A in the first row layout area 10, having a first-second height H12; reference Figure 14 , the output 4A-out of the fourth A layout area 4A in the third row layout area 30 is electrically connected to the input 1A-in of the first A layout area 1A in the fourth row layout area 40, having a fourth-first height H41; reference Figure 12 , the output 2A-out of the second A layout area 2A in the fourth row layout area 40 is electrically connected to the input 3A-in of the third A layout area 3A in the third row layout area, having a second-third height H23; wherein, the third-fourth height H34, the first-second height H12, the fourth-first height H41, and the second-third height H23 are all equal.

[0084] reference Figures 11 to 14, the output 2B-out of the second B layout region 2B in the first row layout region 10 is electrically connected to the input 2A-in of the second A layout region 2A in the first row layout region 10 and has a first 122 length; the output 3B-out of the third B layout region 3B in the first row layout region 10 is electrically connected to the input 3A-in of the third A layout region 3A in the first row layout region 10 and has a first 133 length; the output 1B-out of the first B layout region 1B in the second row layout region 20 is electrically connected to the input 1A-in of the first A layout region 1A in the second row layout region 20 and has a second 211 length; the output 4B-out of the fourth B layout region 4B in the second row layout region 20 is electrically connected to the input 4A-in of the fourth A layout region 4A in the second row layout region 20 and has a second 244 length; the output 3B-out of the third B layout region 3B in the third row layout region 30 is electrically connected to the input 3A-in of the third A layout region 3A in the third row layout region 30 and has a third 333 length; the output of the fourth B layout region 4B in the third row layout region 30 is electrically connected to the input 4A-in of the fourth A layout region 4A in the third row layout region 30 and has a third 344 length; the output 2B-out of the second B layout region 2B in the fourth row layout region 40 is electrically connected to the input 2A-in of the second A layout region 2A in the fourth row layout region 40 and has a fourth 422 length; the output 1B-out of the first B layout region 1B in the fourth row layout region 40 is electrically connected to the input 1A-in of the first A layout region 1A in the fourth row layout region 40 and has a fourth 411 length; wherein, the first 122 length, the first 133 length, the second 211 length, the second 244 length, the third 333 length, the third 344 length, the fourth 422 length, and the fourth 411 length are all equal.

[0085] Continue to refer to Figures 11 to 14 , the output 3A-out of the third A layout region 3A in the first row layout region 10 is electrically connected to the input 2B-in of the second B layout region 2B in the first row layout region 10 and has a first 132 length; the output 1A-out of the first A layout region 1A in the second row layout region 20 is electrically connected to the input 4B-in of the fourth B layout region 4B in the second row layout region 20 and has a second 214 length; the output 4A-out of the fourth A layout region 4A in the third row layout region 30 is electrically connected to the input 3B-in of the third B layout region 3B in the third row layout region 30 and has a third 343 length; the output 2A-out of the second A layout region 2A in the fourth row layout region 40 is electrically connected to the input 1B-in of the first B layout region 1B in the fourth row layout region 40 and has a fourth 421 length; wherein, the first 132 length, the second 214 length, the third 343 length, and the fourth 421 length are all equal.

[0086] Continue to refer to Figures 11 to 14 , for the output of the A layout region and the input of another A layout region:

[0087] In the third row layout area 30 and the fourth row layout area 40, the output 1A-out of the first A layout area 1A is electrically connected to the input 2A-in of the second A layout area 2A, and the output 3A-out of the third A layout area 3A is electrically connected to the input 4A-in of the fourth A layout area 4A, both of which are horizontal traces. The output 2A-out of the second A layout area 2A is electrically connected to the input 3A-in of the third A layout area 3A, and the output 4A-out of the fourth A layout area 4A is electrically connected to the input 1A-in of the first A layout area 1A, both of which are vertical traces. While in the first row layout area 10 and the second row layout area 20, it is exactly the opposite. In the first row layout area 10 and the second row layout area 20, the output 1A-out of the first A layout area 1A is electrically connected to the input 2A-in of the second A layout area 2A, and the output 3A-out of the third A layout area 3A is electrically connected to the input 4A-in of the fourth A layout area 4A, both of which are vertical traces. The output 2A-out of the second A layout area 2A is electrically connected to the input 3A-in of the third A layout area 4A, and the output 4A-out of the fourth A layout area 4A is electrically connected to the input 1A-in of the first A layout area 1A, both of which are horizontal traces.

[0088] In this way, for the output of each A layout area to the input of another A layout area, there is a horizontal trace with the same path and a vertical trace with the same path.

[0089] Continue to refer to Figures 11 to 14 , for the output of an A layout area to the input of another B layout area:

[0090] In the third row layout area 30 and the fourth row layout area 40, the output 4A-out of the fourth A layout area 4A is electrically connected to the input 3B-in of the third B layout area 3B, and the output 2A-out of the second A layout area 2A is electrically connected to the input of the first B layout area 1B, both of which are horizontal traces. The output 3A-out of the third A layout area 3A is electrically connected to the input 2B-in of the second B layout area 2B, and the output 1A-out of the first A layout area 1A is electrically connected to the input 4B-in of the fourth B layout area 4B, both of which are vertical traces. While in the first row layout area 10 and the second row layout area 20, it is exactly the opposite. In the first row layout area 10 and the second row layout area 20, the output 4A-out of the fourth A layout area 4A is electrically connected to the input 3B-in of the third B layout area 3B, and the output 2A-out of the second A layout area 2A is electrically connected to the input 1B-in of the first B layout area 1B, both of which are vertical traces. The output 3A-out of the third A layout area 3A is electrically connected to the input 2B-in of the second B layout area 2B, and the output 1A-out of the first A layout area 1A is electrically connected to the input 4B-in of the fourth B layout area 4B, both of which are horizontal traces.

[0091] In this way, for each output of the A-layout area to the input of the corresponding B-layout area, there is a horizontal trace with the same path and a vertical trace with the same path.

[0092] In addition, each B-layout area and the A-layout area are adjacent to ensure that the paths from the output of each B-layout area to the input of the corresponding A-layout area are consistent. The first row of layout areas 10 and the second row of layout areas 20 form the upper half, and the third row of layout areas 30 and the fourth row of layout areas 40 form the lower half. The upper half and the lower half are connected by vertical traces.

[0093] The setting of the third row of layout areas 30 and the fourth row of layout areas 40 can further consider the requirements of symmetry, matching, and minimum parasitic parameters in the layout of A-layout areas and B-layout areas and the routing, so that the oscillator layout can meet the requirements of high frequency and high symmetry in oscillator design. For example, the oscillator can generate a clock signal with a frequency of 3.2 GHz or 4.8 GHz or higher and a duty cycle close to 50% or even equal to 50%.

[0094] Specifically, in the layout stage, considering the requirements of improving symmetry and reducing parasitic parameters, multiple A-layout areas and multiple B-layout areas are arranged in four rows, that is, 16 layout areas (including 8 A-layout areas and 8 B-layout areas) are arranged horizontally in 4 tiers with a tier stepping structure, namely the first row of layout areas 10, the second row of layout areas 20, the third row of layout areas 30, and the fourth row of layout areas 40, so as to achieve the optimal symmetry of the layout. More specifically, as Figure 10 shown. In the wiring stage, considering the positions of the 16 layout areas, the traces from the output of each layout area to the input of another layout area are reasonably routed to optimize the matching of the lengths of the traces. The above-mentioned second-third length L23, fourth-first length L41, third-fourth length L34, first-second length L12, third-fourth height H34, first-second height H12, fourth-first height H41, second-third height H23, first-second-second length, first-third-third length, second-first-first length, second-fourth-fourth length, third-third-third length, third-fourth-fourth length, fourth-second-second length, fourth-first-first length, etc. all represent the lengths of the traces. More specifically, as Figures 11 to 14 shown.

[0095] Those of ordinary skill in the art can understand that the above embodiments are specific examples for implementing the present invention. In practical applications, various changes can be made in form and details without departing from the spirit and scope of the present invention. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the scope of the claims.

Claims

1. An oscillator layout, characterized in that, Including: The layout area of die A, where the layout area of die A includes the first layout area of die A, the second layout area of die A, the third layout area of die A, and the fourth layout area of die A; The layout area of die B, where the layout area of die B includes the first layout area of die B, the second layout area of die B, the third layout area of die B, and the fourth layout area of die B, and both the layout area of die A and the layout area of die B are the layouts of inverters; The first row layout area, where the second layout area of die B, the second layout area of die A, the third layout area of die B, and the third layout area of die A are arranged side by side in sequence; The second row layout area, where the first layout area of die A, the first layout area of die B, the fourth layout area of die A, and the fourth layout area of die B are arranged side by side in sequence; Among them, the inputs and outputs of the first layout area of die A, the second layout area of die A, the third layout area of die A, and the fourth layout area of die A form a first ring topology structure, the inputs and outputs of the first layout area of die B and the third layout area of die B form a second ring topology structure, the inputs and outputs of the second layout area of die B and the fourth layout area of die B form a third ring topology structure, and both the second ring topology structure and the third ring topology structure are electrically connected to the first ring topology structure; The first layout area of die A, the second layout area of die A, the third layout area of die A, the fourth layout area of die A, the first layout area of die B, the second layout area of die B, the third layout area of die B, and the fourth layout area of die B have the same height; the lengths of the first layout area of die A, the second layout area of die A, the third layout area of die A, and the fourth layout area of die A are greater than the lengths of the first layout area of die B, the second layout area of die B, the third layout area of die B, and the fourth layout area of die B; The output of the second layout area of die A is electrically connected to the input of the third layout area of die A with a second-three length, the output of the fourth layout area of die A is electrically connected to the input of the first layout area of die A with a fourth-one length, and the second-three length is equal to the fourth-one length; The output of the first layout area of die A is electrically connected to the input of the second layout area of die A with a first-two height, the output of the third layout area of die A is electrically connected to the input of the fourth layout area of die A with a third-four height, and the first-two height is equal to the third-four height.

2. The oscillator layout according to claim 1, characterized in that The total area of the layout area of die A is greater than the total area of the layout area of die B.

3. The oscillator layout according to claim 1, characterized in that, The output of the fourth layout area of die A is electrically connected to the input of the third layout area of die B with a fourth-three height, the output of the second layout area of die A is electrically connected to the input of the first layout area of die B with a second-one height, and the fourth-three height is equal to the second-one height.

4. The oscillator layout according to claim 1, characterized in that, The output of the third layout area of die A is electrically connected to the input of the second layout area of die B with a first-three-two length, the output of the first layout area of die A is electrically connected to the input of the fourth layout area of die B with a second-one-four length, and the first-three-two length is equal to the second-one-four length.

5. The oscillator layout according to claim 1, wherein The output of the second B layout region is electrically connected to the input of the second A layout region with a first 122 length; the output of the third B layout region is electrically connected to the input of the third A layout region with a first 133 length; the output of the first B layout region is electrically connected to the input of the first A layout region with a second 11 length; the output of the fourth B layout region is electrically connected to the input of the fourth A layout region with a second 44 length; the first 122 length, the first 133 length, the second 11 length, and the second 44 length are all equal.

6. The oscillator layout according to claim 1, characterized in that It further includes: The third row of layout regions, where the third B layout region, the third A layout region, the fourth B layout region, and the fourth A layout region are arranged side by side in sequence; The fourth row of layout regions, where the second A layout region, the second B layout region, the first A layout region, and the first B layout region are arranged side by side in sequence.

7. The oscillator layout according to claim 6, wherein The output of the second A layout region in the first row of layout regions is electrically connected to the input of the third A layout region in the first row of layout regions with a second 3 length; The output of the fourth A layout region in the second row of layout regions is electrically connected to the input of the first A layout region in the second row of layout regions with a fourth 1 length; The output of the third A layout region in the third row of layout regions is electrically connected to the input of the fourth A layout region in the third row of layout regions with a third 4 length; The output of the first A layout region in the fourth row of layout regions is electrically connected to the input of the second A layout region in the fourth row of layout regions with a first 2 length; wherein, the second 3 length, the fourth 1 length, the third 4 length, and the first 2 length are all equal.

8. The oscillator layout according to claim 6, wherein The output of the third A layout region in the first row of layout regions is electrically connected to the input of the fourth A layout region in the second row of layout regions with a third 4 height; The output of the first A layout region in the second row of layout regions is electrically connected to the input of the second A layout region in the first row of layout regions with a first 2 height; The output of the fourth A layout region in the third row of layout regions is electrically connected to the input of the first A layout region in the fourth row of layout regions with a fourth 1 height; The output of the second A layout region in the fourth row of layout regions is electrically connected to the input of the third A layout region in the third row of layout regions with a second 3 height; wherein, the third 4 height, the first 2 height, the fourth 1 height, and the second 3 height are all equal.

9. The oscillator layout according to claim 6, wherein The output of the second B layout region in the first row of layout regions is electrically connected to the input of the second A layout region in the first row of layout regions with a first 122 length; The output of the third B layout region in the first row of layout regions is electrically connected to the input of the third A layout region in the first row of layout regions with a first 133 length; The output of the first B layout area in the second row layout area is electrically connected to the input of the first A layout area in the second row layout area and has a second one-one length; The output of the fourth B layout area in the second row layout area is electrically connected to the input of the fourth A layout area in the second row layout area and has a second four-four length; The output of the third B layout area in the third row layout area is electrically connected to the input of the third A layout area in the third row layout area and has a third three-three length; The output of the fourth B layout area in the third row layout area is electrically connected to the input of the fourth A layout area in the third row layout area and has a third four-four length; The output of the second B layout area in the fourth row layout area is electrically connected to the input of the second A layout area in the fourth row layout area and has a fourth two-two length; The output of the first B layout area in the fourth row layout area is electrically connected to the input of the first A layout area in the fourth row layout area and has a fourth one-one length; Wherein, the first two-two length, the first three-three length, the second one-one length, the second four-four length, the third three-three length, the third four-four length, the fourth two-two length, and the fourth one-one length are all equal.

10. The oscillator layout according to claim 6, wherein, The output of the third A layout area in the first row layout area is electrically connected to the input of the second B layout area in the first row layout area and has a first three-two length; The output of the first A layout area in the second row layout area is electrically connected to the input of the fourth B layout area in the second row layout area and has a second one-four length; The output of the fourth A layout area in the third row layout area is electrically connected to the input of the third B layout area in the third row layout area and has a third four-three length; The output of the second A layout area in the fourth row layout area is electrically connected to the input of the first B layout area in the fourth row layout area and has a fourth two-one length; Wherein, the first three-two length, the second one-four length, the third four-three length, and the fourth two-one length are all equal.

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