Epitaxial wafer manufacturing method for reducing internal stress of power devices and epitaxial wafer

Abstract

The present invention relates to the field of semiconductor device manufacturing technology, and more specifically to a method for fabricating an epitaxial wafer for reducing the internal stress of a power device, and an epitaxial wafer. The method comprises: forming a substrate, the substrate being made of a first material; etching a plurality of first grooves on the surface of the substrate; forming a buffer layer above the substrate, the buffer layer being made of a second material; etching a plurality of second grooves on the surface of the buffer layer; and forming an epitaxial layer on the surface of the buffer layer to form an epitaxial wafer. The present invention has the beneficial effect of avoiding the problem of insufficient stress release in the substrate and epitaxial layer in the prior art by providing the buffer layer, and further releasing the internal stress of the device by providing the first and second grooves, thereby improving the device yield.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device manufacturing, and in particular to an epitaxial wafer manufacturing method and an epitaxial wafer for reducing internal stress of a power device. Background Art

[0002] The substrate refers to a wafer made from semiconductor single crystal materials, such as single crystal silicon, which is usually used as a base to support the active devices above in semiconductor devices. Usually, the method of making a substrate is mainly to slice, grind and polish the single crystal material. The epitaxial layer refers to the structure formed above the substrate based on the epitaxial process. It is usually a new single crystal layer grown on the processed single crystal substrate to improve the electrical properties of the overall structure. Generally speaking, by preparing the epitaxial layer, the requirements of high breakdown voltage, small series resistance and small saturation voltage drop in the collector region can be achieved. Therefore, the production process of the epitaxial layer plays an extremely important role in the manufacture of semiconductor devices.

[0003] In the prior art, there are related processes for forming single-crystalline epitaxial layers on substrates. However, in actual implementation, the inventors discovered that heteroepitaxial growth is often necessary to achieve good electrical performance. Due to the lattice mismatch between the heteroepitaxial layer and the substrate, high stress exists between the substrate and the epitaxial layer. This leads to low device yield and lifespan. Summary of the Invention

[0004] In view of the above problems existing in the prior art, a method for manufacturing an epitaxial wafer and an epitaxial wafer for reducing the internal stress of a power device are provided.

[0005] The specific technical solutions are as follows:

[0006] A method for manufacturing an epitaxial wafer for reducing internal stress of a power device, comprising:

[0007] forming a substrate made of a first material;

[0008] Etching a plurality of first trenches on the surface of the substrate;

[0009] forming a buffer layer on the substrate, wherein the buffer layer is made of a second material;

[0010] Etching a plurality of second trenches on the surface of the buffer layer;

[0011] forming an epitaxial layer on the surface of the buffer layer to form an epitaxial wafer;

[0012] The epitaxial layer is made of a third material.

[0013] Preferably, the first groove and the second groove are staggered with each other in a vertical direction.

[0014] Preferably, the first trench and the second trench are both formed by wet etching;

[0015] The wet etching method specifically includes:

[0016] Coating a photoresist on a portion of the surface of the device to expose a predetermined trench formation area;

[0017] wet etching the device to form a trench;

[0018] The photoresist is removed and the device is cleaned.

[0019] Preferably, the first material is silicon, sapphire, or aluminum gallium nitride.

[0020] Preferably, the second material is gallium nitride or aluminum nitride.

[0021] Preferably, the third material is gallium nitride or sapphire.

[0022] Preferably, a planarization process is further included after the epitaxial layer is formed, and the planarization process includes:

[0023] Obtaining the current thickness, highest point, and lowest point of the epitaxial layer;

[0024] generating a flat thickness according to the highest point, the lowest point, and a preset lower thickness limit;

[0025] The epitaxial layer is polished according to the flat thickness to complete the planarization process.

[0026] Preferably, the thickness of the buffer layer is between 3 nm and 10 nm.

[0027] An epitaxial wafer comprises a substrate, a buffer layer and an epitaxial layer are sequentially arranged on the substrate;

[0028] The upper surface of the substrate has a plurality of first grooves;

[0029] The upper surface of the buffer layer has a plurality of second grooves;

[0030] The epitaxial wafer is formed according to the above-mentioned epitaxial wafer manufacturing method.

[0031] The above technical solution has the following advantages or beneficial effects: by setting a buffer layer, the problem of insufficient stress release of the substrate and epitaxial layer in the prior art is avoided, and by setting the first groove and the second groove, the internal stress of the device is further released, thereby improving the yield of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The embodiments of the present invention will be described more fully with reference to the accompanying drawings, which are provided for illustration and description only and are not intended to limit the scope of the present invention.

[0033] Figure 1 is an overall schematic diagram of an embodiment of the present invention;

[0034] Figure 2 Schematic diagram of the substrate and the first trench in an embodiment of the present invention;

[0035] Figure 3 Schematic diagram of a buffer layer in an embodiment of the present invention;

[0036] Figure 4 Schematic diagram of the epitaxial layer in an embodiment of the present invention;

[0037] Figure 5 Schematic diagram of a wet etching method according to an embodiment of the present invention;

[0038] Figure 6 A schematic diagram of a planarization process according to an embodiment of the present invention;

[0039] Figure 7 Schematic diagram of an epitaxial wafer in an embodiment of the present invention. DETAILED DESCRIPTION

[0040] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0041] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0042] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0043] The present invention comprises:

[0044] A method for producing an epitaxial wafer for reducing internal stress of a power device, such as Figure 1 Shown, including:

[0045] forming a substrate 1 made of a first material;

[0046] Etching a plurality of first trenches 11 on the surface of the substrate 1;

[0047] A buffer layer 2 is formed on the substrate 1, wherein the buffer layer 2 is made of a second material;

[0048] Etching a plurality of second trenches 21 on the surface of the buffer layer 2;

[0049] forming an epitaxial layer 3 on the surface of the buffer layer 2 to form an epitaxial wafer;

[0050] The epitaxial layer 3 is made of a third material.

[0051] Specifically, in response to the problem in the prior art that the stress between the heteroepitaxial layer 3 and the substrate 1 is large, resulting in a reduced device life, the present invention achieves better compatibility between the substrate 1 and the epitaxial layer 3 by setting a buffer layer 2, and further increases the contact area between the buffer layer 2 and the substrate 1, and between the buffer layer 2 and the epitaxial layer 3 by setting a first groove 11 and a second groove 21, which facilitates the release of device stress and effectively extends the device life.

[0052] In the actual implementation process, Figure 2 As shown, a first groove 11 marked by grid lines is etched on the prepared substrate 1. Figure 3 As shown, a buffer layer 2 is deposited on the substrate 1, and a portion of the buffer layer 2 extends into the first trench 11. Subsequently, second trenches 21 arranged alternately with the first trenches 11 are etched on the buffer layer 2. Finally, as shown in FIG. Figure 4 As shown, an epitaxial layer 3 is deposited on the buffer layer 2, and a portion of the epitaxial layer 3 is filled in the second trench 21.

[0053] In a preferred embodiment, the first groove 11 and the second groove 21 are staggered with each other in the vertical direction.

[0054] Specifically, in order to address the problem in the prior art that the stress between the epitaxial layer 3 and the substrate 1 cannot be effectively released, in this embodiment, by setting staggered first grooves 11 and second grooves 21, the contact area between the buffer layer 2 and the substrate 1, and between the buffer layer 2 and the epitaxial layer 3 is increased, thereby achieving effective stress release and extending the device life.

[0055] In a preferred embodiment, the first trench 11 and the second trench 21 are both formed by wet etching;

[0056] like Figure 5 As shown, the wet etching method specifically includes:

[0057] Coating a photoresist on a portion of the surface of the device to expose a predetermined trench formation area;

[0058] wet etching the device to form trenches;

[0059] Remove the photoresist and clean the device.

[0060] Specifically, in view of the problem in the prior art that the use of ion etching in the groove formation process can cause device damage and thus reduce the device life, this embodiment uses a wet etching method to achieve better groove sidewall flatness, avoiding the damage caused by ion etching that causes the device to deform and be damaged under stress.

[0061] During implementation, the wet etching process utilizes high-temperature phosphoric acid and sulfuric acid mixed with hydrogen peroxide for two consecutive etching steps to achieve optimal etching results. The etching temperature for the high-temperature phosphoric acid is between 170°C and 220°C, while the etching temperature for the sulfuric acid mixed with hydrogen peroxide is between 100°C and 200°C to achieve optimal etching results. The trench depth can be adjusted by appropriately increasing or decreasing the etching temperature.

[0062] In a preferred embodiment, the first material is silicon, sapphire, or aluminum gallium nitride.

[0063] In a preferred embodiment, the second material is gallium nitride or aluminum nitride.

[0064] In a preferred embodiment, the third material is gallium nitride or sapphire.

[0065] During implementation, the first material, the second material and the third material can be arbitrarily combined to adjust the electrical performance of the device.

[0066] In a preferred embodiment, a planarization process is further included after the epitaxial layer 3 is formed, such as Figure 6 As shown, the planarization process includes:

[0067] Obtain the current thickness, highest point, and lowest point of the epitaxial layer 3;

[0068] Generate a flat thickness according to the highest point, the lowest point and a preset lower thickness limit;

[0069] The epitaxial layer 3 is polished according to the flat thickness to complete the planarization process.

[0070] Specifically, in order to avoid problems such as large parasitic capacitance and insufficient stress release caused by the uneven surface of the epitaxial layer 3 during the subsequent active area formation process, in this embodiment, a flattening process is set up to further process the epitaxial layer 3, so that the epitaxial wafer can meet the requirements of related high-frequency devices, thereby improving the overall yield of the device.

[0071] In a preferred embodiment, the thickness of the buffer layer 2 is between 5 nm and 10 nm.

[0072] Specifically, by providing a buffer layer 2 with a relatively low thickness, it is possible to achieve lower stress in the entire device, thereby avoiding the problem of shortened device life due to insufficient stress release.

[0073] An epitaxial wafer comprises a substrate A1, a buffer layer A2 and an epitaxial layer A3 are sequentially arranged on the substrate;

[0074] The upper surface of the substrate A1 has a plurality of first grooves A11;

[0075] The upper surface of the buffer layer A2 has a plurality of second grooves A21;

[0076] The epitaxial wafer is formed according to the above-mentioned epitaxial wafer manufacturing method.

[0077] Specifically, in response to the problem in the prior art that the stress between the heteroepitaxial layer A3 and the substrate A1 is large, resulting in a reduced device life, the present invention achieves better compatibility between the substrate A1 and the epitaxial layer A3 by setting a buffer layer A2, and further increases the contact area between the buffer layer A2 and the substrate A1, and between the buffer layer A2 and the epitaxial layer A3 by setting a first groove A11 and a second groove A21, which facilitates the release of device stress and effectively extends the device life.

[0078] The beneficial effects of the present invention are as follows: by providing a buffer layer, the problem of insufficient stress release of the substrate and the epitaxial layer in the prior art is avoided, and by providing the first trench and the second trench, the internal stress of the device is further released, thereby improving the yield of the device.

[0079] The above are only preferred embodiments of the present invention and do not limit the implementation mode and protection scope of the present invention. For those skilled in the art, it should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the description and illustrations of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for producing an epitaxial wafer for reducing internal stress of a power device, characterized in that: include: forming a substrate made of a first material; Etching a plurality of first trenches on the surface of the substrate; forming a buffer layer on the substrate, wherein the buffer layer is made of a second material; Etching a plurality of second trenches on the surface of the buffer layer; forming an epitaxial layer on the surface of the buffer layer to form an epitaxial wafer; The epitaxial layer is made of a third material; The first trench and the second trench are both formed by a wet etching method; The wet etching method specifically includes: Coating a photoresist on a portion of the surface of the device to expose a predetermined trench formation area; wet etching the device to form a trench; removing the photoresist and cleaning the device; The wet etching process uses high-temperature phosphoric acid, sulfuric acid and hydrogen peroxide mixed together to perform two consecutive etchings; The etching temperature of high-temperature phosphoric acid is between 170℃ and 220℃, and the etching temperature of sulfuric acid mixed with hydrogen peroxide is between 100℃ and 200℃.

2. The epitaxial wafer manufacturing method according to claim 1, characterized in that: The first groove and the second groove are staggered with each other in a vertical direction.

3. The epitaxial wafer manufacturing method according to claim 1, characterized in that: The first material is silicon, sapphire, or aluminum gallium nitride.

4. The epitaxial wafer manufacturing method according to claim 1, wherein: The second material is gallium nitride or aluminum nitride.

5. The epitaxial wafer manufacturing method according to claim 1, characterized in that: The third material is gallium nitride or sapphire.

6. The epitaxial wafer manufacturing method according to claim 1, characterized in that: After the epitaxial layer is formed, a planarization process is further included, and the planarization process includes: Obtaining the current thickness, highest point, and lowest point of the epitaxial layer; generating a flat thickness according to the highest point, the lowest point, and a preset lower thickness limit; The epitaxial layer is polished according to the flat thickness to complete the planarization process.

7. The epitaxial wafer manufacturing method according to claim 1, characterized in that: The thickness of the buffer layer is between 3nm and 10nm.

8. An epitaxial wafer, characterized in that: The method comprises a substrate, wherein a buffer layer and an epitaxial layer are sequentially arranged on the substrate; The upper surface of the substrate has a plurality of first grooves; The upper surface of the buffer layer has a plurality of second grooves; The epitaxial wafer is formed according to the epitaxial wafer manufacturing method according to any one of claims 1 to 7.

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