Chip package structure

Abstract

The application discloses a chip packaging structure, which comprises a substrate, a first chip layer located on one side of the substrate and comprising one or more chips, a non-functional surface of the chip of the first chip layer facing the substrate, a first re-wiring layer located on a side of the first chip layer opposite to the substrate and electrically connected with a functional surface of the chip of the first chip layer, a second chip layer located on a side of the first re-wiring layer opposite to the first chip layer and comprising one or more chips, a functional surface of the chip of the second chip layer facing the first re-wiring layer and electrically connected with the first re-wiring layer, a second re-wiring layer located on a side of the second chip layer opposite to the first re-wiring layer and electrically connected with the first re-wiring layer, and a bonding wire having one end electrically connected with the second re-wiring layer and the other end electrically connected with the substrate. The chip packaging structure provided by the application can realize longitudinal vertical stacking of three-dimensional multi-chips, save the lateral space of the substrate and save the cost.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a chip packaging structure. Background Technology

[0002] The description in this section provides only background information relevant to the disclosure in this specification and does not constitute prior art.

[0003] In the packaging industry, system-in-package (SiP) with horizontally arranged devices is the simplest structure, the easiest to achieve high yields, and therefore the most widely used. However, with the increasing demand for miniaturization of packages, it is necessary to stack chips or devices vertically to further reduce size.

[0004] 3D packaging is achieved by stacking chips. The interconnects after stacking can typically be implemented using wire bonding or through-silicon vias (TSVs). TSV technology has significant limitations and is relatively expensive, while wire bonding is a more traditional interconnect technology that is mature, low-cost, and widely used.

[0005] Wire bonding is a low-cost and relatively easy-to-implement 3D packaging solution commonly used in consumer memory products. Common wire interconnection methods after chip stacking include step-like stacking, stack by spacer, FOW (Film on Wire), and FOD (Film over Die), as described below. Figure 1 , Figure 2 , Figure 3 and Figure 4 As shown. Figures 1 to 4 The positional relationship of substrate 20, chip 30, pad 40 and bonding wire 50 is shown. Among them, staggered stacking and pad stacking leave space for lead interconnection by staggering or setting pads. FOW and FOD cover the lead or device with thick adhesive film.

[0006] However, when using staggered stacking for multi-chip applications, it can easily result in a larger lateral dimension of the product package. FOD (Fixed-Order) requires chips of different sizes. Pad stacking and FOW (Fixed-Out) methods require two bonding wires to be attached to the same bond finger, necessitating a larger bond finger on the substrate, which is not feasible with existing substrate sizes. Simultaneously, both solutions increase the overall vertical dimension of the package, and attaching two bonding wires to the same bond finger also introduces reliability risks.

[0007] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions in this specification and facilitating understanding by those skilled in the art. The fact that these solutions have been described in the background section of this specification should not be construed as meaning that the aforementioned technical solutions are known to those skilled in the art. Summary of the Invention

[0008] The main technical problem addressed by this application is to provide a chip packaging structure that enables vertical stacking of three-dimensional multi-chips, saving lateral space on the substrate and reducing costs.

[0009] To solve the above-mentioned technical problems, one technical solution adopted in this application is to provide a chip packaging structure, the chip packaging structure comprising:

[0010] substrate;

[0011] A first chip layer is located on one side of the substrate. The first chip layer includes one or more chips, and the non-functional surfaces of the chips in the first chip layer face the substrate.

[0012] The first redistribution layer is located on the side of the first chip layer facing away from the substrate, and the first redistribution layer is electrically connected to the functional surface of the chip of the first chip layer.

[0013] The second chip layer is located on the side of the first redistribution layer that is opposite to the first chip layer. The second chip layer includes one or more chips. The functional surfaces of the chips in the second chip layer face the first redistribution layer and are electrically connected to the first redistribution layer.

[0014] The second redistribution layer is located on the side of the second chip layer opposite to the first redistribution layer, and the second redistribution layer is electrically connected to the first redistribution layer.

[0015] The bonding wire has one end electrically connected to the second redistribution layer and the other end electrically connected to the substrate.

[0016] Furthermore, the chip packaging structure also includes:

[0017] A first dielectric layer is located on the side of the first chip layer away from the substrate, and the first dielectric layer at least covers the side of the first chip layer facing the first redistribution layer; the first dielectric layer has a first opening, the position of which corresponds to the pad on the chip of the first chip layer; the first redistribution layer is electrically connected to the functional surface of the chip of the first chip layer through the first opening.

[0018] Furthermore, the chip packaging structure also includes:

[0019] The second dielectric layer is located on the side of the first redistribution layer away from the substrate, and the second dielectric layer at least covers the side of the first redistribution layer away from the substrate; the second dielectric layer has a second opening, the position of which corresponds to the pad on the chip of the second chip layer, and the first redistribution layer is electrically connected to the functional surface of the chip of the second chip layer through the second opening.

[0020] Furthermore, the chips in the first chip layer correspond one-to-one with the chips in the second chip layer to form multiple chip groups; wherein, at least some of the chip groups have two chips with the same pad position, and the first opening and the second opening at the position of the two chips with the same pad position are aligned.

[0021] Furthermore, the chip packaging structure also includes:

[0022] A third dielectric layer is located on the side of the second chip layer away from the substrate, and the third dielectric layer at least covers the side of the second chip layer away from the substrate.

[0023] Furthermore, the third dielectric layer covers the side of the second chip layer opposite to the substrate and the side surface of the second chip layer; wherein, a conductive hole is provided in the third dielectric layer located on the side surface of the second chip layer, and the second redistribution layer is electrically connected to the first redistribution layer through the conductive hole.

[0024] Furthermore, the first dielectric layer, the second dielectric layer, and the third dielectric layer are arranged peripherally aligned.

[0025] Furthermore, the chip packaging structure also includes:

[0026] The solder mask and the first pad are located on the side of the second redistribution layer opposite to the second chip layer. The first pad is electrically connected to the second redistribution layer, and one end of the bonding wire is electrically connected to the first pad.

[0027] Furthermore, the first chip layer includes at least two chips, and the second chip layer includes at least two chips.

[0028] Furthermore, the chips of the first chip layer are aligned on a plane parallel to the surface of the substrate, the chips of the second chip layer are aligned on a plane parallel to the surface of the substrate, and the chips of the first chip layer and the chips of the second chip layer are aligned in a direction perpendicular to the surface of the substrate.

[0029] Unlike existing technologies, the advantages of this application are as follows: The chip packaging structure provided in this application, by sequentially arranging a first chip layer, a first redistribution layer, a second chip layer, and a second redistribution layer on one side of the substrate, with the first redistribution layer electrically connected to the first chip layer, the second chip layer, and the second redistribution layer respectively, more easily achieves vertical stacking of three-dimensional multi-chips, saving lateral space on the substrate and avoiding chip displacement problems caused by low chip alignment accuracy. The first chip layer may include one or more chips, and the second chip layer may also include one or more chips, reducing the overall vertical dimension. Electrical connection between the bonding wires leading from the top second redistribution layer and the substrate saves bonding wires and reduces costs. This chip packaging structure has lower requirements for equipment and environment, and the materials are inexpensive. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0031] Figure 1 This refers to the chip packaging structure that uses a staggered stacking method in existing technologies;

[0032] Figure 2 This is a chip packaging structure that uses a pad stacking method in the existing technology;

[0033] Figure 3 This refers to the chip packaging structure that uses FOW stacking in existing technologies;

[0034] Figure 4 This refers to the chip packaging structure that uses FOD stacking in existing technologies;

[0035] Figure 5 This is a schematic diagram of a chip packaging structure provided in this embodiment;

[0036] Figure 6 This embodiment provides a flowchart of the steps of a chip packaging method.

[0037] Figure 7 for Figure 6 A schematic diagram of a structural embodiment corresponding to step S12;

[0038] Figure 8 for Figure 13 A schematic diagram of a structural embodiment corresponding to step S131;

[0039] Figure 9 for Figure 6 A schematic diagram of the structure of one embodiment corresponding to step S14;

[0040] Figure 10 for Figure 15 A schematic diagram of a structural embodiment corresponding to step S151;

[0041] Figure 11 for Figure 6 A schematic diagram of a structural embodiment corresponding to step S16;

[0042] Figure 12 for Figure 6 A schematic diagram of a structural embodiment corresponding to steps S18 and S110;

[0043] Figure 13 for Figure 6 A flowchart of the steps between steps S12 and S14 in one embodiment;

[0044] Figure 14 for Figure 6 Step S14 is a flowchart of the implementation method.

[0045] Figure 15 for Figure 6 A flowchart of the steps between steps S14 and S16 in one embodiment;

[0046] Figure 16 for Figure 6 Step S16 is a flowchart of the implementation method.

[0047] Figure 17 for Figure 6 A flowchart of the steps between steps S16 and S18 in one embodiment;

[0048] Figure 18 for Figure 6 Step S18 is a flowchart of the implementation method.

[0049] Figure 19 for Figure 6 A flowchart of the steps between steps S18 and S110 in one embodiment.

[0050] Explanation of reference numerals in the attached figures:

[0051] 1. Substrate; 2. Adhesive; 3. First chip layer; 4. First redistribution layer; 5. Second chip layer; 6. Second redistribution layer; 7. Bonding wire; 8. First dielectric layer; 9. Second dielectric layer; 10. Third dielectric layer; 11. First opening; 12. Second opening; 13. Conductive via; 14. Solder resist layer; 15. First pad; 20. Substrate; 30. Chip; 40. Spacer; 50. Bonding wire. Detailed Implementation

[0052] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0053] It should be noted that when an element is referred to as being "set on" another element, it can be directly on the other element or may be interposed with another element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or may be interposed with another element. The terms "vertical," "horizontal," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only possible implementations.

[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0055] Please see Figure 5 This application provides a chip packaging structure, including a substrate 1, a first chip layer 3, a first redistribution layer 4, a second chip layer 5, a second redistribution layer 6, and bonding wires 7.

[0056] In this design, a first chip layer 3 is located on one side of the substrate 1 and includes one or more chips. The non-functional surfaces of the chips in the first chip layer 3 face the substrate 1. A first redistribution layer 4 is located on the side of the first chip layer 3 opposite to the substrate 1, and is electrically connected to the functional surfaces of the chips in the first chip layer 3. A second chip layer 5 is located on the side of the first redistribution layer 4 opposite to the first chip layer 3. The second chip layer 5 includes one or more chips. The functional surfaces of the chips in the second chip layer 5 face the first redistribution layer 4 and are electrically connected to it. A second redistribution layer 6 is located on the side of the second chip layer 5 opposite to the first redistribution layer 4, and is electrically connected to it. One end of a bonding wire 7 is electrically connected to the second redistribution layer 6, and the other end is electrically connected to the substrate 1.

[0057] The chip packaging structure provided in this application, by sequentially arranging a first chip layer 3, a first redistribution layer 4, a second chip layer 5, and a second redistribution layer 6 on one side of a substrate 1, with the first redistribution layer 4 electrically connected to the first chip layer 3, the second chip layer 5, and the second redistribution layer 6 respectively, easily achieves vertical stacking of three-dimensional multi-chips, saving lateral space on the substrate 1 and avoiding chip displacement problems caused by low chip alignment accuracy. The first chip layer 3 may include one or more chips, and the second chip layer 5 may also include one or more chips, reducing the overall vertical dimension. By electrically connecting the bonding wires 7 led from the top second redistribution layer 6 to the substrate 1, bonding wires can be saved, reducing costs. This chip packaging structure has low requirements for equipment and environment, and the materials are inexpensive.

[0058] In this embodiment, the chips of the first chip layer 3 can be mounted on the substrate 1 by dispensing adhesive, that is, adhesive 2 is provided between the first chip layer 3 and the substrate 1. When the first chip layer 3 includes multiple chips, theoretically the chips can be infinitely close to each other.

[0059] In this embodiment, the chip packaging structure may further include a first dielectric layer 8 located on the side of the first chip layer 3 facing away from the substrate 1. The first dielectric layer 8 at least covers the side of the first chip layer 3 facing the first redistribution layer 4. Preferably, the first dielectric layer 8 may also cover the side of the first chip layer 3, and the periphery of the first dielectric layer 8 is connected to the substrate 1. In this case, the first dielectric layer 8 completely encapsulates the first chip layer 3 and the adhesive between the first chip layer 3 and the substrate 1, thus protecting the chip of the first chip layer 3. The surface of the first dielectric layer 8 facing away from the first chip layer 3 is flat, which facilitates the subsequent formation of the first redistribution layer 4. The first dielectric layer 8 is an insulating layer, and its material may be polyimide (PI).

[0060] Specifically, the first dielectric layer 8 has a first opening 11, the position of which corresponds to the pad on the chip of the first chip layer 3. The shape of the first opening 11 can be consistent with the pad on the chip of the first chip layer 3. The first opening 11 can be formed by laser drilling. Laser drilling can accurately locate the opening position and depth of the first opening 11. The first redistribution layer 4 is electrically connected to the functional surface of the chip of the first chip layer 3 through the first opening 11. Specifically, the first opening 11 can be chemically plated and then electroplated with copper to form a first conductive element within the first opening 11, enabling the first opening 11 to be electrically connected to the functional surface of the chip of the first chip layer 3 through the first conductive element.

[0061] In this embodiment, while electroplating the first opening 11, a first metal layer can be formed on the surface of the first dielectric layer 8 facing away from the first chip layer 3, and the first conductive element is electrically connected to the first metal layer. Etching the first metal layer forms an RDL (Re-Distribution Layer), constituting the first redistribution layer 4. Preferably, the first metal layer is a copper layer.

[0062] In this embodiment, the chip packaging structure may further include a second dielectric layer 9 located on the side of the first redistribution layer 4 facing away from the substrate 1. The second dielectric layer 9 at least covers the side of the first redistribution layer 4 facing away from the substrate 1. Preferably, the second dielectric layer 9 may also cover the side of the first redistribution layer 4, and the periphery of the second dielectric layer 9 is connected to the first dielectric layer 8. In this case, the second dielectric layer 9 completely encapsulates the first redistribution layer 4, protecting it. The surface of the second dielectric layer 9 facing away from the first redistribution layer 4 is flat, facilitating the subsequent mounting of the second chip layer 5. The second dielectric layer 9 is an insulating layer, and its material may be polyimide (PI).

[0063] Specifically, a second opening 12 is provided on the second dielectric layer 9, and the position of the second opening 12 corresponds to the pad on the chip of the second chip layer 5. The shape of the second opening 12 can be the same as the pad on the chip of the second chip layer 5. The second opening 12 can be formed by laser drilling. Laser drilling can accurately locate the opening position and depth of the second opening 12. The first redistribution layer 4 is electrically connected to the functional surface of the chip of the second chip layer 5 through the second opening 12. Specifically, the second opening 12 can be chemically plated and then electroplated with copper to form a second conductive element within the second opening 12, so that the second opening 12 can be electrically connected to the functional surface of the chip of the second chip layer 5 through the second conductive element.

[0064] In this embodiment, conductive adhesive can be applied to the pads of the chip in the second chip layer 5, and the pads of the chip in the second chip layer 5 can be aligned with the second opening 12 for mounting, thereby forming the second chip layer 5. The amount of conductive adhesive can be precisely calculated based on the condition of the second opening 12. After high-temperature reflow, the second chip layer 5 can achieve conductivity with the first redistribution layer 4 and the first chip layer 3.

[0065] Specifically, the chips in the first chip layer 3 and the chips in the second chip layer 5 can be the same or different; this application does not impose a unique limitation on this. To further reduce costs, the first chip layer 3 includes at least two chips, and the second chip layer 5 includes at least two chips.

[0066] Preferably, on a plane parallel to the surface of substrate 1, that is... Figure 5 On the horizontal plane, the chips of the first chip layer 3 are aligned and arranged, and the chips of the second chip layer 5 are aligned and arranged. Here, the surface of substrate 1 refers to the side of substrate 1 on which the first chip layer 3 is mounted. In the direction perpendicular to the surface of substrate 1, that is... Figure 5 In the vertical direction, the chips of the first chip layer 3 and the chips of the second chip layer 5 are aligned, and the chips in the first chip layer 3 and the chips in the second chip layer 5 correspond one-to-one to form multiple chip groups. When the chips in the first chip layer 3 and the chips in the second chip layer 5 are the same, the positions of the two chip pads in the chip group are the same, and the first opening 11 and the second opening 12 at the positions of the two chips in the chip group are aligned.

[0067] In this embodiment, the chip packaging structure may further include a third dielectric layer 10 located on the side of the second chip layer 5 facing away from the substrate 1. The third dielectric layer 10 at least covers the side of the second chip layer 5 facing away from the substrate 1. Preferably, the third dielectric layer 10 may also cover the side of the second chip layer 5, and the periphery of the third dielectric layer 10 is connected to the second dielectric layer 9. In this case, the third dielectric layer 10 completely encapsulates the second chip layer 5, protecting the chip of the second chip layer 5. The surface of the third dielectric layer 10 facing away from the second chip layer 5 is flat, facilitating the subsequent formation of the second redistribution layer 6. The third dielectric layer 10 is an insulating layer, and its material may be polyimide (PI).

[0068] Specifically, a conductive via 13 is provided within the third dielectric layer 10 located on the side of the second chip layer 5, through which the second redistribution layer 6 is electrically connected to the first redistribution layer 4. The conductive via 13 can be formed by laser drilling. Laser drilling can precisely position and deepen the conductive via 13. Furthermore, the conductive via 13 can be chemically plated and then electroplated with copper to make it conductive.

[0069] In this embodiment, while electroplating the conductive via 13, a second metal layer can be formed on the surface of the third dielectric layer 10 opposite to the second chip layer 5, and the conductive via 13 is electrically connected to this second metal layer. Etching the second metal layer forms an RDL, constituting the second redistribution layer 6. Preferably, the second metal layer is a copper layer.

[0070] Preferably, the first dielectric layer 8, the second dielectric layer 9, and the third dielectric layer 10 are arranged in a peripheral alignment, thereby making the chip packaging structure more stable.

[0071] In this embodiment, the chip packaging structure may further include a solder mask layer 14 and a first pad 15 located on the side of the second redistribution layer 6 opposite to the second chip layer 5. The first pad 15 is electrically connected to the second redistribution layer 6, and one end of the bonding wire 7 is electrically connected to the first pad 15.

[0072] It should be noted that, Figure 5 The chip packaging structure in this embodiment is a two-layer, multi-chip fan-out packaging structure, and the number of chip layers is not uniquely limited in this embodiment. That is, the chip packaging structure can have multiple chip layers. It is only necessary to continue to set a third chip layer on the side of the second redistribution layer 6 away from the substrate 1, so that the chip in the third chip layer is electrically connected to the second redistribution layer 6, and then set a third redistribution layer on the side of the third chip layer away from the substrate 1, so that the third redistribution layer is electrically connected to the second redistribution layer 6. Then, by stacking upwards in the same way, multiple chip layers and redistribution layers are formed. Finally, the substrate 1 and the top redistribution layer are electrically connected by bonding wires 7.

[0073] Please see Figure 6 This application provides a chip packaging method, including the following steps:

[0074] Step S10: Provide substrate 1;

[0075] Step S12: A first chip layer 3 is formed on one side of the substrate 1. The first chip layer 3 includes one or more chips, and the non-functional surface of the chips in the first chip layer 3 faces the substrate 1.

[0076] Step S14: A first redistribution layer 4 is formed on the side of the first chip layer 3 facing away from the substrate 1. The first redistribution layer 4 is electrically connected to the functional surface of the chip in the first chip layer 3.

[0077] Step S16: A second chip layer 5 is formed on the side of the first redistribution layer 4 opposite to the first chip layer 3. The second chip layer 5 includes one or more chips. The functional surfaces of the chips in the second chip layer 5 face the first redistribution layer 4 and are electrically connected to the first redistribution layer 4.

[0078] Step S18: A second redistribution layer 6 is formed on the side of the second chip layer 5 opposite to the first redistribution layer 4, and the second redistribution layer 6 is electrically connected to the first redistribution layer 4.

[0079] Step S110: Use bonding wire 7 to electrically connect the second redistribution layer 6 and the substrate 1.

[0080] The chip packaging method provided in this application, by sequentially arranging a first chip layer 3, a first redistribution layer 4, a second chip layer 5, and a second redistribution layer 6 on one side of a substrate 1, with the first redistribution layer 4 electrically connected to the first chip layer 3, the second chip layer 5, and the second redistribution layer 6 respectively, easily achieves vertical stacking of three-dimensional multi-chips, saving lateral space on the substrate 1, and avoiding chip displacement problems caused by low chip alignment accuracy. The first chip layer 3 may include one or more chips, and the second chip layer 5 may also include one or more chips, reducing the overall vertical dimension. By electrically connecting the bonding wires 7 led from the top second redistribution layer 6 to the substrate 1, bonding wires can be saved, reducing costs. This chip packaging method has low requirements for equipment and environment, and the materials are inexpensive.

[0081] In step S12, as Figure 7 As shown, the chips in the first chip layer 3 can be mounted on the substrate 1 using adhesive bonding, meaning that adhesive 2 is provided between the first chip layer 3 and the substrate 1. When the first chip layer 3 includes multiple chips, theoretically, the chips can be placed infinitely close to each other.

[0082] like Figure 13 As shown, after step S12 and before step S14, the following steps may also be included:

[0083] Step S131: A first dielectric layer 8 is formed on the side of the first chip layer 3 away from the substrate 1, and the first dielectric layer 8 at least covers the side of the first chip layer 3 facing the first redistribution layer 4.

[0084] Step S132: A first opening 11 is formed on the first dielectric layer 8, and the position of the first opening 11 corresponds to the pad on the chip of the first chip layer 3.

[0085] In step S131, as Figure 8 As shown, the first dielectric layer 8 can also cover the side of the first chip layer 3, and the periphery of the first dielectric layer 8 is connected to the substrate 1. At this time, the first dielectric layer 8 completely encapsulates the first chip layer 3 and the adhesive between the first chip layer 3 and the substrate 1, protecting the chip of the first chip layer 3. The surface of the first dielectric layer 8 facing away from the first chip layer 3 remains flat, which facilitates the subsequent formation of the first redistribution layer 4. The first dielectric layer 8 is an insulating layer, and its material can be polyimide (PI).

[0086] In step S132, as Figure 9 As shown, the shape of the first opening 11 can be consistent with the pads on the chip of the first chip layer 3. The first opening 11 can be formed by laser drilling. Laser drilling can precisely locate the opening position and depth of the first opening 11.

[0087] In step S14, as Figure 14 and Figure 9 As shown, the steps for forming the first redistribution layer 4 may include:

[0088] Step S141: A first conductive element is formed in the first opening 11, so that the first conductive element is electrically connected to the functional surface of the chip in the first chip layer 3.

[0089] Step S142: A first metal layer is formed on the surface of the first dielectric layer 8 away from the first chip layer 3, and the first conductive element is electrically connected to the first metal layer;

[0090] Step S143: Etch the first metal layer to form the first redistribution layer 4.

[0091] In step S141, a first conductive element is formed in the first opening 11. This can be achieved by chemically plating the first opening 11 and then electroplating copper to fill it, so that the first opening 11 can be electrically connected to the functional surface of the chip in the first chip layer 3 through the first conductive element.

[0092] In step S142, the formation of the first metal layer can be performed simultaneously with the electroplating of the first opening 11. The first conductive element is electrically connected to the first metal layer. Preferably, the first metal layer is a copper layer.

[0093] In step S143, etching the first metal layer forms the RDL (Re-Distribution Layer), constituting the first redistribution layer 4. The first redistribution layer 4 is electrically connected to the functional surface of the chip in the first chip layer 3 through the first opening 11.

[0094] like Figure 15 As shown, after step S14 and before step S16, the following steps may also be included:

[0095] Step S151: A second dielectric layer 9 is formed on the side of the first redistribution layer 4 away from the substrate 1, and the second dielectric layer 9 at least covers the side of the first redistribution layer 4 away from the substrate 1.

[0096] Step S152: A second opening 12 is formed on the second dielectric layer 9, and the position of the second opening 12 corresponds to the pad on the chip of the second chip layer 5.

[0097] Step S153: A second conductive element is formed in the second opening 12, and the second conductive element is electrically connected to the first redistribution layer 4.

[0098] In step S151, as Figure 10 As shown, the second dielectric layer 9 can also cover the side of the first redistribution layer 4, and the periphery of the second dielectric layer 9 is connected to the first dielectric layer 8. In this case, the second dielectric layer 9 completely wraps around the first redistribution layer 4, protecting it. The surface of the second dielectric layer 9 facing away from the first redistribution layer 4 is flat, facilitating the subsequent mounting of the second chip layer 5. The second dielectric layer 9 is an insulating layer, and its material can be polyimide (PI).

[0099] In step S152, as Figure 11 As shown, the shape of the second opening 12 can be consistent with the pads on the chip of the second chip layer 5. The second opening 12 can be formed by laser drilling. Laser drilling can precisely locate the opening position and depth of the second opening 12.

[0100] In step S153, a second conductive element is formed within the second opening 12. This can be achieved by chemically plating the second opening 12 followed by electroplating with copper filler, so that the second opening 12 can be electrically connected to the functional surface of the chip in the second chip layer 5 through the second conductive element. The first redistribution layer 4 can be electrically connected to the functional surface of the chip in the second chip layer 5 through the second opening 12.

[0101] In step S16, as Figure 16 and Figure 11 As shown, the steps for forming the second chip layer 5 may include:

[0102] Step S161: Apply conductive adhesive to the pads of the chip in the second chip layer 5.

[0103] Step S162: Align the pads of the chip in the second chip layer 5 with the second opening 12 and install it. The second conductive element is electrically connected to the functional surface of the chip in the second chip layer 5.

[0104] In step S161, the amount of conductive adhesive can be precisely calculated based on the condition of the second opening 12. After step S162, and following high-temperature reflow, the second chip layer 5 can then achieve conductivity with the first redistribution layer 4 and the first chip layer 3.

[0105] Specifically, the chips in the first chip layer 3 and the chips in the second chip layer 5 can be the same or different; this application does not impose a unique limitation on this. To further reduce costs, the first chip layer 3 includes at least two chips, and the second chip layer 5 includes at least two chips.

[0106] Preferably, on a plane parallel to the surface of substrate 1, that is... Figure 11On the horizontal plane, the chips of the first chip layer 3 are aligned and arranged, and the chips of the second chip layer 5 are aligned and arranged. Here, the surface of substrate 1 refers to the side of substrate 1 on which the first chip layer 3 is mounted. In the direction perpendicular to the surface of substrate 1, that is... Figure 11 In the vertical direction, the chips of the first chip layer 3 and the chips of the second chip layer 5 are aligned, and the chips in the first chip layer 3 and the chips in the second chip layer 5 correspond one-to-one to form multiple chip groups. When the chips in the first chip layer 3 and the chips in the second chip layer 5 are the same, the positions of the two chip pads in the chip group are the same, and the first opening 11 and the second opening 12 at the positions of the two chips in the chip group are aligned.

[0107] like Figure 17 As shown, after step S16 and before step S18, the following steps may also be included:

[0108] Step S171: A third dielectric layer 10 is formed on the side of the second chip layer 5 away from the substrate 1, and the third dielectric layer 10 at least covers the side of the second chip layer 5 away from the substrate 1.

[0109] In step S171, as Figure 12 As shown, the third dielectric layer 10 can also cover the side of the second chip layer 5, and the periphery of the third dielectric layer 10 is connected to the second dielectric layer 9. In this case, the third dielectric layer 10 completely encapsulates the second chip layer 5, protecting the chip of the second chip layer 5. The surface of the third dielectric layer 10 facing away from the second chip layer 5 is flat, which facilitates the subsequent formation of the second redistribution layer 6. The third dielectric layer 10 is an insulating layer, and its material can be polyimide (PI).

[0110] like Figure 17 As shown, after step S171 and before step S18, the following steps are also included:

[0111] Step S172: A conductive hole 13 is provided in the third dielectric layer 10 on the side of the second chip layer 5, and the conductive hole 13 is electrically connected to the first redistribution layer 4.

[0112] In step S172, the conductive hole 13 can be formed by laser drilling. Laser drilling can precisely locate the opening position and depth of the conductive hole 13. The conductive hole 13 can be made conductive by chemical plating followed by electroplating with copper.

[0113] In step S18, as Figure 18 and Figure 12 As shown, the steps for forming the second redistribution layer 6 may include:

[0114] Step S181: A second metal layer is formed on the surface of the third dielectric layer 10 opposite to the second chip layer 5, and the conductive hole 13 is electrically connected to the second metal layer;

[0115] Step S182: Etch the second metal layer to form the second redistribution layer 6.

[0116] In step S181, the formation of the second metal layer can be performed simultaneously with the electroplating of the conductive hole 13. The second metal layer is preferably a copper layer.

[0117] In step S182, the second metal layer is etched to form the RDL, constituting the second redistribution layer 6. The second redistribution layer 6 is electrically connected to the first redistribution layer 4 through the conductive via 13.

[0118] Preferably, the first dielectric layer 8, the second dielectric layer 9, and the third dielectric layer 10 are arranged in a peripheral alignment, thereby making the chip packaging structure more stable.

[0119] like Figure 19 and Figure 12 As shown, after step S18 and before step S110, the following steps may also be included:

[0120] Step S19: A solder mask layer 14 and a first pad 15 are formed on the side of the second redistribution layer 6 opposite to the second chip layer 5. The first pad 15 is electrically connected to the second redistribution layer 6, and one end of the bonding wire 7 is electrically connected to the first pad 15.

[0121] It should be noted that, Figure 5 The chip packaging structure in this embodiment is a two-layer, multi-chip fan-out packaging structure, and the number of chip layers is not uniquely limited in this embodiment. That is, the chip packaging structure can have multiple chip layers. It is only necessary to continue to set a third chip layer on the side of the second redistribution layer 6 away from the substrate 1, so that the chip in the third chip layer is electrically connected to the second redistribution layer 6, and then set a third redistribution layer on the side of the third chip layer away from the substrate 1, so that the third redistribution layer is electrically connected to the second redistribution layer 6. Then, by stacking upwards in the same way, multiple chip layers and redistribution layers are formed. Finally, the substrate 1 and the top redistribution layer are electrically connected by bonding wires 7.

[0122] It should be noted that in the description of this specification, the terms "first," "second," etc., are used only for descriptive purposes and to distinguish similar objects; there is no order between them, nor should they be construed as indicating or implying relative importance. Furthermore, in the description of this specification, unless otherwise stated, "a plurality of" means two or more.

[0123] The use of the terms "comprising" or "including" to describe combinations of elements, components, parts, or steps herein also contemplates embodiments essentially consisting of such elements, components, parts, or steps. The use of the term "may" herein is intended to indicate that any described attribute included by "may" is optional.

[0124] Multiple elements, components, parts, or steps can be provided by a single integrated element, component, part, or step. Alternatively, a single integrated element, component, part, or step can be divided into multiple separate elements, components, parts, or steps. The use of "a" or "an" to describe an element, component, part, or step does not imply the exclusion of other elements, components, parts, or steps.

[0125] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A chip packaging structure, characterized in that, The chip packaging structure includes: a substrate; A first chip layer is located on one side of the substrate. The first chip layer includes one or more chips, and the non-functional surfaces of the chips in the first chip layer face the substrate. The first redistribution layer is located on the side of the first chip layer facing away from the substrate, and the first redistribution layer is electrically connected to the functional surface of the chip of the first chip layer. The second chip layer is located on the side of the first redistribution layer opposite to the first chip layer. The second chip layer includes one or more chips. The functional surfaces of the chips in the second chip layer face the first redistribution layer and are electrically connected to the first redistribution layer. The second redistribution layer is located on the side of the second chip layer opposite to the first redistribution layer, and the second redistribution layer is electrically connected to the first redistribution layer. The bonding wire has one end electrically connected to the second redistribution layer and the other end electrically connected to the substrate; A first dielectric layer is located on the side of the first chip layer away from the substrate, and the first dielectric layer at least covers the side of the first chip layer facing the first redistribution layer; the first dielectric layer has a first opening, the position of which corresponds to the pad on the chip of the first chip layer; the first redistribution layer is electrically connected to the functional surface of the chip of the first chip layer through the first opening. The second dielectric layer is located on the side of the first redistribution layer away from the substrate, and the second dielectric layer at least covers the side of the first redistribution layer away from the substrate; the second dielectric layer has a second opening, the position of the second opening corresponds to the pad on the chip of the second chip layer, and the first redistribution layer is electrically connected to the functional surface of the chip of the second chip layer through the second opening; The chips in the first chip layer correspond one-to-one with the chips in the second chip layer to form multiple chip groups; wherein, at least some of the chip groups have two chips with the same pad position, and the first opening and the second opening at the position of the two chips with the same pad position are aligned.

2. The chip packaging structure according to claim 1, characterized in that, The chip packaging structure further includes a third dielectric layer located on the side of the second chip layer away from the substrate, and the third dielectric layer at least covers the side of the second chip layer away from the substrate.

3. The chip packaging structure according to claim 2, characterized in that, The third dielectric layer covers the side of the second chip layer away from the substrate and the side surface of the second chip layer; A conductive hole is provided in the third dielectric layer located on the side of the second chip layer, and the second redistribution layer is electrically connected to the first redistribution layer through the conductive hole.

4. The chip packaging structure according to claim 2, characterized in that, The first dielectric layer, the second dielectric layer, and the third dielectric layer are arranged peripherally aligned.

5. The chip packaging structure according to claim 1, characterized in that, The chip packaging structure further includes: a solder mask layer and a first pad, the solder mask layer and the first pad being located on the side of the second redistribution layer opposite to the second chip layer, the first pad being electrically connected to the second redistribution layer, and one end of the bonding wire being electrically connected to the first pad.

6. The chip packaging structure according to claim 1, characterized in that, The first chip layer includes at least two chips, and the second chip layer includes at least two chips.

7. The chip packaging structure according to claim 6, characterized in that, The chips of the first chip layer are aligned on a plane parallel to the surface of the substrate, the chips of the second chip layer are aligned on a plane parallel to the surface of the substrate, and the chips of the first chip layer and the chips of the second chip layer are aligned in a direction perpendicular to the surface of the substrate.

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