semiconductor memory

Abstract

The present invention provides a semiconductor memory device comprising a semiconductor substrate having a memory area, a peripheral area surrounding the memory area, and multiple wordline structures. Active areas at the edge of the memory cell area intersect only one wordline structure, preventing unstable performance of the active area at the edge from affecting the performance of the entire memory device. Furthermore, the memory cell area and the peripheral area of the device have the same cell configuration, which can address microloading effects caused by varying pattern densities and free up more memory cell area.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor memory. Background Art

[0002] A memory device is an integrated circuit typically used in computer systems to store data. It is fabricated in a matrix format with one or more individual memory cells. Memory devices use bit lines (also known as digit lines, data lines, or read lines) and word lines (also known as access lines) for writing and reading. Bit lines electrically connect to memory cells along the vertical columns of the matrix, while word lines electrically connect to memory cells along the horizontal columns of the matrix. Each memory cell can be individually addressed using a combination of a bit line and a word line.

[0003] Memory devices can be volatile, semi-volatile, or non-volatile. In the absence of power, non-volatile memory devices can store data for a long time, while the data stored in volatile memory devices will dissipate, so they need to be constantly refreshed / rewritten to maintain their data storage. Memory devices use components such as capacitors to store charges, and read the charge of the capacitor to determine which storage state the memory cell is in, such as the "0" or "1" storage state, so as to achieve the purpose of data storage and reading. Memory devices also have electronic components such as transistors to control the switching of the gate and the storage and release of charge. There will be a peripheral circuit area around the memory cell array area of the memory device, and the bit lines and word lines will extend from the memory array area to the peripheral circuit area, and in this area are connected to the external circuit via other wires and interconnect structures such as contacts.

[0004] When manufacturing memory devices or other circuits, continuously miniaturizing and increasing the density of components to achieve higher storage capacity per unit area has always been a constant goal in the industry. However, as memory devices continue to shrink, their performance must be optimized, and their manufacturing processes also encounter many challenges that need to be overcome, such as microloading effects caused by varying pattern densities, insufficient layout space due to overly close spacing between components, and interference between components due to overly close spacing. The present invention is motivated by the need to overcome some of these problems encountered in circuit manufacturing. Summary of the Invention

[0005] To address the problems encountered in the aforementioned memory process, the present invention proposes a novel semiconductor memory device. The device's memory cell region and peripheral region have the same cell configuration, which can resolve the micro-loading effect caused by different pattern densities and free up more memory cell area. Furthermore, the active region at the edge of the memory cell region intersects only with one wordline structure, preventing the performance of the entire memory device from being affected by unstable performance of the active region at the edge.

[0006] A semiconductor memory device proposed in the present invention comprises: a semiconductor substrate having a memory cell region and a peripheral region located around the memory cell region; a device isolation layer defining a plurality of active regions extending along a third direction, wherein a portion of the active regions are completely located within the memory cell region to constitute a first active region, and another portion of the active regions are located at the edge of the memory cell region and extend to the peripheral region to constitute a second active region; and a plurality of word line structures embedded in the semiconductor substrate and extending along the first direction, wherein the first active region intersects with two word line structures, and the second active region intersects with one word line structure.

[0007] Optionally, a portion of the multiple active areas is completely located in the peripheral area to form a third active area, and the third active area does not intersect with the word line structure.

[0008] Optionally, a plurality of word line structures are sequentially arranged along the second direction, and the second active region extends to a peripheral region of the memory cell region facing the second direction.

[0009] Optionally, the semiconductor memory device also includes: a bit line structure located on the semiconductor substrate and extending in a second direction through the memory cell area and the peripheral area; a spacer structure located between the bit line structures; and a storage node contact structure located in the space defined by the spacer structure and the bit line structure in the memory cell area and connected to a portion of the active area in the semiconductor substrate.

[0010] Optionally, two storage node contact structures are connected to the first active region, and the storage node contact structure is connected to the end of the second active region located in the storage cell region.

[0011] Optionally, the storage node contact structure is further recessed into the semiconductor substrate to connect to the active area.

[0012] Optionally, the semiconductor memory device further includes: a sacrificial layer located in the space defined by the spacer structure and the bit line structure in the peripheral region.

[0013] Optionally, the sacrificial layer is formed above the end portion of the second active region located in the peripheral region.

[0014] Optionally, a portion of the multiple active areas is completely located in the peripheral area to form a third active area, and the sacrificial layer is formed above both ends of the third active area.

[0015] Optionally, an insulating interlayer is further provided between the sacrificial layer and the semiconductor substrate.

[0016] These and other objects of the present invention will become more readily apparent to the reader after reading the following detailed description of the preferred embodiment which is illustrated in various figures and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] This specification includes accompanying drawings, which form a part of this specification and are intended to provide a further understanding of embodiments of the present invention. These drawings depict some embodiments of the present invention and, together with the description herein, illustrate the principles thereof. In these drawings:

[0018] Figure 1 A plan view of a semiconductor memory device according to an embodiment of the present invention is shown;

[0019] Figure 2 It is along Figure 1 a cross-sectional view taken along the midline A-A';

[0020] Figure 3 It is along Figure 1 a cross-sectional view taken along the midline BB';

[0021] Figure 4 It is along Figure 1 Cross-section taken along the center line C-C';

[0022] Figure 5 It is along Figure 1 a cross-sectional view taken along the midline D-D';

[0023] Figure 6 According to another embodiment of the present invention Figure 1 a cross-sectional view taken along the midline A-A';

[0024] Figure 7 It is along Figure 1 a cross-sectional view taken along the center line EE'; and

[0025] Figure 8 FIG2 shows a plan view of a semiconductor memory device according to another embodiment of the present invention.

[0026] Please note that all illustrations in this manual are of a legend nature. For the sake of clarity and convenience of illustration, the components in the illustrations may be exaggerated or reduced in size and proportion. Generally speaking, the same reference symbols in the figures will be used to indicate corresponding or similar component features after modification or in different embodiments.

[0027] The description of the accompanying drawings is as follows:

[0028] 1a First doped region

[0029] 1b Second doped region

[0030] 100 semiconductor substrate

[0031] 102 storage unit area

[0032] 104 Outer District

[0033] 106 insulation layer

[0034] 108 spacer structure

[0035] 110 Storage node contact structure

[0036] 112 Sacrificial Layer

[0037] 114-bit line contact structure

[0038] 114a Upper part

[0039] 114b lower part

[0040] 116 External wire

[0041] 118 device isolation layer

[0042] 120 Insulation interlayer

[0043] 122 polysilicon layer

[0044] 124 Silicide layer

[0045] 126 Metal Layer

[0046] 128 hard mask layer

[0047] 130 Next door

[0048] 132 Covering insulation layer

[0049] 134 Depression

[0050] 136-bit line contact spacer

[0051] 138 gate hard mask layer

[0052] 140 gate insulating layer

[0053] ACT active area

[0054] BL bit line

[0055] C1 midline

[0056] C2 midline

[0057] D1 First direction

[0058] D2 Second direction

[0059] D3 third direction

[0060] WL word line DETAILED DESCRIPTION

[0061] The exemplary embodiments of the present invention will now be described in detail below, with reference to the accompanying drawings to illustrate the described features so that the reader can understand and achieve the technical effects. The reader will understand that the description herein is provided by way of example only and is not intended to limit the present invention. The various embodiments of the present invention and the various features of the embodiments that do not conflict with each other can be combined or rearranged in various ways. Modifications, equivalents, or improvements to the present invention will be understood by those skilled in the art without departing from the spirit and scope of the present invention and are intended to be included within the scope of the present invention.

[0062] Readers should be able to easily understand that the meanings of “on,” “above,” and “over” in this case should be interpreted broadly, so that “on” not only means “directly on” something, but also includes the meaning of being “on” something with intervening features or layers, and “on” or “over” not only means “on” or “above” something, but also includes the meaning of being “on” or “above” something with no intervening features or layers (i.e., directly on something).

[0063] In addition, spatially relative terms such as "under," "beneath," "lower," "over," and "upper" may be used herein for descriptive convenience to describe the relationship of one component or feature to another component or features, as shown in the accompanying drawings.

[0064] As used herein, the term "substrate" refers to the material onto which subsequent materials are added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or left unpatterned. Furthermore, the substrate can include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like.

[0065] As used herein, the term "layer" refers to a portion of a material that includes an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent that is less than the extent of the lower or upper structure. In addition, a layer may be an area of a homogeneous or inhomogeneous continuous structure having a thickness that is less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any horizontal faces at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along an inclined surface. A substrate may be a layer that may include one or more layers and / or may have one or more layers thereon, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductors and contact layers (in which contacts, interconnects, and / or vias are formed) and one or more dielectric layers.

[0066] In the illustrations in this manual, Figure 1 A plan view of a semiconductor memory device according to an embodiment of the present invention is shown, which illustrates a plan layout diagram of the semiconductor memory device of the present invention. Figures 2 to 5 They are respectively along Figure 1 The cross-sectional views taken along the center lines AA', BB', CC', and DD' illustrate the relative positions and connection relationships of the components in the memory cell region and the peripheral region of the semiconductor memory device of the present invention.

[0067] Please refer to Figure 1 The semiconductor memory device of the present invention is fabricated on a semiconductor substrate 100, such as a silicon substrate, a germanium substrate, and / or a silicon-germanium substrate. The semiconductor substrate 100 has a memory cell region 102 and a peripheral region 104 located around the memory cell region 102. The memory cell region 102 is used to arrange memory cells of the semiconductor memory device. Multiple memory cells are arranged in a matrix form in the memory cell region 102 and can store charges to generate distinct storage states. The peripheral region 104 is used to arrange peripheral circuits of the memory device, such as column decoders, row decoders, sense amplifiers, or I / O control modules. Active areas ACT are defined in the memory cell region 102 of the semiconductor substrate 100. Each active area ACT is separated by a surrounding device isolation layer. In the process, a photolithography process can be performed on the semiconductor substrate 100 to form individual separated active areas ACT, and an isolation material, such as silicon oxide, is filled into the grooves between the active areas ACT to form a device isolation layer. In the example, the active area ACT has a strip shape in a plan view and has a long axis extending in the third direction D3. The plurality of active areas ACT are evenly arranged in a staggered manner on the plane. Figure 1Only the peripheral region 104 located on one side of the memory cell region 102 is shown. In practice, the peripheral region 104 is present all around the memory cell region 102. Only the portion of the memory cell region 102 where the lines C-C' and D-D' pass through is depicted with the corresponding active region ACT for comparison with the cross-sectional view. In practice, the active region ACT is evenly distributed over the entire memory cell region 102.

[0068] Re-reference Figure 1 . A plurality of word line structures WL are provided in the semiconductor substrate 100, which are parallel to each other and spaced apart by a predetermined interval, and extend in a first direction D1 through the memory cell area 102. A plurality of bit line structures BL are also provided on the semiconductor substrate 100, which are parallel to each other and spaced apart by a predetermined interval, and extend in a second direction D2 through the memory cell area 102 and the peripheral area 104, wherein the second direction D2 is preferably orthogonal to the first direction D1, and the angle between the third direction D3 and the first direction D1 is preferably between 45 degrees and 90 degrees, and the angle between the second direction D2 and the first direction D1 is preferably between 0 degrees and 45 degrees. The word line structure WL is usually buried in the semiconductor substrate 100, and acts as an access transistor to control the switching of the gate and the access of charge. The bit line structure BL is usually provided on the semiconductor substrate 100, and is connected to the active area ACT to perform writing and reading operations. An insulating layer 106 is also formed around the bit line structure BL to isolate the bit line structure BL from surrounding components.

[0069] Re-reference Figure 1 . A plurality of spacer structures 108 are arranged between the bit line structures BL and the bit line structures BL on the semiconductor substrate 100, and their positions are approximately directly above the word line structure WL and are spaced a certain distance apart from each other. In the memory cell area 102, the spacer structure 108 and the bit line structure BL can jointly define a storage node area on the semiconductor substrate 100, on which a storage node contact structure 110 is arranged. In practice, charge storage components such as capacitors are also provided on the storage node contact structure 110, but this component is not the focus of this case and will not be shown in subsequent illustrations for the sake of simplicity. On the other hand, in the peripheral area 104, since there are no memory cells, the space defined by the spacer structure 108 and the bit line structure BL will not be used to set the storage node contact structure 110. On the contrary, the space will be filled with a sacrificial layer 112, which is a portion left over from the process of forming the spacer structure 108. The original sacrificial layer in the memory cell area 102 is removed after the spacer structure 108 is formed, and its space is used to set the storage node contact structure 110.

[0070] In the present embodiment, spacer structures 108 and the storage node contact structures 110 or sacrificial layers 112 separated therefrom are disposed between the bitline structures BL in both the memory cell region 102 and the peripheral region 104. Both the spacer structures 108 and the sacrificial layers 112 are formed of dielectric insulating materials, but the materials used are different. For example, the sacrificial layer 112 can be formed using a spin-on hard mask (SOH) silicon oxide, while the spacer structures 108 can be formed using an insulating material with etch selectivity relative to the sacrificial layer 112, such as silicon nitride. This feature is significantly different from conventional techniques. Conventional techniques generally do not employ spacer structures or sacrificial layer patterns between the bitline structures in the peripheral region; only the memory cell region exhibits such a grid-like pattern. Therefore, in conventional techniques, the patterns in the peripheral region and the memory cell region are quite different. Consequently, significant microloading effects can occur during the process, causing the patterns formed in these regions to deviate from and be inconsistent with the intended pattern. In contrast, in the present embodiment, the peripheral region 104 and the memory cell region 102 are designed to have substantially similar grid patterns. Thus, during the manufacturing process, the patterns formed in the two regions are more consistent, significantly reducing the pattern non-uniformity caused by the micro-loading effect.

[0071] Re-reference Figure 1 In the peripheral region 104, a bitline contact structure 114 is disposed above the bitline structure BL. This structure is used to connect the bitline structure BL to an external conductive line 116. The external conductive line 116 further connects the bitline structure BL to an external circuit, such as a column decoder, so that the column decoder can select a specific bitline structure BL to transmit data during operation. In an embodiment of the present invention, the bitline contact structures 114 are alternately connected to the bitline structures in the peripheral region 104 on both sides of the memory cell region 102 (only one side is shown in the figure). The bitline contact structures 114 have an elongated shape, with their long sides parallel to the second direction in which the bitline structure BL extends. More specifically, the long sides of the bitline contact structures 114 are longer than the length of the spacer structures 108 and / or the length of the sacrificial layer 112. This arrangement and characteristics of the bitline contact structures 114 effectively increase the process tolerance during the connection of the bitline contact structures 114, thereby overcoming the problem of insufficient layout space.

[0072] It should be noted that in some embodiments, a dummy region or redundant repair region may be provided between the memory cell region 102 and the peripheral region 104, where dummy memory cells or self-repair circuits may be installed. Since these regions and components are not the focus of this invention, they will not be shown or described in detail in the text and figures.

[0073] After explaining the planar layout of the semiconductor memory device of the present invention, the following will be Figures 2 to 5To illustrate the relative positions and connection relationships of the components of the semiconductor memory device of the present invention in the vertical direction. Figure 2 and Figure 3 , which illustrates a cross-sectional structure of the peripheral region 104 including the bit line contact structure 114, wherein Figure 2 The section line AA' cuts through the sacrificial layer 112 along the first direction D1. Figure 3 The section line BB′ cuts through the spacer structure 108 along the first direction D1.

[0074] like Figure 2 and Figure 3 As shown, in the peripheral region 104, the bit line structure BL is extended and disposed on the device isolation layer 118, i.e., the device isolation layer that isolates the active area ACT in the memory cell region 102. An insulating interlayer 120 is also provided between the bit line structure BL and the device isolation layer 118. In an embodiment of the present invention, each bit line structure BL may include, from bottom to top, a stacked polysilicon layer 122, a silicide layer 124, a metal layer 126, and a hard mask layer 128. Preferably, the polysilicon layer 122 may be made of doped polysilicon, the metal layer 126 may be made of tungsten, aluminum, titanium, or tantalum, and the hard mask layer 128 may be made of silicon nitride. Spacers 130 are also formed on the sidewalls of the bit line structure BL, on which a conformal insulating layer 106 is formed to isolate the bit line structure BL from surrounding components. The material of the spacers 130 may be, for example, silicon oxide. The insulating layer 106 is made of a material having etching selectivity with respect to both the spacers 130 and the insulating interlayer 120 , such as a silicon nitride layer and / or a silicon oxynitride layer.

[0075] Re-reference Figure 2 and Figure 3 Depending on the location, a sacrificial layer 112 or a spacer structure 108 is formed between the bit line structures BL on the peripheral region 104, wherein the top surfaces of the sacrificial layer 112 and the spacer structure 108 are flush with the top surfaces of the bit line structures BL. In the manufacturing process, the space between the bit line structures BL is first filled with a sacrificial layer 112. The sacrificial layer 112 can be formed using a spin-on hard mask (S0H) material, such as S0H silicon oxide. Thereafter, the pattern of the spacer structure 108 is carved out through a photolithography process and the spacer material is filled therein to form the spacer structure 108. The spacer structure 108 can be formed of an insulating material having an etching selectivity relative to the sacrificial layer 112. For example, the spacer structure 127 can be formed of silicon nitride. Thereafter, a capping insulating layer 132 is formed on the entire bit line structure BL, the spacer structure 108, and the sacrificial layer 112.

[0076] Finally, a bitline contact structure 114 is formed directly above and in contact with the bitline structure BL. In this embodiment, the bitline contact structure 114 is divided into an upper portion 114a with a larger planar area and a lower portion 114b with a smaller planar area. The upper portion 114a is formed in the cover insulating layer 132, while the lower portion 114b is formed at the location of the hard mask layer 128 of the bitline structure BL. The centerlines of the upper and lower portions 114a and 114b are aligned, and the left and right halves are symmetrical. In actual fabrication, a photolithography process is first performed to define the pattern of the upper portion 114a of the bitline contact structure 114 in the cover insulating layer 132. The non-conductive hard mask layer 128 of the bitline structure BL is then removed. A deposition process is then performed to fill the etched space with contact material to form the bitline contact structure 114. The bitline contact structure 114 directly contacts the metal layer 126 of the bitline structure BL. In the embodiment of the present invention, the design of different planar areas of the upper and lower halves of the bit line contact structure 114 can increase the contact area and process tolerance when connecting the bit line structure BL with the upper external conductive line 116 .

[0077] In other embodiments, Figure 6 As shown, the centerlines C1 and C2 of the upper and lower halves 114a and 114b of the bitline contact structure 114 may also be misaligned, causing the upper halves 114a to be horizontally offset relative to the lower halves 114b and the bitline structure BL, resulting in asymmetry between the left and right halves of the bitline contact structure 114. This phenomenon may be caused by pattern shift during the photolithography process of defining the pattern of the bitline contact structure 114. However, because the upper halves 114a of the bitline contact structure 114 are designed with a larger planar area, this effectively increases the process tolerance for manufacturing, overcoming this shift issue.

[0078] Please also refer to Figure 4 and Figure 5 , which depicts the cross-sectional structure of the memory cell region 102, wherein Figure 4 The section line CC' cuts through the storage node contact structure 110 along the first direction D1. Figure 5 The section line DD′ cuts through the spacer structure 108 along the first direction D1.

[0079] like Figure 4 and Figure 5As shown, in the memory cell area 102, unlike the peripheral area 104, its substrate is composed of an active area ACT and a device isolation layer 118 that isolates each active area ACT. Part of the active area ACT and the device isolation layer 118 are patterned by a photolithography process to form a word line trench along the second direction D2, and a conductive material is filled in the word line trench to form a word line structure WL. The material of the word line structure WL can be a metal, such as tungsten, aluminum, titanium and / or tantalum. The remaining trench space on the word line structure WL is filled with a gate hard mask layer 138, such as a silicon nitride layer. A gate insulation layer 140 is also formed between the word line structure WL and the active area ACT below to isolate the word line structure WL from the active area ACT.

[0080] Re-reference Figure 4 and Figure 5 The active area ACT may be formed with a first doping region 1a and a second doping region 1b, which are respectively located at both sides of the word line structure WL and at the center and both ends of the active area ACT (see FIG. Figure 1 ). The first doped region 1a and the second doped region 1b can be formed by an ion implantation process and may include dopants of a conductivity type opposite to that of the active region ACT. The bottom surfaces of the first doped region 1a and the second doped region 1b may be positioned at a predetermined depth below the top surface of the active region ACT. In addition, an insulating interlayer 120 may be formed on the surface of the active region ACT and the device isolation layer 118 to isolate the active region ACT below from the components above. The insulating interlayer 120 may be formed by a single insulating layer or multiple insulating layers, such as a silicon nitride layer, a silicon nitride layer and / or a silicon oxynitride layer. After forming the insulating interlayer 120, the active region ACT and the device isolation layer 118 may be patterned again by a photolithography process to form a recessed region 134 exposing the first doped region 1a, which corresponds to the center of the active region ACT. The bottom surface of the recessed region 134 may be higher than the bottom surface of the first doped region 1a (as shown by the dotted line). The polysilicon layer 122 of a portion of the bitline structure BL is formed in the recessed region 134 as a bitline contact that directly contacts the first impurity region 1a. Furthermore, the minimum width of the recessed region 134 can be greater than the width of each bitline structure BL. The polysilicon layer 122 of the bitline structure BL can be separated from the adjacent storage node contact structure 110 by a bitline contact spacer 136. The bitline contact spacer 136 can be formed of an insulating material having an etching selectivity relative to the insulating interlayer 107. For example, the bitline contact spacer 121 can include a silicon oxide layer, a silicon nitride layer, and / or a silicon oxynitride layer.

[0081] Re-reference Figure 4 and Figure 5. Similar to the peripheral area 104, a spacer structure 108 is formed between the bit line structures BL in the memory cell area 102. However, unlike the peripheral area 104, in the memory cell area 102, the space defined by the spacer structure 108 and the bit line structure BL is used to form a storage node contact structure 110, which is formed by removing the original sacrificial layer 112 there and then filling it with a conductive material. Each storage node contact structure 110 corresponds to a second doped region 1b of an active area ACT, and in order to make the two contact, the insulating interlayer 120 therebetween is removed through an etching process, so that part of the active area ACT and the device isolation layer 118 are removed, and part of the storage node contact structure 110 extends into the substrate. The storage node contact 110 can be formed from multiple components, including, for example, a doped semiconductor material (e.g., doped silicon), a metal (e.g., tungsten, aluminum, titanium, and / or tantalum), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, and / or tungsten nitride), and / or a metal-semiconductor alloy (e.g., metal silicide). In some other embodiments, the storage node contact 110 may include, from bottom to top, a polysilicon layer, a metal silicide layer, and a landing pad, each of which is further connected to a corresponding capacitor to serve as a storage node. Because these components are not the focus of the present invention, detailed descriptions of these components will be omitted to avoid obscuring the main focus of the invention.

[0082] Reference Figure 1 . In an embodiment of the present invention, a semiconductor memory device located at the junction of the memory cell area 102 and the peripheral area 104 will have a different structure and connection relationship than a normal semiconductor memory device. For this type of semiconductor memory device, its active area ACT may only have one word line WL passing through it instead of two. Specifically, a part of the multiple active areas ACT is completely located in the memory cell area 102. In this embodiment, the active area completely located in the memory cell area 102 can be defined as a first active area; another part of the multiple active areas ACT is located at the edge of the memory cell area 102 and extends to the peripheral area 104. In this embodiment, it can be defined as a second active area. As for the second active area, it can only intersect with one word line structure, while the first active area completely located in the memory cell area 102 can intersect with two word line structures. Furthermore, in some embodiments, the storage node contact structure is connected to the end of the second active area located in the memory cell area, which can be simultaneously referred to. Figure 7 For the doping region of this type of semiconductor memory device, the second doping region 1b located next to the word line WL is upwardly connected to a storage node contact structure 110, such as Figure 1As shown by circle F in FIG. 1 ; as for the other end of the second active region, since there is no word line WL, it only has a first doped region 1a, which spans the memory cell region 102 and the peripheral region 104. The portion located in the peripheral region 104 is upwardly connected to the sacrificial layer 112 that is not replaced by the storage node contact structure 110 (that is, the sacrificial layer 112 is formed above the end of the second active region located in the peripheral region), as shown in FIG. Figure 1 As shown by circle G in FIG. 1 , this feature is different from the configuration in which all the second doped regions 1 b in the memory cell region 102 are connected to the storage node contact structure 110 .

[0083] In other embodiments, Figure 8 As shown, a complete active area ACT may also be formed in the peripheral region 104, that is, a portion of the multiple active areas may be completely located in the peripheral region to form a third active area. However, the connection structure of the third active area will be different from that of the first active area located in the memory cell area 102. The two second doped regions 1b of the active area ACT located completely in the peripheral region 104 are both connected upward to the sacrificial layer 112, but are not connected to any storage node contact structure 110. In addition, the third active area does not intersect with the word line structure.

[0084] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A semiconductor memory device, characterized in that: Include: A semiconductor substrate having a memory cell region and a peripheral region located around the memory cell region; a device isolation layer defining a plurality of active regions extending along a third direction, wherein a portion of the active regions is completely located within the memory cell region to constitute a first active region, and another portion of the active regions is located at an edge of the memory cell region and extends to a peripheral region to constitute a second active region; and a plurality of word line structures embedded in the semiconductor substrate and extending along a first direction, wherein the first active region intersects with two word line structures, and the second active region intersects with one word line structure; A bit line structure is located on the semiconductor substrate and extends in a second direction through the memory cell area and the peripheral area; a spacer structure located between the bit line structures; a storage node contact structure, located in a space defined by the spacer structure and the bit line structure in the memory cell region and connected to a portion of the active area in the semiconductor substrate; as well as a sacrificial layer located in a space defined by the spacer structure and the bit line structure in the peripheral region; The storage node contact structure is connected to the end of the second active region located in the storage cell region, and the sacrificial layer is formed above the end of the second active region located in the peripheral region.

2. The semiconductor memory device according to claim 1, wherein A portion of the multiple active areas is completely located in the peripheral area to form a third active area, and the third active area does not intersect with the word line structure.

3. The semiconductor memory device according to claim 1, wherein A plurality of word line structures are sequentially arranged along a second direction, and the second active region extends to a peripheral region of the memory cell region facing the second direction.

4. The semiconductor memory device according to claim 1, wherein Two storage node contact structures are connected to the first active region.

5. The semiconductor memory device according to claim 1, wherein The storage node contact structure is further recessed into the semiconductor substrate to connect to the active region.

6. The semiconductor memory device according to claim 1, wherein A portion of the multiple active areas is completely located in the peripheral area to form a third active area, and the sacrificial layer is formed above both ends of the third active area.

7. The semiconductor memory device according to claim 1, wherein An insulating interlayer is further provided between the sacrificial layer and the semiconductor substrate.

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