Gate line break repairing method of array substrate, array substrate and display device

Abstract

The embodiments of the present disclosure provide a gate line break repair method for an array substrate, an array substrate, and a display device. The gate line break repair method includes the following steps: forming a first metal layer, exposing and etching the first metal layer to form a gate circuit, and detecting the gate line break point; forming a second metal layer, exposing the second metal layer, performing photoresist repair and etching on the exposed second metal layer to form a source-drain circuit; and repairing the line break on the formed array substrate. The technical solution of the embodiments of the present disclosure is aimed at the peripheral double-layer metal wiring. By pre-repairing the source-drain circuit photoresist, the source-drain circuit metal layer is etched after the photoresist repair, and the wiring repair in the double-layer metal area is transformed into the wiring repair in the single-layer metal area, thereby improving the success rate and reliability of the gate line break repair in the peripheral double-layer wiring area.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a gate disconnection repair method of an array substrate, an array substrate, and a display device. Background Art

[0002] In the existing array substrate production process, the double-layer metal wiring area of ​​the array substrate (such as Figure 1 The typical method for repairing gate wire breaks (as shown in the figure) is to drill holes, inject film, and then form a film to connect the broken wires after the array substrate is formed. This repair method requires drilling through the double metal layer, which easily leaves residual source and drain circuit metal layer material in the holes. This residual material is prone to warping, affecting the contact between the film and the gate metal. This results in a low success rate and reliability for wire break repair. Summary of the Invention

[0003] The embodiments of the present disclosure provide a method for repairing a gate disconnection of an array substrate to solve or alleviate one or more technical problems in the prior art.

[0004] As one aspect of an embodiment of the present disclosure, the present disclosure provides a method for repairing a gate disconnection of an array substrate, comprising the following steps:

[0005] The gate circuit forming step includes forming a first metal layer on the surface of the substrate, exposing and etching the first metal layer to form a gate circuit, and detecting the gate disconnection point;

[0006] a source-drain circuit forming step, comprising forming a second metal layer on a side of the first metal layer facing away from the substrate, exposing the second metal layer, performing photoresist repair on the exposed second metal layer, and etching to form the source-drain circuit;

[0007] The array substrate repairing step includes repairing gate disconnections on the formed array substrate.

[0008] In some possible implementations, the photoresist repair includes downloading the detected gate disconnection point, forming a photoresist layer on the surface of the second metal layer facing away from the substrate, and stripping off part of the photoresist on both sides of the gate disconnection point.

[0009] In some possible implementations, etching the second metal layer after the photoresist repair includes etching the second metal layer at the photoresist stripping location to form a single metal layer at the etched location.

[0010] In some possible implementations, repairing gate breakage on the formed array substrate includes applying photoresist to the repaired breakage points, and performing drilling, film injection, and film formation on the single metal layer areas on both sides of the gate breakage to repair the connection breakage.

[0011] In some possible implementations, photoresist stripping is performed using a picosecond laser.

[0012] In some possible implementations, the material used for repairing the broken wire is W.

[0013] In some possible implementations, a gate circuit protection film forming step and a metal oxide forming step are sequentially included between the gate circuit forming step and the source-drain circuit forming step.

[0014] As another aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide an array substrate, including a gate break repaired by using the above-mentioned gate break repair method.

[0015] As another aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a display device including the above-mentioned array substrate.

[0016] The gate line break repair method of the disclosed embodiment is repaired by stripping the pre-photoresist in the source-drain circuit forming step, and the double-layer metal area at the punching site is converted into a single-layer metal area after etching, and there is no metal residue, warping and other abnormalities in the hole; the success rate of the punching repair of the single-layer metal area is high and the reliability is good.

[0017] The above summary is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments and features described above, further aspects, embodiments and features of the present disclosure will be readily apparent by reference to the accompanying drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments according to the present disclosure and should not be regarded as limiting the scope of the present disclosure.

[0019] Figure 1 is a schematic diagram of a double-layer metal wiring area in an array substrate;

[0020] Figure 2 A schematic diagram of a process flow for repairing a broken line on an array substrate in the prior art;

[0021] Figure 3 A schematic diagram of a process flow for repairing a broken line on an array substrate in an embodiment of the present disclosure;

[0022] Figure 4 A schematic diagram of the cross-sectional structure of a peripheral double-layer metal wiring area in an array substrate of the prior art;

[0023] Figure 5A schematic diagram of drilling holes on both sides of a gate break line of an array substrate in the prior art;

[0024] Figure 6 This is a schematic diagram of the prior art of injecting a film into the hole of the array substrate to form a bridge to repair the broken line;

[0025] Figure 7 Schematic diagram of poor contact (A) and weak lines (B and C) formed when drilling holes in an array substrate in a conventional repair method;

[0026] Figure 8 Schematic diagram of gate disconnection locations detected in the gate circuit forming and AOI inspection steps of the gate disconnection repair method in one embodiment of the present disclosure;

[0027] Figure 9 A schematic diagram of a cross-sectional structure after a photoresist stripping step is performed in a gate disconnection repair method according to an embodiment of the present disclosure;

[0028] Figure 10 A schematic diagram of a cross-sectional structure after etching the source-drain circuit in a gate disconnection repair method according to an embodiment of the present disclosure;

[0029] Figure 11 A schematic cross-sectional view of the gate disconnection repair method according to an embodiment of the present disclosure after the source-drain circuit protection film forming step is performed;

[0030] Figure 12 A schematic cross-sectional structural diagram of a method for repairing a gate break in an embodiment of the present disclosure for drilling a hole in a single metal layer area;

[0031] Figure 13 Schematic diagram of the cross-sectional structure after gate breakage repairing by the gate breakage repairing method in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] Hereinafter, only certain exemplary embodiments are briefly described. As will be appreciated by those skilled in the art, the described embodiments may be modified in various ways without departing from the spirit or scope of the present disclosure. Therefore, the drawings and description are to be considered as illustrative in nature and not restrictive.

[0033] like Figure 2 As shown, the conventional method for preparing and repairing an array substrate includes the following steps:

[0034] S101 is a gate circuit forming step, comprising: forming a metal film of the gate circuit on a substrate, exposing and etching the metal film of the gate circuit to form a gate circuit pattern, and performing an automatic optical inspection on the formed gate circuit pattern to detect gate disconnection locations;

[0035] S102 forming a gate circuit protection film, including: forming a gate circuit protection film on a side of the gate circuit pattern facing away from the substrate;

[0036] S103 metal oxide forming, including: forming a metal oxide film on the side of the gate circuit protection film facing away from the substrate, and patterning it to form a semiconductor layer;

[0037] S104: forming a source-drain circuit, including: forming a metal film of the source-drain circuit on a side of the semiconductor layer facing away from the substrate, exposing and etching the metal film of the source-drain circuit to form a source-drain circuit pattern;

[0038] S105 forming a source-drain circuit protection film, including: forming a source-drain circuit protection film on a side of the source-drain circuit pattern layer facing away from the substrate;

[0039] S106 ITO forming, including: forming an ITO film on the side of the source / drain circuit protection film facing away from the substrate;

[0040] S107 Repairing the TFT array substrate, including: electrical inspection and array repair of the TFT array substrate, and repairing the peripheral gate disconnection.

[0041] like Figure 4 As shown, the peripheral wiring structure of the TFT array substrate includes a gate circuit layer 1, a source-drain circuit protection layer 2, a source-drain circuit layer 3 and a source-drain circuit protection layer 4, that is, the wiring structure includes a double metal layer, namely the gate circuit layer 1 and the source-drain circuit layer 3.

[0042] The conventional gate disconnection repair method includes the following steps: after the TFT array is constructed, the lower gate disconnection defect detected in step S101 is downloaded to the TFT array substrate repair equipment, and holes 5 are punched on both sides of the lower gate circuit layer near the disconnection site 7, as shown in FIG. Figure 5 Then, a film-forming material is injected into the formed via hole to fill the formed via hole and form a bridge repair line 8 on the passivation layer region between the via holes, as shown. Figure 6 shown.

[0043] Using the above repair method, it is necessary to penetrate two metal layers (gate circuit layer and source and drain circuit layer) when drilling. In particular, the metal layer of the source and drain circuit will form a barrier when drilling. Figure 7 As shown, the source and drain circuit metal layer material will remain in the hole or rise, which will affect the contact between the implanted film and the gate metal layer, resulting in poor contact 9 (see Figure 7 A), resulting in high impedance after repair and forming a weak line (see Figure 7 B and C), reducing the success rate and reliability of repair.

[0044] According to one embodiment of the present disclosure, a method for repairing a gate disconnection of an array substrate is provided, comprising the following steps:

[0045] The gate circuit forming step includes forming a first metal layer on the surface of the substrate, exposing and etching the first metal layer to form a gate circuit, and detecting the gate disconnection point;

[0046] a source-drain circuit forming step, comprising forming a second metal layer on a side of the first metal layer facing away from the substrate, exposing the second metal layer, performing photoresist repair on the exposed second metal layer, and etching to form the source-drain circuit;

[0047] The array substrate repairing step includes repairing gate disconnections on the formed array substrate.

[0048] Specifically, see Figure 3 According to an embodiment of the present disclosure, a method for preparing and repairing an array substrate includes the following steps in sequence.

[0049] S201 gate circuit formation, including: forming a first metal layer of the gate circuit on a substrate, exposing and etching the first metal layer of the gate circuit to form a gate circuit pattern, and performing automatic optical inspection (AOI inspection) on the formed gate circuit pattern to detect gate disconnection locations;

[0050] S202 forming a gate circuit protection film, including: forming a gate circuit protection film on a side of the gate circuit pattern facing away from the substrate;

[0051] S203 metal oxide forming, including: forming a metal oxide film on the side of the gate circuit protection film facing away from the substrate, and patterning it to form a semiconductor layer;

[0052] S204: forming a source-drain circuit, including: forming a second metal layer of the source-drain circuit on a side of the semiconductor layer facing away from the substrate, exposing the second metal layer of the source-drain circuit, performing photoresist repair on the exposed second metal layer, and etching to form a source-drain circuit pattern;

[0053] S205 forming a source-drain circuit protection film, including: forming a source-drain circuit protection film on a side of the source-drain circuit pattern layer facing away from the substrate;

[0054] S206 ITO forming, including: forming an ITO film on a side of the source / drain circuit protection film facing away from the substrate;

[0055] S207 Repairing the TFT array substrate, including: performing electrical inspection and array repair on the TFT array substrate, and repairing the peripheral gate disconnection.

[0056] Compared with the conventional method for repairing a gate disconnection of an array substrate, the method disclosed herein performs a photoresist repair step in advance during the source-drain circuit forming step before repairing the array substrate.

[0057] The photoresist repair comprises: downloading the gate break point detected by automatic optical inspection, forming a photoresist layer on the surface of the second metal layer away from the base substrate, and stripping the photoresist on both sides of the gate break.

[0058] After photoresist etching, the second metal layer, which has been repaired, not only etches the portion of the second metal layer complementary to the source / drain circuit pattern but also etches the portion of the second metal layer where the photoresist was stripped, forming a single metal layer area at the etched location. After completing subsequent array substrate processing steps, such as forming the source / drain circuit protection layer and the ITO layer, drilling, film injection, and bridging repairs are performed at the single metal layer location, resulting in a higher repair success rate and reliability.

[0059] According to an embodiment of the present disclosure, a method for repairing a gate disconnection of an array substrate includes the following steps.

[0060] After the gate circuit is formed according to the prior art method, AOI inspection is performed to detect the disconnection point 7 on the gate 1. Figure 8 shown.

[0061] like Figure 9 As shown, after the second metal layer 3 of the source-drain circuit is exposed, a photoresist layer 10 is formed on the surface of the second metal layer 3 facing away from the substrate, the broken line location detected by AOI is downloaded to the repair equipment, and part of the photoresist 11 on both sides of the gate broken line location 7 is stripped off. For example, the photoresist can be stripped off by a picosecond laser method to perform a photoresist repair step.

[0062] like Figure 10 As shown, the second metal layer after the photoresist repair is etched for source-drain circuits to remove the second metal layer at the position where the photoresist is stripped in the photoresist repair step, thereby forming a single metal layer area 12 on both sides of the disconnection site 7 .

[0063] like Figure 11 As shown, a source-drain circuit protection layer 4 is formed on the side of the second metal layer 3 away from the substrate after the source-drain circuit is etched.

[0064] like Figure 12 and Figure 13 As shown, a hole 13 is punched in a single metal layer region near the gate disconnection site 7 of the array substrate, and after the punching, film injection and film formation are performed to form a repaired connection disconnection 8. The repairing material used for the film injection and film formation can be W.

[0065] The gate line break repair method disclosed in the present invention pre-etches the double metal layer at the punching location into a single metal layer, and punching and repairing the single metal layer is a conventional repair method, which can improve product quality and repair success rate, increase yield, reduce reliability anomalies, and thus improve customer complaints.

[0066] If broken wires are repaired during the gate circuit forming step, the repair material (such as W) has the characteristic of diffusion during film formation. In actual mass production, the diffusion range can reach more than 15μm. Regardless of whether direct connection or bridge repair is used in the peripheral wiring area, the W film diffusion will cause short circuits in adjacent gate lines, resulting in low repair success rate and reliability.

[0067] If broken wires are repaired during the source / drain circuit formation step, the repair material (e.g., W) will diffuse during film formation. During actual mass production, the diffusion range can reach over 15μm. Regardless of whether direct connection or bridge repair is used in the peripheral wiring area, the diffusion of the repair material (e.g., W) will cause a short circuit between the underlying metal and the surrounding source / drain circuit metal materials, increasing the load and resulting in a large number of weak wires. This results in a low repair success rate and unreliable repair.

[0068] If the drilling and film repair are performed directly after the array substrate is completed, the following Figure 6 The cross-sectional structure of the peripheral double wiring area shown in the figure is that a double metal layer area near the disconnection point 7 is directly punched, injected and formed into a film to form a bridge repair line 8. This repair method has a low repair success rate and a high reliability failure rate (3%). Analysis found that the metal of the source and drain circuit layer has residual and warping phenomena during the punching process. When the repair material (such as W) is injected, it is blocked by the residual metal of the source and drain circuit layer, and the metal contact with the gate circuit layer is poor, which easily leads to abnormalities such as disconnection and weak line (such as Figure 7 shown).

[0069] The gate line break repair method in the embodiment of the present disclosure is aimed at the lower gate line break in the peripheral double-layer metal wiring area. Through the photoresist repair step performed in the previous source and drain circuit forming step, the double-layer metal wiring in the punching area is converted into a single-layer repair wiring while etching the source and drain circuit metal layer, thereby improving the success rate and reliability of the gate line break repair in the peripheral double-layer wiring area.

[0070] In the description of this specification, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0071] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of such features. Throughout the present disclosure, "plurality" means two or more, unless otherwise specifically defined.

[0072] In the present disclosure, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Moreover, a first feature being "above," "above," and "above" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0073] The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any person skilled in the art can easily conceive of various modifications or substitutions within the technical scope disclosed in this disclosure, and such modifications or substitutions should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A method for repairing a gate disconnection of an array substrate, characterized in that: The following steps are involved: The gate circuit forming step includes forming a first metal layer on the surface of the substrate, exposing and etching the first metal layer to form a gate circuit, and detecting the gate disconnection point; a source-drain circuit forming step, comprising forming a second metal layer on a side of the first metal layer facing away from the substrate, exposing the second metal layer, performing photoresist repair on the exposed second metal layer, and etching to form the source-drain circuit; Etching the second metal layer after the photoresist repair includes etching the second metal layer at the photoresist stripping location to form a single metal layer at the etched location; The array substrate repairing step includes repairing the gate break of the formed array substrate, wherein the photoresist repair includes downloading the detected gate break point, forming a photoresist layer on the surface of the second metal layer away from the base substrate, and stripping off part of the photoresist on both sides of the gate break point, forming a source and drain circuit protection layer on the side of the second metal layer away from the base substrate after the source and drain circuit is etched; repairing the gate break of the formed array substrate includes downloading the break point after the photoresist repair, and performing drilling, film injection and film formation on the single metal layer area on both sides of the gate break to repair the connection break.

2. The gate disconnection repair method according to claim 1, characterized in that: Photoresist stripping is performed using a picosecond laser.

3. The gate disconnection repair method according to claim 1, characterized in that: A gate circuit protection film forming step and a metal oxide forming step are sequentially included between the gate circuit forming step and the source-drain circuit forming step. 4 . An array substrate comprising a gate broken line repaired by the gate broken line repairing method according to claim 1 . 5 . A display device comprising the array substrate according to claim 4 .

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