A dual-energy flat panel detector structure

Abstract

The present invention relates to the field of detector technology, and in particular to a dual-energy flat-panel detector structure, comprising a photoelectric sensor array layer, the photoelectric sensor array layer comprising a high-energy sensor unit and a low-energy sensor unit, the photosensitive region structure of the high-energy sensor unit is a high-energy photosensitive transistor with an opaque top gate and a transparent bottom gate, and the photosensitive region structure of the low-energy sensor unit is a low-energy photosensitive transistor with a transparent top gate and an opaque bottom gate. By adopting photosensitive transistors for photosensitivity, the photosensitive transistors and thin-film transistors have fully compatible processes, and by designing the spacing between the source and the drain of the high-energy photosensitive transistor to be larger than the spacing between the source and the drain of the high-energy thin-film transistor, and designing the spacing between the source and the drain of the low-energy photosensitive transistor to be larger than the spacing between the source and the drain of the low-energy thin-film transistor, the photosensitivity performance of the photosensitive region can be increased, the photosensitivity area can be increased, and the pixel resolution can be improved.

Description

Technical Field

[0001] The present invention relates to the field of detector technology, and in particular to a dual-energy flat-panel detector structure. Background Art

[0002] The traditional dual-energy radiation detector is composed of two detection systems. The radiation first passes through the first thin layer of scintillator, where the low-energy X-rays are absorbed by the first thin layer of scintillator and converted into visible light photons. The generated visible light photons are then detected by the first layer of photoelectric sensor array, and a low-energy image is given. After the high-energy radiation passes through the first thin layer of scintillator and the first layer of photoelectric sensor array, it enters the second layer of scintillator, is converted into visible light photons, and is detected by the second layer of photoelectric sensor array, forming a high-energy image. This dual-energy radiation detector using two detection systems undoubtedly greatly increases the cost of the detector system, and causes the detector system to have a complex structure and a large volume. In addition, the alignment accuracy of the upper and lower sets of detectors will also have a great impact on data analysis. Inaccurate alignment often leads to measurement deviations, which in turn leads to a decrease in imaging quality. Therefore, a solution to integrate the two detection systems into one detection system has emerged. For details, please refer to the patent with publication number CN112713163A. This patented design uses an active matrix flat-panel imager composed of a PIN photodiode and a TFT: the PIN photodiode is a photosensitive structure that converts light into electrons; the TFT has a switching characteristic and periodically switches pixels through a matrix structure. The pixel electrical signal is read by an external circuit, and the image is reconstructed through the strength of the electrical signal and the coordinate point information to obtain a medical diagnosis picture. However, there are some problems with this combination of a PIN photodiode and a TFT: 1. The PIN photodiode has a poor photocurrent level: The PIN photodiode has a high internal quantum efficiency (Internal Quantum Efficiency, IQE) due to its good light absorption, but the external quantum efficiency (External Quantum Efficiency, EQE) is low, generally not higher than 1. In order to obtain a better photoelectric conversion efficiency, a larger area (>50*50μm 2), which will reduce pixel resolution and produce large parasitic capacitance; 2. On the other hand, the manufacturing process is complicated: the manufacturing sequence of PIN photodiodes is incompatible with the manufacturing sequence of a-Si:H TFT. The production process of ordinary photodiodes alone requires three to five more masks in the manufacturing process compared to the manufacturing process of a-Si:H TFT. For a dual-energy flat-panel detector that integrates two detectors into one, this conventional photodiode structure requires more masks for preparation because the pixels that sense high energy and the pixels that sense low energy need to sense light in different directions up and down and block light in the opposite direction. Compared with the manufacturing process of a-Si:H TFT, the number of masks required is increased by four to six, which leads to a sharp increase in process complexity, reduces product yield, and greatly increases product prices. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a dual-energy flat-panel detector structure capable of improving pixel resolution.

[0004] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0005] A dual-energy flat-panel detector structure comprises a first scintillator layer, on one side of which a ray filtering layer, a transparent substrate, a photoelectric sensor array layer and a second scintillator layer are sequentially stacked and covered, the photoelectric sensor array layer comprises high-energy sensor units and low-energy sensor units which are alternately distributed, the structure of the photosensitive region of the high-energy sensor unit is a high-energy photosensitive transistor with an opaque top gate and a transparent bottom gate, the structure of the photosensitive region of the low-energy sensor unit is a low-energy photosensitive transistor with a transparent top gate and an opaque bottom gate, the structure of the switch region of the high-energy sensor unit and the structure of the switch region of the low-energy sensor unit are both thin-film transistors, and are respectively a high-energy thin-film transistor and a low-energy thin-film transistor, the spacing between the source and the drain of the high-energy photosensitive transistor is greater than the spacing between the source and the drain of the high-energy thin-film transistor, and the spacing between the source and the drain of the low-energy photosensitive transistor is greater than the spacing between the source and the drain of the low-energy thin-film transistor.

[0006] The beneficial effects of the present invention are:

[0007] In this scheme, the structure of the photosensitive area of ​​the high-energy sensor unit is designed to be a high-energy photosensitive transistor with an opaque top gate and a transparent bottom gate, the structure of the photosensitive area of ​​the low-energy sensor unit is designed to be a low-energy photosensitive transistor with a transparent top gate and an opaque bottom gate, and the structure of the switch area of ​​the high-energy sensor unit and the structure of the switch area of ​​the low-energy sensor unit are both designed to be thin-film transistors. By using photosensitive transistors for light sensing, the photosensitive transistors and thin-film transistors have fully compatible processes, and the photosensitivity can be controlled and adjusted by gate voltage and source-drain voltage. Compared with traditional photodiodes, photosensitive transistors have higher light gain and better or equivalent responsiveness and quantum efficiency, and have higher gain and signal-to-noise ratio and smaller occupied area. By designing the spacing between the source and drain of the high-energy photosensitive transistor to be larger than the spacing between the source and drain of the high-energy thin-film transistor, and designing the spacing between the source and drain of the low-energy photosensitive transistor to be larger than the spacing between the source and drain of the low-energy thin-film transistor, the photosensitivity of the photosensitive area can be increased, the photosensitivity area can be increased, and the pixel resolution can be improved, thereby realizing the preparation of a dual-energy flat-panel detector with higher resolution. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A schematic structural diagram of a dual-energy flat panel detector according to the present invention;

[0009] Figure 2 A schematic structural diagram of a high-energy sensor unit of a dual-energy flat-panel detector structure according to the present invention;

[0010] Figure 3 A schematic structural diagram of a low-energy sensor unit of a dual-energy flat-panel detector structure according to the present invention;

[0011] Figure 4 A schematic structural diagram of an X-ray sensor with a dual-energy flat panel detector structure according to the present invention;

[0012] Figure 5 A schematic diagram of the configuration of photosensitive pixels of a photoelectric sensor array layer of a dual-energy flat panel detector structure according to the present invention;

[0013] Figure 6 It is a schematic diagram of the principle of a high-energy photosensitive transistor (or a low-energy photosensitive transistor) in a dual-energy flat-panel detector structure according to the present invention in a dark state and a bright state;

[0014] Description of labels:

[0015] 1. a first scintillator layer;

[0016] 2. Radiation filtering layer;

[0017] 3. Transparent substrate;

[0018] 4. Photoelectric sensor array layer; 41. High-energy sensor unit; 411. High-energy photosensitive transistor; 4111. First high-energy insulating layer; 4112. High-energy active layer; 4113. High-energy drain metal layer; 4114. Second high-energy insulating layer; 4115. High-energy top gate metal layer; 4116. Third high-energy insulating layer; 412. High-energy thin film transistor; 4121. First switch insulating layer; 4122. Switch active layer; 4123. Switch source and drain metal layer; 4124, second switch insulating layer; 4125, mask layer; 4126, third switch insulating layer; 4127, switch bottom gate metal layer; 42, low energy sensor unit; 421, low energy photosensitive transistor; 4211, first low energy insulating layer; 4212, low energy active layer; 4213, low energy drain metal layer; 4214, second low energy insulating layer; 4215, low energy bottom gate metal layer; 4216, third low energy insulating layer; 422, low energy thin film transistor;

[0019] 5. Second scintillator layer. DETAILED DESCRIPTION

[0020] In order to explain the technical content, achieved objectives and effects of the present invention in detail, the following is an explanation in combination with the implementation modes and the accompanying drawings.

[0021] Please refer to Figure 1 , the technical solution provided by the present invention:

[0022] A dual-energy flat-panel detector structure comprises a first scintillator layer, on one side of which a ray filtering layer, a transparent substrate, a photoelectric sensor array layer and a second scintillator layer are sequentially stacked and covered, the photoelectric sensor array layer comprises high-energy sensor units and low-energy sensor units which are alternately distributed, the structure of the photosensitive region of the high-energy sensor unit is a high-energy photosensitive transistor with an opaque top gate and a transparent bottom gate, the structure of the photosensitive region of the low-energy sensor unit is a low-energy photosensitive transistor with a transparent top gate and an opaque bottom gate, the structure of the switch region of the high-energy sensor unit and the structure of the switch region of the low-energy sensor unit are both thin-film transistors, and are respectively a high-energy thin-film transistor and a low-energy thin-film transistor, the spacing between the source and the drain of the high-energy photosensitive transistor is greater than the spacing between the source and the drain of the high-energy thin-film transistor, and the spacing between the source and the drain of the low-energy photosensitive transistor is greater than the spacing between the source and the drain of the low-energy thin-film transistor.

[0023] From the above description, it can be seen that the beneficial effects of the present invention are:

[0024] In this scheme, the structure of the photosensitive area of ​​the high-energy sensor unit is designed to be a high-energy photosensitive transistor with an opaque top gate and a transparent bottom gate, the structure of the photosensitive area of ​​the low-energy sensor unit is designed to be a low-energy photosensitive transistor with a transparent top gate and an opaque bottom gate, and the structure of the switch area of ​​the high-energy sensor unit and the structure of the switch area of ​​the low-energy sensor unit are both designed to be thin-film transistors. By using photosensitive transistors for light sensing, the photosensitive transistors and thin-film transistors have fully compatible processes, and the photosensitivity can be controlled and adjusted by gate voltage and source-drain voltage. Compared with traditional photodiodes, photosensitive transistors have higher light gain and better or equivalent responsiveness and quantum efficiency, and have higher gain and signal-to-noise ratio and smaller occupied area. By designing the spacing between the source and drain of the high-energy photosensitive transistor to be larger than the spacing between the source and drain of the high-energy thin-film transistor, and designing the spacing between the source and drain of the low-energy photosensitive transistor to be larger than the spacing between the source and drain of the low-energy thin-film transistor, the photosensitivity of the photosensitive area can be increased, the photosensitivity area can be increased, and the pixel resolution can be improved, thereby realizing the preparation of a dual-energy flat-panel detector with higher resolution.

[0025] Furthermore, the high-energy photosensitive transistor includes a first high-energy insulating layer, which covers a side of the transparent substrate away from the ray filtering layer, and a high-energy active layer, a high-energy drain metal layer, a second high-energy insulating layer, a high-energy top gate metal layer and a third high-energy insulating layer are sequentially stacked on the side of the first high-energy insulating layer away from the transparent substrate;

[0026] The high energy drain metal layer comprises a high energy electrode layer and a high energy drain layer, and the distance between the high energy electrode layer and the high energy drain layer is greater than the distance between the source and the drain of the high energy thin film transistor.

[0027] Furthermore, the length of the high-energy top gate metal layer in a vertical cross section is greater than or equal to the distance between the high-energy source layer and the high-energy drain layer.

[0028] From the above description, it can be seen that designing the length of the high-energy top gate metal layer in the vertical section to be greater than or equal to the distance between the high-energy source layer and the high-energy drain layer can further improve the photosensitivity of the photosensitive area of ​​the high-energy sensor unit, thereby further improving the pixel resolution.

[0029] Furthermore, the high-energy top gate metal layer is located directly above the gap between the high-energy source layer and the high-energy drain layer.

[0030] From the above description, it can be seen that designing the high-energy top gate metal layer just above the gap between the high-energy source layer and the high-energy drain layer can further improve the photosensitivity of the photosensitive area of ​​the high-energy sensor unit, thereby further improving the pixel resolution.

[0031] Furthermore, the distance between the high energy source layer and the high energy drain layer ranges from 5 μm to 30 μm.

[0032] From the above description, it can be seen that setting the spacing range between the high energy source layer and the high energy drain layer to 5 μm-30 μm can further improve the photosensitivity of the photosensitive area of ​​the high energy sensor unit, thereby further improving the pixel resolution.

[0033] Furthermore, the low-energy transistor includes a first low-energy insulating layer, the first low-energy insulating layer covers a side of the transparent substrate away from the ray filtering layer, the side of the first low-energy insulating layer away from the transparent substrate is sequentially stacked with a low-energy active layer, a low-energy drain metal layer, a second low-energy insulating layer and a third low-energy insulating layer, and a low-energy bottom gate metal layer is further included between the first low-energy insulating layer and the transparent substrate, and the low-energy bottom gate metal layer is in contact with the first low-energy insulating layer and the transparent substrate respectively;

[0034] The low-energy drain metal layer includes a low-energy electrode layer and a low-energy drain layer, and the distance between the low-energy electrode layer and the low-energy drain layer is greater than the distance between the source and the drain of the low-energy thin film transistor.

[0035] Furthermore, the length of the low-energy bottom gate metal layer in a vertical cross section is greater than or equal to the distance between the low-energy source electrode layer and the low-energy drain electrode layer.

[0036] From the above description, it can be seen that designing the length of the low-energy bottom gate metal layer in the vertical section to be greater than or equal to the spacing between the low-energy source layer and the low-energy drain layer can further improve the photosensitivity of the photosensitive area of ​​the low-energy sensor unit, thereby further improving the pixel resolution.

[0037] Furthermore, the low-energy bottom gate metal layer is located directly below the gap between the low-energy source layer and the low-energy drain layer.

[0038] From the above description, it can be seen that designing the low-energy bottom gate metal layer directly below the gap between the low-energy source layer and the low-energy drain layer can further improve the photosensitivity of the photosensitive area of ​​the low-energy sensor unit, thereby further improving the pixel resolution.

[0039] Furthermore, the distance between the low energy source layer and the low energy drain layer ranges from 5 μm to 30 μm.

[0040] From the above description, it can be seen that setting the spacing range between the low energy source layer and the low energy drain layer to 5 μm-30 μm can further improve the photosensitivity of the photosensitive area of ​​the low energy sensor unit, thereby further improving the pixel resolution.

[0041] Furthermore, the high-energy thin-film transistor includes a first switch insulating layer, which covers a side of the transparent substrate away from the radiation filtering layer, and a switch active layer, a switch source and drain metal layer, a second switch insulating layer, a mask layer and a third switch insulating layer are sequentially stacked on the side of the first switch insulating layer away from the transparent substrate. A switch bottom gate metal layer is also provided between the first switch insulating layer and the transparent substrate, and the switch bottom gate metal layer is in contact with the first switch insulating layer and the transparent substrate respectively.

[0042] Please refer to Figures 1 to 6 , Embodiment 1 of the present invention is:

[0043] Please refer to Figure 1 , Figure 2 and Figure 3 A dual-energy flat panel detector structure comprises a first scintillator layer 1, on one side of which a ray filtering layer 2, a transparent substrate 3, a photoelectric sensor array layer 4 and a second scintillator layer 5 are sequentially stacked, the photoelectric sensor array layer 4 comprises high-energy sensor units 41 and low-energy sensor units 42 which are alternately distributed, the photosensitive region of the high-energy sensor unit 41 has a structure of a high-energy photosensitive transistor 411 with an opaque top gate and a transparent bottom gate, and the photosensitive region of the low-energy sensor unit 42 has a structure of a top gate transparent The low-energy photosensitive transistor 421 has an opaque bottom gate, and the structure of the switch area of ​​the high-energy sensor unit 41 and the structure of the switch area of ​​the low-energy sensor unit 42 are both thin-film transistors, which are respectively a high-energy thin-film transistor 412 and a low-energy thin-film transistor 422. The spacing between the source and the drain of the high-energy photosensitive transistor 411 is greater than the spacing between the source and the drain of the high-energy thin-film transistor 412, and the spacing between the source and the drain of the low-energy photosensitive transistor 421 is greater than the spacing between the source and the drain of the low-energy thin-film transistor 422.

[0044] Please refer to Figure 2 The high-energy photosensitive transistor 411 includes a first high-energy insulating layer 4111, which covers the side of the transparent substrate 3 away from the ray filtering layer 2, and the side of the first high-energy insulating layer 4111 away from the transparent substrate 3 is sequentially stacked with a high-energy active layer 4112, a high-energy drain metal layer 4113, a second high-energy insulating layer 4114, a high-energy top gate metal layer 4115 and a third high-energy insulating layer 4116; the material of the high-energy active layer 4112 is amorphous silicon (i.e., a-Si:H).

[0045] Please refer to Figure 2 The high-energy drain metal layer 4113 includes a high-energy electrode layer and a high-energy drain layer, and the distance between the high-energy electrode layer and the high-energy drain layer is greater than the distance between the source and the drain of the high-energy thin film transistor 412.

[0046] Please refer to Figure 2 , the length of the high-energy top gate metal layer 4115 in the vertical cross section is greater than or equal to the distance between the high-energy source layer and the high-energy drain layer.

[0047] Please refer to Figure 2 The high energy top gate metal layer 4115 is located directly above the gap between the high energy source layer and the high energy drain layer.

[0048] The distance between the high energy source layer and the high energy drain layer is in the range of 5 μm-30 μm, preferably 15 μm.

[0049] The width of the high-energy active layer 4112 ranges from 4μm to 50μm, with a preferred value of 6μm; the length of the high-energy active layer 4112 ranges from 100μm to 3000μm, with a preferred value of 300μm; the height of the high-energy active layer 4112 ranges from 0.1μm to 1μm, with a preferred value of 0.3μm, which can improve the sensitivity of the high-energy photosensitive transistor 411 to low-dose X-rays to further improve the photosensitivity.

[0050] Please refer to Figure 3 The low-energy transistor includes a first low-energy insulating layer 4211, which covers the side of the transparent substrate 3 away from the ray filtering layer 2, and the side of the first low-energy insulating layer 4211 away from the transparent substrate 3 is sequentially stacked with a low-energy active layer 4212, a low-energy drain metal layer 4213, a second low-energy insulating layer 4214 and a third low-energy insulating layer 4216, and a low-energy bottom gate metal layer 4215 is also included between the first low-energy insulating layer 4211 and the transparent substrate 3, and the low-energy bottom gate metal layer 4215 is in contact with the first low-energy insulating layer 4211 and the transparent substrate 3 respectively; the material of the low-energy active layer 4212 is amorphous silicon (i.e., a-Si:H).

[0051] Please refer to Figure 3 The low-energy drain metal layer 4213 includes a low-energy electrode layer and a low-energy drain layer, and the distance between the low-energy electrode layer and the low-energy drain layer is greater than the distance between the source and the drain of the low-energy thin film transistor 422.

[0052] Please refer to Figure 3 , the length of the low-energy bottom gate metal layer 4215 in the vertical cross section is greater than or equal to the distance between the low-energy source layer and the low-energy drain layer.

[0053] Please refer to Figure 3 , the low-energy bottom gate metal layer 4215 is located directly below the gap between the low-energy electrode layer and the low-energy drain layer.

[0054] The distance between the low energy electrode layer and the low energy drain electrode layer is in the range of 5 μm to 30 μm.

[0055] The width of the low-energy active layer 4212 ranges from 4 μm to 50 μm, the length of the low-energy active layer 4212 ranges from 100 μm to 3000 μm, and the height of the low-energy active layer 4212 ranges from 1000 μm to 10000 μm, which can improve the sensitivity of the low-energy photosensitive transistor 421 to low-dose X-rays to further improve the photosensitivity.

[0056] The high-energy thin film transistor 412 comprises a first switch insulating layer 4121, which covers the side of the transparent substrate 3 away from the ray filtering layer 2, and the side of the first switch insulating layer 4121 away from the transparent substrate 3 is sequentially stacked with a switch active layer 4122, a switch source and drain metal layer 4123, a second switch insulating layer 4124, a mask layer 4125 and a third switch insulating layer 4126, and a switch bottom gate metal layer 4127 is further provided between the first switch insulating layer 4121 and the transparent substrate 3, and the switch bottom gate metal layer 4127 is in contact with the first switch insulating layer 4121 and the transparent substrate 3 respectively. The switch active layer 4122 is amorphous silicon (i.e., a-Si:H).

[0057] The first high-energy insulating layer 4111, the first low-energy insulating layer 4211 and the first switch insulating layer 4121 can be prepared by the same process flow;

[0058] The high energy active layer 4112, the low energy active layer 4212 and the switch active layer 4122 can be prepared by the same process flow;

[0059] The high energy drain metal layer 4113, the low energy drain metal layer 4213 and the switch source drain metal layer 4123 can be prepared by the same process flow;

[0060] The second high-energy insulating layer 4114, the second low-energy insulating layer 4214 and the second switch insulating layer 4124 can be prepared by the same process flow;

[0061] The high energy top gate metal layer 4115 and the mask layer 4125 can be prepared by the same process flow;

[0062] The third high-energy insulating layer 4116, the third low-energy insulating layer 4216 and the third switch insulating layer 4126 can be prepared by the same process flow;

[0063] The low energy bottom gate metal layer 4215 and the switch bottom gate metal layer 4127 can be prepared by the same process flow;

[0064] The thickness of the first scintillator layer 1 is greater than that of the second scintillator layer 5. The thickness of the first scintillator is 300μm-1500μm, and the preferred value is 800μm; the thickness of the second scintillator layer 5 is 100μm-1000μm, and the preferred value is 500μm; the second scintillator layer 5 has a relatively low thickness, which can absorb low-energy X-rays while reducing the absorption of high-energy X-rays, while the first scintillator layer 1 has a relatively large thickness and can fully absorb high-energy X-rays.

[0065] The materials of the first scintillator layer 1 and the second scintillator layer 5 can be the same or different, and can be selected from, but not limited to, GOS (Gd 2 O 2 S)、NaI(T1)、LaC 13 (Ce), CsI(T1, Na), LaBr 3 (Ce), YAlO 3 (Ce), CsI, GOS (Tb, Pr, Ce, F), CaWO4, Gd 3 Ga 5 O 12 (Cr, Ce), Lu 2 Si 2 O 7 (Ce), CdWO 4 、BGO、Lu 2 SiO 5 (Ce), Lu 2 AlO 3 (Ce), YTaO 4 (Nb) or more.

[0066] The material of the ray filtering layer 2 is an optical fiber panel, which has the advantages of high light transmission efficiency, small inter-stage coupling loss, clear and real image transmission, and zero optical thickness.

[0067] The transparent substrate 3 is a substrate for preparing the high and low energy sensor unit 42, which can be rigid or flexible. The material of the transparent substrate 3 is a combination of one or more of PI (Polyimide in English), ultra-thin glass and PET (Polyethylene terephthalate), and its thickness can be 10μm-50μm, with a preferred value of 40μm.

[0068] Please refer to Figure 4, is a schematic diagram of the structure of the X-ray sensor, which provides the gate drive voltage of the switch TFT through the scanning drive electrode, and the data drive and reading circuit provides the data drive voltage and reads the electrical signal of the high and low energy sensor unit 42, and obtains the high and low energy X-ray images through the back-end analysis and processing;

[0069] Please refer to Figure 5 , which is a schematic diagram of the configuration of the photosensitive pixels of the photoelectric sensor array layer 4; to further improve the imaging quality, the high-energy sensor units 41 and the low-energy sensor units 42 are arranged in a chessboard array with multiple rows and columns, and the missing pixel grayscale values ​​in the low-energy and high-energy pixels can be replaced by the average of the four similar pixels around them (the parts framed by dotted or solid lines), and an image obtained by a single exposure can be converted into a low-energy image and a high-energy image.

[0070] Please refer to Figure 6 , is a schematic diagram of the high-energy photosensitive transistor 411 (or low-energy photosensitive transistor 421) in the dark state and the bright state of this scheme. Its working principle is to use the amorphous silicon (a-Si) semiconductor of the TFT active layer as the optical active area, and use the photogenerated carriers to change the leakage current when light is irradiated. Compared with the traditional PID photosensitive diode flat panel detector, this structure has the following advantages: 1. It occupies a small area and can prepare a flat panel detector with higher resolution. 2. High light conversion efficiency, EQE>1000%; 3. The leakage current (Id) can be amplified to achieve fast response; 4. The structure is simple and has strong compatibility with ordinary TFT production processes. Photosensitive TFTs and switching TFTs can be prepared through the same process flow; 5. It can be controlled and adjusted by gate voltage and source-drain voltage.

[0071] In summary, the present invention provides a dual-energy flat-panel detector structure. In this scheme, the structure of the photosensitive area of ​​the high-energy sensor unit is designed to be a high-energy photosensitive transistor with an opaque top gate and a transparent bottom gate, and the structure of the photosensitive area of ​​the low-energy sensor unit is designed to be a low-energy photosensitive transistor with a transparent top gate and an opaque bottom gate. The structure of the switch area of ​​the high-energy sensor unit and the structure of the switch area of ​​the low-energy sensor unit are both designed as thin-film transistors. By using photosensitive transistors for light sensing, the photosensitive transistors and thin-film transistors have a fully compatible process, and the photosensitivity can be controlled and adjusted by the gate voltage and the source-drain voltage. Section, compared with traditional photodiodes, phototransistors have higher light gain and better or equivalent responsiveness and quantum efficiency, and have higher gain and signal-to-noise ratio and occupy a smaller area. By designing the spacing between the source and the drain of the high-energy phototransistor to be larger than the spacing between the source and the drain of the high-energy thin-film transistor, and designing the spacing between the source and the drain of the low-energy phototransistor to be larger than the spacing between the source and the drain of the low-energy thin-film transistor, the photosensitivity of the photosensitive area can be increased, the photosensitivity area can be increased, thereby improving the pixel resolution, and then realizing the preparation of a dual-energy flat-panel detector with higher resolution.

[0072] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent transformations made using the contents of the present invention's specification and drawings, or directly or indirectly applied in related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A dual-energy flat panel detector structure, comprising a first scintillator layer, wherein a ray filtering layer, a transparent substrate, a photoelectric sensor array layer and a second scintillator layer are sequentially stacked on one side of the first scintillator layer, wherein the photoelectric sensor array layer comprises high-energy sensor units and low-energy sensor units that are alternately distributed, characterized in that: The structure of the photosensitive area of ​​the high-energy sensor unit is a high-energy photosensitive transistor with an opaque top gate and a transparent bottom gate, the structure of the photosensitive area of ​​the low-energy sensor unit is a low-energy photosensitive transistor with a transparent top gate and an opaque bottom gate, the structure of the switch area of ​​the high-energy sensor unit and the structure of the switch area of ​​the low-energy sensor unit are both thin-film transistors, and are respectively a high-energy thin-film transistor and a low-energy thin-film transistor, the spacing between the source and the drain of the high-energy photosensitive transistor is greater than the spacing between the source and the drain of the high-energy thin-film transistor, and the spacing between the source and the drain of the low-energy photosensitive transistor is greater than the spacing between the source and the drain of the low-energy thin-film transistor.

2. The dual-energy flat panel detector structure according to claim 1, characterized in that: The high-energy photosensitive transistor comprises a first high-energy insulating layer, the first high-energy insulating layer covers a side of the transparent substrate away from the ray filtering layer, and the side of the first high-energy insulating layer away from the transparent substrate is sequentially stacked with a high-energy active layer, a high-energy drain metal layer, a second high-energy insulating layer, a high-energy top gate metal layer and a third high-energy insulating layer; The high energy drain metal layer comprises a high energy electrode layer and a high energy drain layer, and the distance between the high energy electrode layer and the high energy drain layer is greater than the distance between the source and the drain of the high energy thin film transistor.

3. The dual-energy flat panel detector structure according to claim 2, characterized in that: The length of the high-energy top gate metal layer in a vertical cross section is greater than or equal to the distance between the high-energy source layer and the high-energy drain layer.

4. The dual-energy flat panel detector structure according to claim 2, characterized in that: The high energy top gate metal layer is located directly above the gap between the high energy source layer and the high energy drain layer.

5. The dual-energy flat panel detector structure according to claim 2, characterized in that: The distance between the high energy source layer and the high energy drain layer is in the range of 5 μm to 30 μm.

6. The dual-energy flat panel detector structure according to claim 1, characterized in that: The low-energy photosensitive transistor comprises a first low-energy insulating layer, the first low-energy insulating layer covers a side of a transparent substrate away from the ray filtering layer, a low-energy active layer, a low-energy drain metal layer, a second low-energy insulating layer and a third low-energy insulating layer are sequentially stacked on the side of the first low-energy insulating layer away from the transparent substrate, a low-energy bottom gate metal layer is further included between the first low-energy insulating layer and the transparent substrate, and the low-energy bottom gate metal layer is in contact with the first low-energy insulating layer and the transparent substrate respectively; The low-energy drain metal layer includes a low-energy electrode layer and a low-energy drain layer, and the distance between the low-energy electrode layer and the low-energy drain layer is greater than the distance between the source and the drain of the low-energy thin film transistor.

7. The dual-energy flat panel detector structure according to claim 6, characterized in that: The length of the low-energy bottom gate metal layer in a vertical cross section is greater than or equal to the distance between the low-energy source electrode layer and the low-energy drain electrode layer.

8. The dual-energy flat panel detector structure according to claim 6, characterized in that: The low-energy bottom gate metal layer is located directly below the gap between the low-energy source layer and the low-energy drain layer.

9. The dual-energy flat panel detector structure according to claim 6, characterized in that: The distance between the low energy electrode layer and the low energy drain electrode layer is in the range of 5 μm to 30 μm.

10. The dual-energy flat panel detector structure according to claim 1, characterized in that: The high-energy thin-film transistor includes a first switch insulating layer, which covers a side of a transparent substrate away from a radiation filtering layer. A switch active layer, a switch source and drain metal layer, a second switch insulating layer, a mask layer and a third switch insulating layer are sequentially stacked on the side of the first switch insulating layer away from the transparent substrate. A switch bottom gate metal layer is also provided between the first switch insulating layer and the transparent substrate, and the switch bottom gate metal layer is in contact with the first switch insulating layer and the transparent substrate respectively.

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