Semiconductor element and method for manufacturing the same

Abstract

This invention discloses a semiconductor device and a method for manufacturing the same, wherein the semiconductor device structure includes a substrate. A first gate insulating layer is disposed on the substrate. A second gate insulating layer is disposed on the substrate, is thicker than the first gate insulating layer, and is adjacent to the first gate insulating layer. A gate layer has a first portion of the gate on the first gate insulating layer and a second portion of the gate on the second gate insulating layer. A dielectric layer has an upper dielectric layer and a lower dielectric layer. The upper dielectric layer contacts the gate layer, and the lower dielectric layer contacts the substrate. A field plate layer is disposed on the dielectric layer and includes a depletion region, at least disposed on the lower dielectric layer.

Description

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor manufacturing technology, and in particular, to a structure of a semiconductor device and a method of manufacturing the same. BACKGROUND

[0002] With the multi-function of electronic products, the control circuit thereof needs to drive both high voltage elements operating at high voltage and low voltage elements operating at low voltage. In response to the operation of high voltage elements, high voltage transistors need to withstand high operating voltage, and thus the structure of the transistor needs to withstand high voltage, i.e. to increase the breakdown voltage thereof.

[0003] In response to high voltage transistors, such as a Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistor structure, a field plate is disposed to assist the control of the gate structure on the channel layer of the substrate.

[0004] Based on the high voltage operation mechanism, the boundary region between the drain region and the gate structure is generally prone to high electric field, causing the transistor to break down. It is known that increasing the insulation between the field plate and the substrate can slow down the generation of high electric field, and prevent the transistor from breaking down. However, the thickness of the insulation layer between the field plate and the substrate is not easy to increase the thickness of the insulation layer to increase the breakdown voltage under the manufacturing process compatible with the general manufacturing process.

[0005] The structure design of high voltage transistors still needs to be developed. SUMMARY

[0006] The present invention proposes a structure of a semiconductor device and a method of manufacturing the same. For a transistor structure including a field plate, a general compatible manufacturing process can be used to achieve an improved insulation capability between the field plate and the substrate in the drain region.

[0007] In an embodiment, the present invention provides a semiconductor device structure. The semiconductor device structure includes a substrate. A first gate insulation layer is disposed on the substrate. A second gate insulation layer is disposed on the substrate, thicker than and adjacent to the first gate insulation layer. A gate layer has a first portion of the gate on the first gate insulation layer and a second portion of the gate on the second gate insulation layer. A dielectric layer has an upper portion of the dielectric layer and a lower portion of the dielectric layer. The upper portion of the dielectric layer is in contact with the gate layer, and the lower portion of the dielectric layer is in contact with the substrate. A field plate layer is disposed on the dielectric layer and includes a depletion region disposed at least on the lower portion of the dielectric layer.

[0008] In one embodiment, for the semiconductor device structure, the field plate layer further comprises a doped polysilicon layer or a doped silicon layer on the depletion region.

[0009] In one embodiment, for the semiconductor device structure, the dielectric layer comprises an oxide, a nitride, or an oxide and a nitride.

[0010] In one embodiment, for the semiconductor device structure, the dielectric layer is a single layer.

[0011] In one embodiment, for the semiconductor device structure, the dielectric layer comprises: the upper dielectric layer; a vertical layer on the sidewall of the gate layer; and the lower dielectric layer on the substrate. The upper dielectric layer, the vertical layer, and the lower dielectric layer are connected together.

[0012] In one embodiment, for the semiconductor device structure, the upper dielectric layer and the vertical layer are nitride, and the lower dielectric layer comprises a nitride layer and an oxide layer.

[0013] In one embodiment, for the semiconductor device structure, the depletion region of the field plate layer provides an insulating capability to the dielectric layer.

[0014] In one embodiment, for the semiconductor device structure, the depletion region of the field plate layer is only on the lower dielectric layer.

[0015] In one embodiment, for the semiconductor device structure, the depletion region of the field plate layer covers on the lower dielectric layer and the lower dielectric layer.

[0016] In one embodiment, for the semiconductor device structure, the field plate layer and the gate layer are to be electrically connected to the same voltage source.

[0017] In one embodiment, the present application further provides a method for manufacturing a semiconductor device, comprising providing a substrate. Thereafter, forming adjacent first and second gate insulating layers on the substrate, wherein the second gate insulating layer is thicker than the first gate insulating layer. Forming a gate layer having a first portion of the gate on the first gate insulating layer and a second portion of the gate on the second gate insulating layer. Forming a dielectric layer having an upper dielectric layer and a lower dielectric layer, wherein the upper dielectric layer contacts the gate layer and the lower dielectric layer contacts the substrate. Forming a field plate layer on the dielectric layer, wherein the field plate layer comprises a depletion region disposed at least on the lower dielectric layer.

[0018] In one embodiment, for the method for manufacturing a semiconductor device, the field plate layer further comprises a doped polysilicon layer or a doped silicon layer on the depletion region.

[0019] In one embodiment, for the method of fabricating a semiconductor device, the dielectric layer comprises an oxide, a nitride, or an oxide and a nitride.

[0020] In one embodiment, for the method of fabricating a semiconductor device, the dielectric layer is a single layer.

[0021] In one embodiment, for the method of fabricating a semiconductor device, the dielectric layer formed comprises: the upper dielectric layer; a vertical layer on the sidewall of the gate layer; and the lower dielectric layer on the substrate. The upper dielectric layer, the vertical layer and the lower dielectric layer are connected together.

[0022] In one embodiment, for the method of fabricating a semiconductor device, an oxide layer is formed on the substrate, and a nitride layer is formed on the oxide layer, constituting the upper dielectric layer, the vertical layer and the lower dielectric layer.

[0023] In one embodiment, for the method of fabricating a semiconductor device, the depletion region of the field plate layer formed provides insulation capability to the dielectric layer.

[0024] In one embodiment, for the method of fabricating a semiconductor device, the depletion region of the field plate layer formed is only on the lower dielectric layer.

[0025] In one embodiment, for the method of fabricating a semiconductor device, the depletion region of the field plate layer formed covers the lower dielectric layer and the lower dielectric layer.

[0026] In one embodiment, for the method of fabricating a semiconductor device, the field plate layer formed and the gate layer are electrically connected to the same voltage source. BRIEF DESCRIPTION OF DRAWINGS

[0027] The accompanying drawings are included to provide a further understanding of the application, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the application and, together with the description, serve to explain the principles of the application.

[0028] Figure 1 is a schematic diagram of a cross-sectional structure of a semiconductor device explored in one embodiment;

[0029] Figure 2 is a schematic diagram of a cross-sectional structure of a semiconductor device in one embodiment;

[0030] Figure 3 is a schematic diagram of a cross-sectional structure of a semiconductor device in one embodiment; and

[0031] Figure 4 is a schematic diagram of a cross-sectional structure of a semiconductor device in one embodiment.

[0032] Explanation of icon numbers

[0033] 50:Substrate

[0034] 100: Gate structure

[0035] 102, 102a, 102b: Gate insulating layer

[0036] 104: Gate layer

[0037] 104a: First part gate

[0038] 104b: Second part of the gate

[0039] 106: Dielectric layer

[0040] 108: Field Slab Layer

[0041] 110: Spacer wall

[0042] 112: Area

[0043] 200: Dielectric layer

[0044] 200a: Upper dielectric layer

[0045] 200b: Vertical layer

[0046] 200c: Lower dielectric layer

[0047] 202: Doped layer

[0048] 204: Void Zone

[0049] 206: Field Slab Layer Detailed Implementation

[0050] This invention relates to semiconductor devices and methods for manufacturing the same. The semiconductor device is, for example, the structure of a high-voltage transistor. In one embodiment, the high-voltage transistor includes a field plate to assist in the operation of a gate structure to control a channel region in a substrate.

[0051] In one embodiment, the transistor structure can be achieved using a manufacturing process compatible with that of general components in other regions, which can improve the insulation between the field plate and the substrate in the drain region.

[0052] The following examples illustrate the present invention, but the invention is not limited to these examples. Suitable combinations of the examples are also permitted.

[0053] Figure 1 This is a schematic cross-sectional view of the semiconductor device being investigated according to one embodiment. See also... Figure 1This invention explores, for example, the performance of an LDMOS transistor. The gate structure 100 of the transistor is disposed on a substrate 50. The gate structure 100 includes a gate insulating layer 102 and a gate layer (G) 104. As is typical, the substrate 50 also contains some doped regions corresponding to the conductivity type, which are not described here. The doped regions of this invention are not limited to a specific structure. Regarding gate control, for the purpose of high-voltage operation, a field plate layer 108 is formed on the gate structure 100 at the drain end. The field plate 108 is above the gate structure 100 and the substrate 50 and is insulated by a dielectric layer 106. Additionally, spacer walls 110 are also formed, for example, on the sidewalls of the structure.

[0054] Field layer 108 and gate layer 104 are connected to the same gate voltage VG. A portion of field layer 108 is shown on substrate 50 to provide auxiliary control for the channel. The drain region of gate structure 100 is adjacent to field layer 108 and receives drain voltage VD. The source region of gate structure 100 receives source voltage VS.

[0055] The dielectric layer 106 provides insulation between the field plate layer 108 and the substrate 50. As explored in this invention, if the thickness of the dielectric layer 106 is insufficient, for example in the indicated region 112, it may generate an excessively high electric field, easily leading to breakdown. This invention explores... Figure 1 After the transistor structure is completed, the insulation capability between the field plate layer 108 and the substrate 50 is improved while being compatible with the manufacturing process of components in other regions.

[0056] Figure 2 This is a schematic cross-sectional view of a semiconductor device according to one embodiment. See also... Figure 2 In one embodiment, the overall gate insulating layer may include a first gate insulating layer 102 and a second gate insulating layer 102a. The first gate insulating layer 102 and the second gate insulating layer 102a are adjacent and disposed on the substrate 50. The thickness of the second gate insulating layer 102a is, for example, greater than the thickness of the first gate insulating layer 102.

[0057] A gate layer 104 is formed on a first gate insulating layer 102 and a second gate insulating layer 102a. The gate layer 104 has a first portion of gate 104a on the first gate insulating layer 102. The gate layer 104 also has a second portion of gate 104b on the second gate insulating layer 102a. Thus, the gate layer 104 achieves greater insulation capability with the substrate 50 near the drain terminal. The second gate insulating layer 102a may be, for example, a field oxide layer to obtain a larger thickness, but is not limited thereto.

[0058] In one embodiment, both the first gate insulating layer 102 and the second gate insulating layer 102a are, for example, oxides. In another embodiment, depending on a variation in the manufacturing process, the oxide dielectric layer 102b may also be formed on the substrate 50 first. The dielectric layer 102b serves as insulation between the substrate 50 and the subsequently formed field plate layer 206.

[0059] In one embodiment, dielectric layer 102b may be part of the overall dielectric layer 200. In one embodiment, dielectric layer 200 includes an upper dielectric layer 200a covering the gate layer 104, for example, covering the second portion of the gate 104b. Dielectric layer 200 also includes a lower dielectric layer 200c covering the substrate 50. Dielectric layer 200 also includes a vertical layer 200b on the sidewall of the gate layer 104, connecting the lower dielectric layer 200c and the upper dielectric layer 200a. As mentioned above, the lower dielectric layer 200c is included in the underlying dielectric layer 102b.

[0060] In one embodiment, the dielectric layer 200 is, for example, a nitride or an oxide, and an upper dielectric layer 200a, a vertical layer 200b, and a lower dielectric layer 200c can be formed together. The dielectric layer 102b can be formed first during the process of forming other components, but is not limited thereto.

[0061] In one embodiment, the upper dielectric layer 200a and the vertical layer 200b are nitride layers, while the lower dielectric layer 200c is a stack of oxides and nitrides.

[0062] In one embodiment, a field plate layer 206 is formed on the dielectric layer 200. It should be noted that the material of the field plate layer 206, in one embodiment, is formed as a doped layer 202, such as a doped silicon layer or a doped polysilicon layer, by means of deposition or epitaxial growth. Furthermore, depending on the doping process, a depletion region 204 can be formed in the field plate layer 206. The depletion region 204 can be, for example, an undoped region or close to undoped. The depletion region 204 provides insulation. Therefore, in practical effect, during the formation of the field plate layer 206, the depletion region 204 is formed by controlling the doping technique to substantially provide the function of an insulating layer. Thus, in one embodiment, the lower dielectric layer 200c of the dielectric layer 200 does not need to form an additional insulating layer to increase its thickness to achieve the insulating effect. The insulating effect can be provided by the depletion region 204 of the field plate layer 206. In practical effect, the depletion region 204 can provide an additional insulating layer.

[0063] The formation of the vacancy region 204 can be controlled or adjusted, for example, by using an implanting process. In one embodiment, when the vacancy region 204 is formed using an epitaxial growth process, the dopant can be controlled during the growth process. The formation of the vacancy region 204 is not limited to a specific method.

[0064] Figure 3 This is a schematic cross-sectional view of a semiconductor device according to one embodiment. See also... Figure 3 In one embodiment, the depletion region 204 may also be formed by completely covering the dielectric layer 200. The formation of the dielectric layer 200 is as described above and will not be described again.

[0065] Figure 4 This is a schematic cross-sectional view of a semiconductor device according to one embodiment. See also... Figure 4 In one embodiment, depending on the manufacturing process, the dielectric layer 200 can be a single-layer structure of the same material, wherein the lower dielectric layer 200c is, for example, an oxide or a nitride, rather than a stack of oxides and nitrides.

[0066] The dielectric layer 200 of the present invention can be formed compatiblely with the manufacturing process of components in other regions. At the thickness that the dielectric layer 200 can be formed, a depletion region 204 is also formed during the formation of the field plate layer 206, which can further provide a function equivalent to an insulating layer to improve the insulation capability at the drain terminal, thereby improving the breakdown voltage.

[0067] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device structure, comprising: Comprising: a substrate; a first gate insulating layer disposed on the substrate; a second gate insulating layer disposed on the substrate, thicker than the first gate insulating layer and adjacent to the first gate insulating layer; a gate layer having a first portion of the gate on the first gate insulating layer and a second portion of the gate on the second gate insulating layer; a dielectric layer having an upper dielectric layer in contact with the gate layer and a lower dielectric layer in contact with the substrate; and a field plate layer disposed on the dielectric layer and including a depletion region, wherein the depletion region is disposed at least on the lower dielectric layer, the field plate layer further including a doped polysilicon layer or a doped silicon layer on the depletion region, the depletion region being an undoped region or approaching an undoped level.

2. The semiconductor element structure according to claim 1, characterized by The dielectric layer includes an oxide, a nitride, or an oxide and a nitride.

3. The semiconductor element structure according to claim 1, characterized by The dielectric layer is a single layer.

4. The semiconductor element structure according to claim 1, characterized by The dielectric layer includes: the upper dielectric layer; a vertical layer on a sidewall of the gate layer; and the lower dielectric layer on the substrate, wherein the upper dielectric layer, the vertical layer, and the lower dielectric layer are connected together.

5. The semiconductor element structure according to claim 4, characterized by The upper dielectric layer and the vertical layer are a nitride, and the lower dielectric layer includes a nitride layer and an oxide layer.

6. The semiconductor element structure according to claim 1, characterized by The depletion region of the field plate layer provides an insulating capability to the dielectric layer.

7. The semiconductor element structure according to claim 1, characterized by The depletion region of the field plate layer is only on the lower dielectric layer.

8. The semiconductor element structure according to claim 1, characterized by The depletion region of the field plate layer covers the upper dielectric layer and the lower dielectric layer.

9. The semiconductor element structure according to claim 1, characterized by The field plate layer and the gate layer are to be electrically connected to the same voltage source.

10. A method of manufacturing a semiconductor element, characterized by, Comprising: providing a substrate; forming adjacent first and second gate insulating layers on the substrate, wherein the second gate insulating layer is thicker than the first gate insulating layer; forming a gate layer having a first portion of the gate on the first gate insulating layer and a second portion of the gate on the second gate insulating layer; forming a dielectric layer having an upper dielectric layer in contact with the gate layer and a lower dielectric layer in contact with the substrate; and forming a field plate layer on the dielectric layer, wherein the field plate layer includes a depletion region, wherein the depletion region is disposed at least on the lower dielectric layer, the field plate layer further including a doped polysilicon layer or a doped silicon layer on the depletion region, the depletion region being an undoped region or approaching an undoped level.

11. The method of manufacturing a semiconductor element according to claim 10, wherein The dielectric layer includes an oxide, a nitride, or an oxide and a nitride.

12. The method of manufacturing a semiconductor element according to claim 10, wherein The dielectric layer is a single layer.

13. The method of manufacturing a semiconductor element according to claim 10, wherein The formed dielectric layer includes: the upper dielectric layer; a vertical layer on a sidewall of the gate layer; and the lower dielectric layer on the substrate, wherein the upper dielectric layer, the vertical layer, and the lower dielectric layer are connected together.

14. The method of manufacturing a semiconductor element according to claim 13, wherein forming an oxide layer on the substrate, and forming a nitride layer on the oxide layer, constituting the upper dielectric layer, the vertical layer, and the lower dielectric layer.

15. The method of manufacturing a semiconductor element according to claim 10, wherein The depletion region of the formed field plate layer provides an insulating capability to the dielectric layer.

16. The method of manufacturing a semiconductor element according to claim 10, wherein The depletion region of the formed field plate layer is only on the lower dielectric layer.

17. The method of producing a semiconductor element according to claim 10, wherein The depletion region of the field plate layer formed covers the upper dielectric layer and the lower dielectric layer.

18. The method of producing a semiconductor element according to claim 10, wherein The field plate layer and the gate layer formed are electrically connected to the same voltage source.

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