An NLDMOS device integrated with an overvoltage protection diode

Abstract

The present invention discloses an NLDMOS device integrated with an overvoltage protection diode, which is applied to the field of semiconductor integrated circuit technology. It includes a P-type semiconductor substrate, in which a P-type heavily doped buried layer and an N-type heavily doped buried layer are provided from bottom to top, and an epitaxial layer is located at the top of the P-type semiconductor substrate; the deep N-well led out from the N-type heavily doped buried layer is located in the epitaxial layer; an N+ contact region for leading out the drain is provided on the surface of the deep N-well led out; an isolation shallow trench is provided between the deep N-well led out and the drain of the power switch transistor; the drain of the power switch transistor, the gate of the power switch transistor, the source of the power switch transistor and the back gate of the power switch transistor are all located in the epitaxial layer. The present invention forms a body surge protection diode built under the power switch transistor in the chip itself only by adding one process level, realizing an innovative solution for integrated protection of overvoltage stresses such as ESD and surge with high efficiency and low cost.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuits, and more particularly to an NLDMOS device integrated with an overvoltage protection diode. Background Art

[0002] High-voltage LDMOS (Laterally Diffused Metal Oxide Semiconductor) devices are the most important type of devices in the BCD (Bipolar-CMOS-DMOS) process, mainly used as high-voltage power switches, high-voltage drive transistors, etc., and are applied to high-voltage circuit modules in integrated circuits. Usually, according to different application bias conditions, LDMOS can be divided into low-side LDMOS (Low Side LDMOS), high-side LDMOS (High Side LDMOS), and fully isolated LDMOS (Fully isolated LDMOS), and there are also significant differences in device structures. Among them, the high-side LDMOS refers to an LDMOS device that includes an isolation structure with the same potential as the drain, and the source and back gate can be biased to a high potential. Therefore, the device needs to be fabricated in a deep N-well or an isolation structure surrounded by a deep N-well and an N-type buried layer. For the LDMOS breakdown voltage (BV: Breakdown Voltage), on-resistance (Rsp: Ron specified), and safe operating area (SOA: Safe Operation Area) are its most important performance parameters. At the rated operating voltage level, the higher the BV, the smaller the Rsp, and the larger the SOA, the better the performance of the LDMOS.

[0003] A typical application of the high-side N-type LDMOS is as a high-voltage power switch with low on-resistance. Its drain input terminal is connected to a high-voltage input. When the switch is turned on, since the output has a load, the potential of the high-side source will also float up to a high voltage following the drain. For example, in a load switch application, the drain of the high-side LDMOS serving as a power switch is short-circuited to the isolation potential as the high-voltage input terminal, and the source is short-circuited to the back gate as the output terminal. In many high-voltage interface applications, for the high-voltage switch input terminal, it is also required to have protection functions against relatively high surge overvoltage and ESD to cope with the damage to the switch transistor itself and the subsequent chips of the switch output caused by possible instantaneous pulses. An idea of an existing technology is to additionally add an overvoltage detection circuit module and a clamping and current-discharging NLDMOS transistor at the input terminal of the high-voltage switch NLDMOS, and use the overvoltage detection circuit module to control the turning on of the current-discharging NLDMOS transistor to achieve clamping and discharging the voltage overshoot or the energy of ESD, and realize the protection function for the internal switch transistor. Refer to Figure 1For example, publication number CN104009458A mentions adding an additional current-discharging power NLDMOS transistor on a chip, using multiple Zener diodes and resistors in series to achieve surge overvoltage detection, and controlling the conduction of the current-discharging power NLDMOS transistor to achieve the clamping of the voltage of the protected port to ground and the discharging of the surge current. In this prior art, due to the requirement of large current discharging capacity, a current-discharging power NLDMOS transistor with a very small on-resistance is needed, and generally the on-resistance is about several tens of milliohms, which requires a large additional area. The entire detection circuit and the current-discharging power transistor occupy more than one-third of the entire chip area, greatly increasing the chip area and cost and occupying the system board space.

[0004] Therefore, it is an urgent problem for those skilled in the art to propose an NLDMOS device integrated with an overvoltage protection diode without adding an additional surge detection circuit module and a surge clamping and discharging power MOS transistor. Summary of the Invention

[0005] In view of this, the present invention provides an NLDMOS device integrated with an overvoltage protection diode, in which a longitudinal overvoltage protection diode to ground is integrated under the high-side NLDMOS of the power switch transistor itself, realizing ESD and surge overvoltage self-protection and solving the problems of input surge overvoltage and ESD protection.

[0006] In order to achieve the above object, the present invention adopts the following technical solutions:

[0007] An NLDMOS device integrated with an overvoltage protection diode, comprising:

[0008] A P-type semiconductor substrate, in which a P-type heavily doped buried layer and an N-type heavily doped buried layer are provided from bottom to top, and an epitaxial layer is located at the top of the P-type semiconductor substrate; the deep N-well led out from the N-type heavily doped buried layer is located in the epitaxial layer; a drain N+ contact region is provided on the surface of the deep N-well led out; an isolation shallow trench is provided between the deep N-well led out and the drain of the power switch transistor;

[0009] The drain of the power switch transistor, the gate of the power switch transistor, the source of the power switch transistor and the back gate of the power switch transistor are all located in the epitaxial layer, and are sequentially arranged at one end of the isolation shallow trench far from the deep N-well led out to form a power switch transistor;

[0010] Wherein, the P-type heavily doped buried layer and the N-type heavily doped buried layer form a PN junction; the device is symmetrically arranged along the longitudinal axis.

[0011] Optionally, a back gold layer is provided at the bottom of the P-type semiconductor substrate as the lead-out of the P-type heavily doped buried layer.

[0012] Optionally, a P-type epitaxial buffer layer is provided on the surface of the P-type semiconductor substrate, and the P-type heavily doped buried layer and the N-type heavily doped buried layer are located inside the P-type epitaxial buffer layer.

[0013] Optionally, a plurality of finger-shaped parallel power switch tubes are provided in an isolation region formed by the N-type heavily doped buried layer and the lead-out deep N-well.

[0014] Optionally, a P-type back heavily doped region is provided at the bottom of the P-type semiconductor substrate and is then led out using a back gold layer.

[0015] Optionally, the shallow isolation trench adopts shallow trench isolation (STI) of a BCD process.

[0016] It can be seen from the above technical solution that compared with the prior art, the present invention provides an NLDMOS device with an integrated overvoltage protection diode: the present invention forms an internal surge protection diode built into the chip's own power switch tube by simply adding a P-type heavily doped buried layer, which saves the transient voltage suppression diode outside the chip, saves the system board area, and does not increase the chip's own area. It is a very efficient and low-cost integrated protection solution for overvoltage electrical stress such as ESD and surge, and is very suitable for application in current mobile terminal load switches, power management and other products that contain power switches. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0018] Figure 1 This is a diagram of the integrated surge protection structure of the prior art;

[0019] Figure 2 This is a diagram of the integrated surge protection structure proposed by the present invention;

[0020] Figure 3 This is a structural diagram of an NLDMOS device with an integrated overvoltage protection diode according to the present invention;

[0021] Figure 4 This is another structural diagram of an NLDMOS device with an integrated overvoltage protection diode according to the present invention;

[0022] Figure 5 A top view of an NLDMOS device structure with an integrated overvoltage protection diode according to the present invention;

[0023] Among them, 1 is a P-type semiconductor substrate, 2 is a P-type heavily doped buried layer, 3 is a P-type epitaxial buffer layer, 4 is an N-type heavily doped buried layer, 5 is an epitaxial layer, 6 is an extracted deep N well, 7 is an extracted drain N+ contact region, 8 is an isolation shallow trench, 9 is the drain of a power switch transistor, 10 is the gate of a power switch transistor, 11 is the source of a power switch transistor, 12 is the back gate of a power switch transistor, 13 is the back gold terminal, and 14 is a P-type back surface heavily doped region. Detailed implementation manners

[0024] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0025] Referring to Figure 1 As shown, it is an integrated surge protection structure in the prior art. An independent surge detection circuit C and a surge protection discharge tube D are added in front of the input pin, that is, the drain end, of the protected power switch transistor B. When an ESD or surge occurs in the system, the surge detection circuit will detect the ESD and surge overvoltage in the system, and turn on the surge discharge tube D near the clamping voltage to achieve voltage clamping and transient large current discharge.

[0026] Referring to Figure 2 As shown, it is an integrated surge protection architecture diagram proposed by the present invention. It does not require a surge detection circuit and an additional surge discharge tube. It adopts a method similar to an off-chip transient voltage diode, but its clamping protection diode E is parasitically formed in the high-side LDMOS (labeled B) of the power switch transistor itself to be protected, as shown within the dashed box. Its cathode is connected to the drain of the high-side NLDMOS of the protected power switch transistor, and its anode is directly connected to the substrate ground.

[0027] Referring to Figure 3 As shown, the present invention discloses an NLDMOS device integrated with an overvoltage protection diode, including:

[0028] A P-type semiconductor substrate 1, in which a P-type heavily doped buried layer 2 and an N-type heavily doped buried layer 4 are provided from bottom to top, and an epitaxial layer 5 is located on the top of the P-type semiconductor substrate 1; an extracted deep N well 6 of the N-type heavily doped buried layer 4 is located within the epitaxial layer 5; an extracted drain N+ contact region 7 is provided on the surface of the extracted deep N well 6; an isolation shallow trench 8 is provided between the extracted deep N well 6 and the drain 9 of the power switch transistor;

[0029] The drain 9 of the power switch transistor, the gate 10 of the power switch transistor, the source 11 of the power switch transistor, and the back gate 12 of the power switch transistor are all located in the epitaxial layer 5, and are sequentially arranged at one end of the isolation shallow trench 8 away from the lead-out deep N-well 6, forming a power switch transistor;

[0030] Among them, the P-type heavily doped buried layer 2 and the N-type heavily doped buried layer 4 form a PN junction; the device is symmetrically arranged along the longitudinal axis.

[0031] In a specific embodiment, the surface of the P-type semiconductor substrate 1 has a P-type epitaxial buffer layer 3, and the P-type heavily doped buried layer 2 and the N-type heavily doped buried layer 4 are located inside the P-type epitaxial buffer layer 3;

[0032] A back gold layer 13 is provided at the bottom of the P-type semiconductor substrate 1 as the lead-out of the P-type heavily doped buried layer 2; the P-type semiconductor substrate 1 can be a P-type heavily doped semiconductor substrate 1.

[0033] In a specific embodiment, the heavily doped substrate is set to have a doping concentration less than or equal to 0.1 ohm*cm.

[0034] In a specific embodiment, a P-type back heavily doped region 14 that forms an ohmic contact with the back gold layer 13 is provided at the bottom of the P-type semiconductor substrate 1, and then led out by the back gold layer 13. The P-type semiconductor substrate 1 can be a P-type moderately doped semiconductor substrate 1.

[0035] In a specific embodiment, the moderately doped substrate is set to have a doping concentration between 0.1 ohm*cm and 10 ohm*cm.

[0036] In a specific embodiment, multiple finger-shaped parallel power switch transistors are provided in the isolation region formed by the N-type heavily doped buried layer 4 and the lead-out deep N-well 6, including: the drain 9 of the power switch transistor, the gate 10 of the power switch transistor, the source 11 of the power switch transistor, and the back gate 12 of the power switch transistor, that is, the body region.

[0037] Multiple finger-shaped parallel NLDMOS power switch transistors are provided in the isolation region formed by the N-type heavily doped buried layer 4 and the lead-out deep N-well 6. The entire switch transistor is composed of multiple such isolated power switch transistor modules in parallel. The grid-shaped lead-out deep N-well 6 forms the cathode lead-out at the top of the overvoltage protection diode.

[0038] In a specific embodiment, the P-type semiconductor substrate 1 is a P-type heavily doped substrate or a P-type non-heavily doped substrate; the isolation shallow trench 8 adopts the shallow trench isolation STI of the BCD process.

[0039] In a specific embodiment, the P-type heavily doped buried layer 2 and the N-type heavily doped buried layer 4 form the breakdown voltage of the integrated overvoltage protection diode PN junction, which can be changed by adjusting the parameters of the P-type heavily doped buried layer 2, and is set between the highest operating voltage and the breakdown voltage of the NLDMOS itself.

[0040] Referring to Figure 5 as shown, for Figure 3 and Figure 4 the top surface top view, the P-type heavily doped buried layer 2 pattern is nested inside the N-type heavily doped buried layer 4. Since the large current switching transistors in the process usually adopt a unitized pattern, the 3x3 parallel device units are used for description in the figure. The active region of the NLDMOS device in each unit is the part surrounded by the dashed line marked 54. Each unit is surrounded by the annular region marked 53, and its composition is a deep N-well combined with other N-doped wells and N+ active regions. The mark 51 in the figure is the boundary of the N-type buried layer square pattern of the high-side NLDMOS switch transistor. The entire N-type buried layer is led out from the silicon surface by 53 as the cathode, and 52 is the PUBL pattern boundary proposed in this patent. In order to reduce the influence of the PN junction boundary effect between the PUBL and the NBL on the breakdown voltage, the size d of the NBL pattern boundary surrounding the PUBL pattern boundary is set to ≥1um.

[0041] The solution of the present invention is based on the high-side power switch transistor that requires surge protection on the chip itself. A P-type doped buried layer PUBL (P Under Bury Layer) is formed under the NBL of the high-side power switch device NLDMOS. The PUBL is directly connected to the ground through the substrate, thereby forming a surge protection diode with the anode being the PUBL and the cathode being the NBL. The PUBL adjusts the breakdown voltage from the NBL to the substrate ground by changing the implanted doping concentration, thereby forming protection for the drain terminal of the high-side LDMOS, and a longitudinal NBL / PUBL overvoltage protection diode that does not occupy additional silicon surface area. The above concept is the main innovative idea of this patent.

[0042] Specifically elaborate on the main implementation methods in the present invention:

[0043] 1. In terms of device structure, based on the high-side NLDMOS device including the N-type buried layer NBL, a P-type heavily doped PUBL layer is formed under the NBL pattern of the NLDMOS, thus forming a clamping protection diode of a PN junction with the NBL as the cathode and the PUBL as the anode and directly connected to the substrate ground, achieving the ESD and surge overvoltage protection effects on the drain of the high-side NLDMOS, that is, the high-voltage input terminal to the substrate ground loop. This is the main innovation point of this patent.

[0044] 2. The main parameter characteristics of the NBL / PUBL clamping overvoltage protection diode: 1) The breakdown voltage BV of the overvoltage protection diode is set to be more than 5% higher than the highest operating voltage of the protected pin; 2) If the breakdown voltage from the drain of the high-side LDMOS to the ground without adding the PUBL is defined as the intrinsic breakdown voltage Vint, then the breakdown voltage of the NBL / PUBL diode is lower than the intrinsic breakdown voltage Vint.

[0045] 3. A preferred implementation is to form a PUBL layer on a P-type epitaxial buffer layer on a P-type heavily doped low-resistance substrate; it is formed by doping through an implantation process and annealing and driving, and then the epitaxial growth of the NBL and device layers is carried out. A PUBL / NBL PN junction is formed. Among them, the resistivity of a typical P-type heavily doped substrate is ≤0.1 Ω·cm, and the resistivity of the P-type epitaxial buffer layer is between 5 and 20 Ω·cm.

[0046] 4. Another implementation is on a P-type medium-resistance substrate in a common BCD process. The resistivity of this medium-resistance substrate is between 6 and 20 Ω·cm. Inject and anneal and drive to form a heavily doped P-type well. The N-type buried layer is doped by injecting in the PUBL pattern area, thermally driven, and then the epitaxial layer where the device is located is grown, and at the same time, the NBL / PUBL PN junction interface is formed.

[0047] 5. For the PUBL / NBL clamping diode formed by the BCD process on a P-type heavily doped substrate, the PUBL is generally led out by thinning the heavily doped P-type substrate and then forming a back gold lead on the back, such as a typical Ti / Ni / Ag. Or if it is a P-type substrate with medium-resistance doping, it can be led out by back P-type heavy doping and then back gold. When the PUBL is led out from the back, the thickness of the silicon wafer after thinning is between 80 μm and 280 μm.

[0048] 6. The PUBL is doped with B, and the doping method can be the commonly used method of thermal driving after implantation, or the method of thermal diffusion after spin-coating boron silicate glass. The doping conditions are determined by the breakdown voltage setting of the device, and can be conveniently adjusted by the implantation dose or the thickness of the boron silicate glass, and the thermal driving conditions.

[0049] 7. The PUBL pattern feature is nested inside the N-row buried layer NBL pattern, and can be formed by shrinking each side of the entire N-type buried layer NBL pattern of the high-side LDMOS device by ≥1 μm or more.

[0050] The present invention does not require additional chip area. By increasing the implantation level, a parasitic surge clamping protection diode is formed within the body of the chip's power switch device itself. It is particularly suitable for chips with a relatively large area of the chip's own power switch. This parasitic surge clamping diode can also achieve very considerable system ESD and overvoltage surge protection functions. The technical solution proposed by the present invention forms an in-body surge protection diode built under the chip's own power switch only by adding one process level. It not only saves the transient voltage suppression diode outside the chip and saves the system board area, but also does not increase the chip's own area. It is a very high-efficiency and low-cost innovative solution for integrated protection against overvoltage stresses such as ESD and surges, and is very suitable for applications in current mobile terminal load switches, power management, and other products containing power switches.

[0051] The above description of the disclosed embodiments is presented in a progressive manner so that those skilled in the art can implement or use the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. An NLDMOS device integrated with an overvoltage protection diode, characterized in that, Including: A P-type semiconductor substrate (1), in which a P-type heavily doped buried layer (2) and an N-type heavily doped buried layer (4) are provided from bottom to top, and an epitaxial layer (5) is located on the top of the P-type semiconductor substrate (1); a deep N-well (6) led out from the N-type heavily doped buried layer (4) is located in the epitaxial layer (5); a drain N+ contact region (7) is provided on the surface of the deep N-well (6) led out; an isolation shallow trench (8) is provided between the deep N-well (6) led out and the drain of the power switch transistor (9); The drain of the power switch transistor (9), the gate of the power switch transistor (10), the source of the power switch transistor (11) and the back gate of the power switch transistor (12) are all located in the epitaxial layer (5), and are sequentially arranged at one end of the isolation shallow trench (8) away from the deep N-well (6) led out, forming a power switch transistor; Wherein, the P-type heavily doped buried layer (2) and the N-type heavily doped buried layer (4) form a PN junction; the device is symmetrically arranged along the longitudinal axis.

2. The NLDMOS device with an integrated overvoltage protection diode according to claim 1, wherein, A back gold layer (13) is provided at the bottom of the P-type semiconductor substrate (1) as an extraction of the P-type heavily doped buried layer (2).

3. The NLDMOS device with an integrated overvoltage protection diode according to claim 2, wherein, The surface of the P-type semiconductor substrate (1) has a P-type epitaxial buffer layer (3), and the P-type heavily doped buried layer (2) and the N-type heavily doped buried layer (4) are located inside the P-type epitaxial buffer layer (3).

4. The NLDMOS device with an integrated overvoltage protection diode according to claim 1, wherein, Multiple finger-shaped parallel power switch transistors are provided in the isolation region formed by the N-type heavily doped buried layer (4) and the deep N-well (6) led out.

5. The NLDMOS device with an integrated overvoltage protection diode according to claim 1, wherein, A P-type back surface heavily doped region (14) is provided at the bottom of the P-type semiconductor substrate (1), and is then extracted by the back gold layer (13).

6. The NLDMOS device with an integrated overvoltage protection diode according to claim 1, wherein, The isolation shallow trench (8) adopts a shallow trench isolation STI of the BCD process.

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