Farrow filter based on FPGA and implementation method thereof

Abstract

The application aims to provide a Farrow filter design based on FPGA. The design adopts a filter coefficient solving method based on a symmetric structure, and the filter coefficients of the final Farrow filter are obtained through weighting optimization. The digital delay filter adopting the design can adaptively adjust the delay amount without changing the filter coefficients, and has good flexibility. Meanwhile, the method fully utilizes the symmetric structure, can effectively save the multiplier resources of the FPGA, and has engineering implementation value especially when multiple delay results are needed at the same time.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of radar signal processing, and particularly relates to a Farrow filter and an implementation method thereof. BACKGROUND

[0002] The Farrow filter is a fractional time delay filter with continuous variable time delay, and the structure of the filter is proposed by Farrow CW in 1988, and is initially used to solve the fractional time delay problem in sonar.

[0003] Although the common digital delay filter has a simple structure, the coefficient calculation process is complex, and when the delay parameter changes rapidly, the coefficient update speed cannot meet the real-time requirement, which is limited in engineering application. The Farrow structure digital delay filter can more flexibly and efficiently perform fractional delay filtering, and when the delay parameter changes, the filter coefficients do not need to be recalculated, and it is easier to realize on a field programmable gate array (FPGA).

[0004] In the FPGA implementation process of signal processing, a large amount of multiplication resources are often consumed, so that the multiplier resources of the FPGA become the system bottleneck, and the design introduces a Farrow filter design method based on FPGA. The method adopts a symmetric structure filter solving method, fully utilizes the multiplication resources, and efficiently realizes the Farrow filter function. SUMMARY

[0005] The purpose of the application is to propose a Farrow filter design based on FPGA. The design proposes a filter coefficient solving method based on symmetric structure, and obtains the final Farrow filter coefficients through weighting optimization; the digital delay filter adopting the design can adaptively adjust the delay amount, without replacing the filter coefficients, and has good flexibility. At the same time, the method fully utilizes the symmetric structure, can effectively save the multiplier resources of the FPGA, and has engineering implementation value especially when multiple delay results are needed at the same time.

[0006] A Farrow filter based on FPGA, the filter is M groups of N-order FIR sub-filters, and can complete the digital delay function of any T delay amount.

[0007] Comprise:

[0008] 1 set of Farrow filter coefficients, the coefficients can be solved by a Farrow filter coefficient calculation method, the coefficients should meet the M group N-order Farrow filter parameters, and should meet the symmetric characteristic.

[0009] M groups of FIR sub-filter modules, each group of modules contains N order multipliers, especially coefficient symmetry, engineering implementation can use symmetric structure of FIR structure, save two pairs of multiplier resources.

[0010] The actual delay amount p1, p2, … is provided by an external delay parameter.

[0011] The Farrow filter structure has the following advantages: the sub-filter coefficients a mn are independent of the fractional delay amount p, when the delay amount p changes, the sub-filter coefficients a mn do not need to be updated, nor do they need to store a large number of coefficients, and when there are multiple delay amounts p1, p2, … p B need to be compensated at the same time, only the B group of delay multipliers need to be increased, and the FIR sub-filter structure does not need to be changed.

[0012] The Farrow filter coefficient calculation method is as follows:

[0013] As Figure 1 , the transfer function of the Farrow filter can be expressed as:

[0014]

[0015] In the formula, p ∈ [-0.5, 0.5]

[0016] The frequency response function of the ideal delay filter can be expressed as:

[0017] H id (ω, p) = e -jωp

[0018] Using the frequency-weighted least squares method to approximate the ideal value, the objective function is:

[0019]

[0020] In the formula: W1(ω) and W2(p) are variable window functions, and the derivative of J4 is equal to 0, that is, the Farrow filter coefficients a mn can be solved.

[0021] Let:

[0022] p = [1, p, p 2 ……, p M ] T ,

[0023] e = [1, e -jω , e -j2ω ……, e -jNω ] T ,

[0024] q = [cos[ω(p + N1)], cos[ω(p + N1 - 1)] …, cos[ω(p - N2)] T

[0025] Available filter coefficients:

[0026]

[0027] Wherein:

[0028]

[0029]

[0030]

[0031] Wherein, the transfer function H(ω, p) of the Farrow filter can be regarded as the weighted sum of M sub-filters multiplied by the fractional delay p, so the Farrow filter structure can be divided into M groups of N-order FIR sub-filters and M fractional delay multipliers.

[0032] For example, as Figure 2 , M groups of 2N+1-order FIR sub-filters are taken as an example, a Farrow filter design based on FPGA is designed, which can realize real-time digital delay processing of multiple arbitrary delay parameters, and effectively save multiplier resources when aiming at symmetric coefficients.

[0033] A Farrow filter implementation method based on FPGA, the specific steps are:

[0034] Step 1, calculate the symmetric Farrow filter coefficients according to the Farrow filter coefficient calculation method, and write into the FPGA program design in advance;

[0035] The Farrow filter coefficient calculation method is as follows:

[0036] The transfer coefficient of the Farrow filter can be expressed as:

[0037]

[0038] In the formula, p ∈ [-0.5, 0.5]

[0039] The frequency response function of the ideal delay filter can be expressed as:

[0040] H id (ω, p) = e -jωp

[0041] The frequency weighted least squares method is used to approximate the ideal value, and the objective function is:

[0042]

[0043] In the formula: W1 (ω) and W2 (p) are variable window functions, the Farrow filter coefficient a is obtained by deriving J4 and making it equal to 0 mn .

[0044] Let:

[0045] p = [1, p, p 2 ……, p M ] T ,

[0046] e = [1, e -jω , e -j2ω ……, e -jNω ] T ,

[0047] q = [cos [ω (p + N1)], cos [ω (p + N1-1)] … …, cos [ω (p - N2)] T

[0048] The filter coefficient can be obtained:

[0049]

[0050] Wherein:

[0051]

[0052]

[0053]

[0054] Wherein, the transfer function H (ω, p) of the Farrow filter can be regarded as the weighted multiplication and summation of M sub-filters with the fractional delay amount p, so that the Farrow filter structure can be divided into M groups of N-order FIR sub-filters and M fractional delay multipliers.

[0055] Step 2, the input signal flows into the M group Farrow sub-filter group module in turn, and each N-order FIR filter in each group completes the respective filtering processing;

[0056] Step 3, four multiplication and addition modules will complete the multiplication and addition operation of each sub-filter group according to the actual delay amount.

[0057] Step 4, four digital delay results are obtained.

[0058] The beneficial effects of the present application are:

[0059] Strong universality: the present application can support a variety of bandwidth signals and complete digital delay of any delay parameter;

[0060] Strong operability: the application does not need to update the filter tap coefficient in real time, and has strong operability;

[0061] Save multiplication resources: the application makes full use of the characteristics of symmetric coefficients to save the multiplier resources of FPGA. BRIEF DESCRIPTION OF DRAWINGS

[0062] Figure 1 Farrow filter structure

[0063] Figure 2 FPGA-based Farrow filter design DETAILED DESCRIPTION

[0064] The technical solutions provided by the application will be described in detail below in combination with specific embodiments, and it should be understood that the following specific embodiments are only used to illustrate the application and not to limit the scope of the application.

[0065] A FPGA-based Farrow filter is composed of M groups of N-order FIR sub-filters, which can complete the digital delay function of any T delay amount. For convenience of description, the following takes a 4-group 4-order Farrow filter design (with upward compatibility and expansion function) that needs to complete 4 delay amounts at the same time as an example for description, including:

[0066] 1 set of Farrow filter coefficients, which can be solved by the transfer coefficient calculation formula of the Farrow filter, and the coefficients should meet the parameters of the 4-group 4-order Farrow filter, which should meet the symmetry characteristic.

[0067] 4 groups of FIR sub-filter modules, each group of modules contains 4-order multipliers, especially symmetric coefficients, and the FIR structure with symmetric structure can be used in engineering implementation to save two pairs of multiplier resources.

[0068] The actual delay amount p1, p2, p3, p4 is provided by an external delay parameter.

[0069] The transfer coefficient of the Farrow filter can be expressed as:

[0070]

[0071] In the formula, p∈[-0.5, 0.5]

[0072] The ideal delay filter frequency response function can be expressed as:

[0073] H id (ω, p)=e -jωp

[0074] The ideal value is approximated by using the frequency-weighted least square method, and the objective function is:

[0075]

[0076] In the formula, W1(ω) and W2(p) are variable window functions, and the Farrow filter coefficient a can be obtained by deriving J4 and setting it equal to 0 mn .

[0077] Let:

[0078] p = [1, p, p 2 ... , p M ] T ,

[0079] e = [1, e -jω , e -j2ω ... , e -jNω ] T ,

[0080] q = [cos[ω(p+N1)], cos[ω(p+N1-1)]... , cos[ω(p-N2)] T

[0081] The filter coefficient can be obtained:

[0082]

[0083] Wherein:

[0084]

[0085]

[0086]

[0087] Wherein, the transfer function H(ω, p) of the Farrow filter can be regarded as the weighted multiplication and summation of M sub-filters by the fractional delay amount p, so the Farrow filter structure can be divided into M groups of N-order FIR sub-filters and M fractional delay multipliers.

[0088] A Farrow filter implementation method based on FPGA, the steps are as follows:

[0089] Step 1, calculate the symmetric Farrow filter coefficient according to the formula, and write it into the FPGA program in advance;

[0090] The transfer coefficient of the Farrow filter can be expressed as:

[0091]

[0092] In the formula, p ∈ [-0.5, 0.5]

[0093] The ideal delay filter frequency response function can be expressed as:

[0094] H id (ω, p) = e -jωp

[0095] The ideal value is approximated by using frequency weighted least square method, and the objective function is:

[0096]

[0097] In the formula, W1(ω) and W2(p) are variable window functions, and the Farrow filter coefficients a mn .

[0098] Let:

[0099] p = [1, p, p 2 ... , p M ] T ,

[0100] e = [1, e -jω , e -j2ω ... , e -jNω ] T ,

[0101] q = [cos[ω(p+N1)], cos[ω(p+N1-1)]... , cos[ω(p-N2)] T

[0102] The filter coefficients are obtained:

[0103]

[0104] Wherein:

[0105]

[0106]

[0107]

[0108] Wherein, the transfer function H(ω, p) of the Farrow filter can be regarded as the weighted sum of M sub-filters multiplied by the fractional delay p, so the Farrow filter structure can be divided into M groups of N-order FIR sub-filters and M fractional delay multipliers.

[0109] Step 2, the input signal flows into 4 groups of Farrow sub-filter group modules in turn, and each group of 4-order FIR filters completes its own filtering processing;

[0110] Step 3, four multiplication-addition modules will complete multiplication-addition operation of each sub-filter group according to actual delay amount respectively;

[0111] Step 4, final four digital delay results are obtained.

[0112] The above description is only the best specific embodiment of the present application, but the protection scope of the present application is not limited to this, any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the present application.

[0113] The contents not described in detail in the specification of the present application belong to the known technology of the person skilled in the art.

Claims

1. A Farrow filter based on FPGA, characterized in that, This filter is an M-group, N-order FIR sub-filter capable of performing digital delay functions for any T delay amounts, including: One set of Farrow filter coefficients, which can be solved by the Farrow filter coefficient calculation method, should satisfy M sets of Nth-order Farrow filter parameters and should conform to symmetry characteristics; M groups of FIR sub-filter modules, each group containing an Nth-order multiplier, with particularly symmetrical coefficients. In engineering implementation, a symmetrical FIR structure can be adopted, saving two pairs of multiplier resources. The actual delay values ​​p1, p2, ... are provided by external delay parameters. In the Farrow filter, the sub-filter coefficients a mn Independent of the fractional delay p, the sub-filter coefficients a change as the delay p changes. mn No updates are needed, nor is it necessary to store a large number of coefficients, and when there are multiple delay values ​​p1, p2, ... p B When simultaneous compensation is required, only a B-group delay multiplier needs to be added, and the FIR sub-filter structure does not need to be changed. The transfer coefficients of the Farrow filter can be expressed as: In the formula, p∈[-0.5,0.5] The frequency response function of an ideal delay filter can be expressed as: H id (ω,p)=e -jωp The objective function for approximating the ideal value using the frequency-weighted least squares method is: In the formula: W1(ω) and W2(p) are variable window functions. Taking the derivative of J4 and setting it equal to 0, the Farrow filter coefficients a can be obtained. mn ; make: p=[1,p,p2……,p M ] T , and=[1,e -jω ,And -j2ω ……,And -jNω ] T , q=[cos[ω(p+N1)],cos[ω(p+N1-1)]……,cos[ω(p-N2)] T The filter coefficients can be obtained as follows: in: The transfer function H(ω,p) of the Farrow filter can be regarded as a weighted sum of fractional delay p multiplied by M sub-filters. Therefore, the Farrow filter structure can be decomposed into M groups of N-order FIR sub-filters and M fractional delay multipliers.

2. A method for implementing a Farrow filter based on FPGA, characterized in that, The steps of this method are as follows: Step 1: Calculate the coefficients of the symmetrical Farrow filter according to the Farrow filter coefficient calculation method, and write them into the FPGA program design in advance; Step 2: The input signals flow into the M groups of Farrow sub-filter modules, where each N-order FIR filter completes its own filtering process. Steps 3 and 4 will perform multiplication and addition operations on each sub-filter bank for each delay amount according to the actual delay amount; Step 4: Obtain the final four digital delay results; The transfer coefficients of the Farrow filter can be expressed as: In the formula, p∈[-0.5,0.5] The frequency response function of an ideal delay filter can be expressed as: H id (ω,p)=e -jωp The objective function for approximating the ideal value using the frequency-weighted least squares method is: In the formula: W1(ω) and W2(p) are variable window functions. Taking the derivative of J4 and setting it equal to 0, the Farrow filter coefficients a can be obtained. mn ; make: p=[1,p,p 2 ……,p M ] T , and=[1,e -jω ,And -j2ω ……,And -jNω ] T , q=[cos[ω(p+N1)],cos[ω(p+N1-1)]……,cos[ω(p-N2)] T The filter coefficients can be obtained as follows: in: The transfer function H(ω,p) of the Farrow filter can be regarded as a weighted sum of fractional delay p multiplied by M sub-filters. Therefore, the Farrow filter structure can be decomposed into M groups of N-order FIR sub-filters and M fractional delay multipliers.

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