Forming a self-aligned top via at the online end

Abstract

A method for manufacturing a semiconductor device includes: recessing a first odd hard mask and a first even hard mask to form recessed odd and even hard masks; forming a first conductive hard mask on the recessed odd hard mask, the first conductive hard mask including a first conductive hard mask material, and forming a second conductive hard mask on the recessed even hard mask; and forming self-aligned vias at line ends corresponding to first odd and even wires at least partially based on the first conductive hard mask and the second conductive hard mask.

Description

BACKGROUND OF THE INVENTION

[0001] The present invention generally relates to semiconductor devices, and more particularly to semiconductor devices including wires and vias and methods of forming the same.

[0002] Lithographic alignment of vias and wires can occur through a thick, opaque conductive film (e.g., a metal film). At small dimensions, overlap and alignment errors can have a large impact on via contact resistance and dielectric barrier resistance. Critical dimension (CD) variations can introduce additional overlay and alignment fluctuations. Limited coverage offsets can cause the via to move away from the wire end or be cut off by the wire end, resulting in a reduction in via CD. SUMMARY OF THE INVENTION

[0003] According to an embodiment of the present invention, a method for manufacturing a semiconductor device is provided. The method includes: recessing a first odd hard mask and a first even hard mask to form recessed odd and even hard masks; forming a first conductive hard mask on the recessed odd hard mask, the first conductive hard mask including a first conductive hard mask material, and forming a second conductive hard mask on the recessed even hard mask; and forming a self-aligned top via at a wire end corresponding to the first odd and even wires, at least in part based on the first conductive hard mask and the second conductive hard mask.

[0004] According to another embodiment of the present invention, a method for manufacturing a semiconductor device is provided. The method includes recessing a first odd hard mask and a first even hard mask to form recessed odd and even hard masks. The first odd hard mask is formed to include a different material than the first even hard mask to support selective etching of the first odd and even hard masks. The method further includes: forming a first conductive hard mask on the recessed odd hard mask and forming a second conductive hard mask on the recessed even hard mask, the first conductive hard mask including a first conductive hard mask material. The first and second conductive hard masks are formed to have a semi-circular cross-sectional shape along the direction of the first odd and even wires. The method further includes forming a self-aligned top via at a wire end corresponding to the first odd and even wires, at least in part based on the first and second conductive hard masks.

[0005] According to yet another embodiment of the present invention, a method for manufacturing a semiconductor device is provided. The method includes forming a first odd hard mask on a first odd wire and a first even hard mask on a first even wire. The first odd hard mask is formed to include a material different from that of the first even hard mask to support selective etching of the first odd and even hard masks. The method further includes: forming a first dielectric layer on sidewalls of the first odd and even hard masks and the first odd and even wires; forming a first cut region corresponding to the first even wire; and forming a second cut region corresponding to the first odd wire, recessing the first odd hard mask and the first even hard mask to form recessed odd and even hard masks; replacing the first dielectric layer with a corresponding replacement layer; and forming a first conductive hard mask including a first conductive hard mask material on the recessed odd hard mask and a second conductive hard mask on the recessed even hard mask. The first conductive hard mask and the second conductive hard mask are formed to have a semi-circular cross-sectional shape along the direction of the first odd and even wires. The method further includes forming self-aligned top vias at least partially based on the first and second conductive hard masks at wire ends corresponding to the first odd and even wires.

[0006] According to yet another additional embodiment of the present invention, a method for manufacturing a semiconductor device is provided. The method includes forming a first odd hard mask on a first odd wire and forming a first even hard mask on a first even wire. The first odd hard mask is formed to include a material different from the first even hard mask to support selective etching of the first odd and even hard masks. The method further includes: forming a first dielectric layer on sidewalls of the first odd and even hard masks and the first odd and even wires; forming a first cutting region corresponding to the first even wire; and forming a second cutting region corresponding to the first odd wire, forming a first sacrificial layer in the first cutting region and forming a second sacrificial layer in the second cutting region, recessing the first odd hard mask and the first even hard mask to form a recessed odd hard mask and an even hard mask, replacing the first dielectric layer with a corresponding replacement layer; and forming a first conductive hard mask including a first conductive hard mask material on the recessed odd hard mask and forming a second conductive hard mask on the recessed even hard mask. The first conductive hard mask and the second conductive hard mask are formed to have a semi-circular cross-sectional shape along the direction of the first odd and even wires. The method further includes: forming an additional hard mask material on the recessed odd and even hard masks and the first and second conductive hard masks; performing a planarization process after forming the additional hard mask material; forming third and fourth conductive hard masks based on non-line end via patterning after the planarization process; forming self-aligned top vias at least partially based on the first and second conductive hard masks at line ends corresponding to the first odd and even wires; and performing additional processing. Performing the additional processing includes: removing the first and second sacrificial layers to form an opening between the self-aligned top vias; forming a second dielectric layer in the opening; and replacing the replacement layer with a third dielectric layer.

[0007] According to an embodiment of the present invention, a semiconductor device is provided. The device includes: at least one odd wire and at least one even wire; self-aligned top vias, each self-aligned top via being disposed at a line end corresponding to the odd and even wires; and dielectric layers, the dielectric layers being respectively disposed between adjacent self-aligned top vias among the self-aligned top vias.

[0008] These and other features and advantages will become apparent from the following detailed description of its illustrative embodiments read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The following description will provide details of the preferred embodiments with reference to the following drawings, wherein:

[0010] Figure 1 is a top view of forming a hard mask on a wire during manufacturing of a semiconductor device according to an embodiment of the present invention;

[0011] Figure 2 is a cross-sectional view of an odd-numbered wire of the odd-numbered wire region of the device shown by Figure 1 ;

[0012] Figure 3 is a cross-sectional view of an even-numbered wire of the even-numbered wire region of the device shown by Figure 1 ;

[0013] Figure 4 is a top view of forming a first cutting region corresponding to the even-numbered wires during the manufacture of a semiconductor device according to an embodiment of the present invention;

[0014] Figure 5 is a cross-sectional view of an odd-numbered wire of the device shown by Figure 3 ;

[0015] Figure 6 is a cross-sectional view of an even-numbered wire of the device shown by Figure 3 ;

[0016] Figure 7 is a top view of forming a second cutting region corresponding to the odd-numbered wires during the manufacture of a semiconductor device according to an embodiment of the present invention;

[0017] Figure 8 is a cross-sectional view of an odd-numbered wire of the device shown by Figure 7 ;

[0018] Figure 9 is a cross-sectional view of an even-numbered wire of the device shown by Figure 7 ;

[0019] Figure 10 is a cross-sectional view of forming a sacrificial material in the first cutting region according to an embodiment of the present invention;

[0020] Figure 11 is a cross-sectional view of forming a sacrificial material in the second cutting region according to an embodiment of the present invention;

[0021] Figure 12 is a cross-sectional view of forming a conductive hard mask on the material formed in the first cutting region according to an embodiment of the present invention;

[0022] Figure 13 is a cross-sectional view of forming a conductive hard mask on the material formed in the second cutting region according to an embodiment of the present invention;

[0023] Figure 14A cross-sectional view of hard mask filling and planarization within an odd-numbered wire region according to an embodiment of the present invention;

[0024] Figure 15 A cross-sectional view of hard mask filling and planarization within an even-numbered wire region according to an embodiment of the present invention;

[0025] Figure 16 A top view of forming an additional mask material on additional wires during the fabrication of a semiconductor device according to an embodiment of the present invention;

[0026] Figure 17 A top view of removing a hard mask from a wire during the fabrication of a semiconductor device according to an embodiment of the present invention;

[0027] Figure 18 A top view of removing a sacrificial material from a cutting region and a dielectric material filler during the fabrication of a semiconductor device according to an embodiment of the present invention;

[0028] Figure 19 A cross-sectional view of the odd-numbered wires of the device shown in Figure 18 according to an embodiment of the present invention;

[0029] Figure 20 A cross-sectional view of the even-numbered wires of the device shown in Figure 18 according to an embodiment of the present invention; and

[0030] Figure 21 A block diagram / flowchart showing a system / method for manufacturing a semiconductor device according to another embodiment of the present invention. DETAILED DESCRIPTION

[0031] The embodiments described herein provide for the formation of self-aligned top vias or up vias at the ends of wires. More specifically, a cutting mask can be used to define wire cuts, and selective deposition can be used to form self-aligned top vias on both sides of the cuts corresponding to the wire ends. The via critical dimension (CD) at the wire ends can be controlled by selective deposition coverage along the direction of the wire. As a result, via CD variations that would otherwise be introduced due to lithographically aligning the vias to previously formed wire cuts are not introduced.

[0032] It should be understood that various aspects of the present invention will be described in accordance with a given illustrative architecture; however, other architectures, structures, substrate materials, and process features and steps may vary within the scope of various aspects of the present invention.

[0033] It should also be understood that when an element such as a layer, region, or substrate is referred to as being "on" or "above" another element, it can be directly on the other element or there can be intervening elements. In contrast, when an element is referred to as being "directly on" or "immediately on" another element, there are no intervening elements. It should also be understood that when an element is referred to as being "connected" or "coupled" to another element, the element can be directly connected or coupled to the other element or there can be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0034] This embodiment may include the design for an integrated circuit chip, which can be created in a graphical computer programming language and stored in a computer storage medium (such as a disk, magnetic tape, physical hard disk drive, or virtual hard disk drive, such as in a storage access network). If the designer does not fabricate the chip or the lithography mask for fabricating the chip, the designer can transfer the resulting design directly or indirectly to such an entity by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., via the Internet). The stored design is then converted into an appropriate format (e.g., GDS11) for fabricating the lithography mask, and the appropriate format typically includes multiple copies of the chip design under discussion that are to be formed on the wafer. The lithography mask is used to define the areas of the wafer (and / or the layers thereon) to be etched or otherwise processed.

[0035] The methods described herein can be used to fabricate integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of the original wafer (i.e., as a single wafer having multiple unpackaged chips), as a bare chip, or in a packaged form. In the latter case, the chip is mounted in a single-chip package (such as a plastic carrier with leads fixed to a motherboard or other higher-level carrier) or a multi-chip package (such as a ceramic carrier having one or both of surface interconnects or buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (such as a motherboard) or (b) a final product. The final product can be any product that includes an integrated circuit chip, ranging from toys and other low-end applications to advanced computer products having a display, keyboard, or other input devices and a central processing unit.

[0036] It should also be understood that material compounds will be described in terms of the listed elements (e.g., SiGe). These compounds include the elements in different proportions within the compound. For example, SiGe includes Si x Ge 1-x, where x is less than or equal to 1, and so on. In addition, other elements can be included in the compound and still function in accordance with the principles of the present invention. Compounds having additional elements will be referred to herein as alloys.

[0037] References in the specification to "one embodiment" or "an embodiment" and other variations thereof mean that the particular features, structures, characteristics, etc. described in connection with that embodiment are included in at least one embodiment. Thus, the phrases "in one embodiment" or "in an embodiment" and any other variations thereof that appear throughout the specification do not necessarily all refer to the same embodiment.

[0038] It should be understood that, for example, in the case of "A / B", "A and / or B", and "at least one of A and B", the use of any of the following " / ", "and / or", and "at least one of" is intended to cover the selection of only the first-listed item (A), or only the second-listed item (B), or the selection of both options (A and B). As another example, in the case of "A, B, and / or C" and "at least one of A, B, and C", such language is intended to cover the selection of only the first-listed option (A), or only the second-listed option (B), or only the third-listed option (C), or only the first and second-listed options (A and B), or only the first-listed item and the third-listed item (A and C), or only the second-listed item and the third-listed item (B and C), or the selection of all three options (A and B and C). It will be apparent to those of ordinary skill in the art that this can be extended for many of the listed options.

[0039] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the exemplary embodiments. As used herein, unless the context clearly dictates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms as well. It should be further understood that when used herein, the terms "comprises", "comprising", "includes", and / or "including" specify the presence of the stated features, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or combinations thereof.

[0040] For ease of description, spatial relative terms such as "under", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or feature to another element or feature, as shown in the figures. It will be understood that the spatial relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is flipped, an element described as "below" or "under" another element or feature will be oriented "above" the other element or feature. Thus, the term "below" can include both the above and below orientations. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly. In addition, it should also be understood that when a layer is referred to as being "between" two layers, that layer may be the only layer between the two layers, or there may also be one or more intermediate layers.

[0041] It will be understood that although the terms first, second, etc. may be used herein to describe different elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, without departing from the scope of the inventive concept, the first element discussed below may be referred to as the second element.

[0042] Now referring to the accompanying drawings, where like numbers represent like or similar elements, and first referring to Figure 1 , a top view of a semiconductor device 100 is provided. As shown, the device 100 includes a dielectric layer 102. According to the embodiments described herein, the dielectric layer 102 may include any suitable dielectric material. For example, the lower dielectric layer may include, for example, silicon dioxide (SiO2), low-k dielectrics, nitride layers, and combinations thereof. In one embodiment, the dielectric layer 102 may include an ultra-low-k (ULK) material. For example, the dielectric layer 102 may include a dielectric material having a dielectric constant k less than or equal to, for example, about 2.5.

[0043] As further shown, a plurality of hard masks are formed on a plurality of wires. More specifically, "odd" hard masks 110-1 and 110-2 are formed on "odd" wires within an "odd" wire region (not shown), and "even" hard masks 120-1 and 120-2 are formed on "even" wires within an "even" wire region (not shown).

[0044] The odd hard masks 110-1 and 110-2 include materials different from those of the even hard masks 120-1 and 120-2. More specifically, as will be described in further detail below, the materials of the hard masks can be selected to support selective etching of the hard masks during the process. In addition, the odd hard masks 110-1 and 110-2 can include the same or different materials, and the even hard masks 120-1 and 120-2 can include the same or different materials.

[0045] Examples of suitable materials for forming the odd hard masks 110-1 and 110-2 can include silicon nitride materials (e.g., SiN), silicon carbide materials (e.g., SiC), etc. Examples of suitable materials for forming the even hard masks 120-1 and 120-2 can include, but are not limited to, silicon oxide materials (SiO x ), spin-on glass (SOG) materials, etc. However, according to the embodiments described herein, the odd hard masks and the even hard masks can include any suitable materials.

[0046] Reference Figure 2 , a cross-sectional view of the device 100 through the line 1-1’ of Figure 1 is provided corresponding to a cross-section through one of the odd wire regions, and reference Figure 3 , a cross-sectional view of the device 100 through the line 2-2’ of Figure 1 is provided corresponding to a cross-section through one of the even wire regions.

[0047] As Figure 2 shown, the device 100 includes an odd wire 130-1 and an odd hard mask 110-1 formed on the odd wire 130-1. As Figure 3 shown, the device 100 includes an even wire 130-2 and an even hard mask 120-1 formed on the even wire 130-2. A dielectric layer 102 is formed along the sidewalls of the wires 130-1 and 130-2 and the hard masks 110-1 and 120-1. Examples of suitable conductive materials that can be used to form the wires 130-1 and 130-2 include, but are not limited to, copper (Cu), tungsten (W), ruthenium (Ru), cobalt (Co), aluminum (Al), etc.

[0048] Referring to Figures 4 to 6, openings 137-1 and 137-2 are formed, as well as a cut region 150-2 corresponding to the even-numbered wire 130-2. For example, as shown in this illustrative example, openings 137-1 and 137-2 can be formed by forming a mask material 135, patterning the mask material 135 into hard masks 110-1 and 120-1, selectively etching the hard mask 120-1 relative to the hard mask 110-1, and etching the even-numbered wire 130-2 to form the cut region 150-2. Then the mask material 135 can be removed after forming the cut region 150-2.

[0049] According to the embodiments described herein, any suitable process can be used to form the openings 137-1 and 137-2 and the cut region 150-2. In one embodiment, reactive ion etching (RIE) can be used. For example, selective RIE can be used to selectively etch the material of the hard mask 120-1 (e.g., SiOx) relative to the material of the hard mask 110-1 (e.g., SiN).

[0050] According to the embodiments described herein, the mask material 135 can include any suitable material. In some embodiments, the mask material 135 can include multiple layers. For example, the mask material 135 can include an organic planarization layer (OPL), an anti-reflective coating (ARC) (e.g., a SiARC layer), and a resist layer, which can form a three-layer photolithography mask. As another example, the mask material 135 can include an OPL, a dielectric layer (e.g., an oxide), a bottom anti-reflective coating (BARC layer), and a resist layer, which can form a four-layer photolithography mask. The pattern in the mask material 135 can be formed using any suitable photolithography stack (not shown) with any suitable photolithography process (e.g., deep UV lithography or extreme UV lithography).

[0051] Reference Figures 7 to 9 , openings 147-1 and 147-2 are formed, as well as a cut region 150-1 corresponding to the odd-numbered wire 130-1. For example, as shown in this illustrative example, openings 147-1 and 147-2 can be formed by forming a mask material 145, patterning the mask material 145 into hard masks 110-1 and 120-1, selectively etching the hard mask 110-1 relative to the hard mask 120-1, and etching the odd-numbered wire 130-1 to form the cut region 150-1. Then the mask material 135 can be removed after forming the cut region 150-1.

[0052] According to the embodiments described herein, any suitable process can be used to form openings 147-1 and 147-2 and cutting regions 150-1. In one embodiment, RIE can be used. For example, selective RIE can be used to selectively etch the material of hard mask 120-1 (e.g., SiOx) relative to the material of hard mask 110-1 (e.g., SiN).

[0053] According to the embodiments described herein, mask material 145 can include any suitable material. In some embodiments, similar to mask material 135, mask material 145 can include multiple layers. For example, mask material 435 can include an OPL, an ARC (e.g., a SiARC layer), and a resist layer, which can form a three-layer lithography mask. As another example, mask material 145 can include an OPL, a dielectric layer (e.g., an oxide), a BARC layer, and a resist layer, which can form a four-layer lithography mask. The pattern in mask material 145 can be formed using any suitable lithography stack (not shown) using any suitable lithography process (e.g., deep UV lithography or extreme UV lithography).

[0054] Reference Figure 10 , a cross-sectional view of device 100 corresponding to the odd wire region is provided, which shows that a sacrificial layer 155-1 is formed within cutting region 150-1, and reference Figure 11 , a cross-sectional view of device 100 corresponding to the even wire region is provided, which shows that a sacrificial layer 155-2 is formed within cutting region 150-2.

[0055] According to the embodiments described herein, sacrificial layers 155-1 and 155-2 can include any suitable material. Examples of suitable materials that can be used to form sacrificial layers 155-1 and 155-2 include, but are not limited to, titanium nitride materials (e.g., TiN), titanium oxide materials (e.g., TiO x ), aluminum oxide materials (e.g., A1O x ), aluminum nitride materials (e.g., AlN), etc.

[0056] According to the embodiments described herein, any suitable process can be used to form sacrificial layers 155-1 and 155-2. For example, sacrificial layers 155-1 and 155-2 can be formed in cutting regions 150-1 and 150-2 by filling cutting regions 150-1 and 150-2 with a sacrificial material, performing a planarization process (e.g., chemical mechanical planarization (CMP)), and recessing the sacrificial material in cutting regions 150-1 and 150-2 to form sacrificial layers 155-1 and 155-2. For example, if the sacrificial material includes a metal oxide, a chlorine-based etch chemistry can be used to selectively etch the sacrificial material (e.g., using RIE) from hard masks 110-1 and 120-1 and dielectric layer 102.

[0057] At this time, the dielectric layer 102 is replaced by the replacement layer 103. Replacing the dielectric layer 102 with the replacement layer 103 may include removing the dielectric layer 102 using one or more etching processes, filling the voids with a replacement material, and planarizing (e.g., CMP) or etch-back the replacement material to form the replacement layer 103. According to the embodiments described herein, the replacement layer 103 may include any suitable material. For example, the replacement layer 103 may include, for example, an organic planarization layer (OPL) or other organic spin-on materials.

[0058] Reference Figure 12 and Figure 13 , the hard masks 110-1 and 120-1 are selectively recessed with respect to the sacrificial layers 155-1 and 155-2, a conductive hard mask 160-1 is formed on the sacrificial layer 155-1 and the hard mask 110-1, and a conductive hard mask 160-2 is formed on the sacrificial layer 155-2 and the hard mask 110-2. More specifically, the conductive hard masks 160-1 and 160-2 may be formed by selective deposition of a conductive hard mask material. As Figure 12 and Figure 13 shown, the conductive hard masks 160-1 and 160-2 may be formed to have a semi-circular or semi-elliptical cross-sectional shape along the directions of the wires 130-1 and 130-2. According to the embodiments described herein, the conductive hard masks 160-1 and 160-2 may include any suitable material. Examples of suitable materials that may be used to form the conductive hard masks 160-1 and 160-2 include, but are not limited to, titanium (Ti), tantalum (Ta), titanium nitride materials (e.g., TiN), tantalum nitride materials (e.g., TaN), etc.

[0059] According to the embodiments described herein, any suitable process may be used to recess the hard masks 110-1 and 120-1 and form the conductive hard masks 160-1 and 160-2. For example, timed RIE etching, wet etching processes, or a combination thereof may be used to perform the recessing of the hard masks 110-1 and 120-1, and the timed RIE etching, wet etching processes, or a combination thereof may selectively etch the hard masks 110-1 and 120-1 with respect to the layers 103, 155-1, and 155-2. In one embodiment, a fluorocarbon-based RIE process may be used to recess the hard masks 110-1 and 120-1.

[0060] Referring to Figure 14 and Figure 15 , additional hard masks 170-1 and 170-2 are formed on the hard masks 110-1 and 120-1, respectively. In the exemplary embodiments herein, the additional hard masks 170-1 and 170-2 may be formed by depositing an additional hard mask material and performing a planarization process (e.g., CMP). As Figure 14 and15 As shown, planarization can cause the conductive hard masks 160-1 and 160-2 to have a flat upper surface.

[0061] Reference Figure 16 provides a top view showing the formation of additional hard masks 170-3 and 170-4 and additional conductive hard masks 180-1 and 180-2 corresponding to the odd hard mask 110-2 and the even hard mask 120-2, respectively. The additional hard masks 170-3 and 170-4 may include the same or different materials as the additional hard masks 170-1 and 170-2, and the additional conductive hard masks 180-1 and 180-2 may include the same or different materials as the additional conductive hard masks 160-1 and 160-2.

[0062] According to the embodiments described herein, any suitable process may be used to form the additional hard masks 170-3 and 170-4 and the additional conductive hard masks 180-1 and 180-2. For example, non-line-end via patterning for the even hard mask 120-2 may be performed to form a mask, the even hard mask 120-2 may be etched to form an opening based on the mask, and the mask may be removed. Non-line-end via patterning for the odd hard mask 110-2 may be performed to form a mask, the odd hard mask 110-2 may be etched to form an opening based on the mask, and the mask may be removed. After forming the openings in the odd hard mask 110-2 and the even hard mask 120-2, additional conductive hard mask material may be formed in the openings and a planarization process (e.g., CMP) may be performed.

[0063] Reference Figure 17 According to the embodiments described herein, any suitable etching process is used to remove the additional hard masks 170-1 to 170-4, the odd hard masks 110-1 and 110-2, and the even hard masks 120-1 and 120-2. Removal of the material results in the formation of top vias.

[0064] Reference Figure 18 provides a top view of the semiconductor device 100, describing the formation of the self-aligned top via 185, the removal of the replacement layer 103 and the sacrificial layers 155-1 and 155-2, and the formation of the dielectric layers 190 and 195.

[0065] Top vias 185 are each formed at a line end corresponding to a wire. For example, the top vias 185 can be formed by partially etching the wires 130-1 and 130-2 using the hard masks 160-1, 160-2, 180-1, and 180-2. Then, the replacement layer 103s can be removed using an etching process (e.g., RIE), the sacrificial layers 155-1 and 155-2 can be removed using another etching process (e.g., a wet etching process), the dielectric layer 190 can be formed by depositing a dielectric material and performing a planarization process (e.g., CMP), and the dielectric layer 195 can be formed by filling the space previously occupied by the sacrificial layers 155-1 and 155-2 and performing a planarization process (e.g., CMP).

[0066] According to the embodiments described herein, the dielectric layers 190 and 195 can include any suitable material. For example, the dielectric layer 190 can include a low-k or ULK dielectric material, and the dielectric layer 195 can include a "mid-k", low-k, or ULK dielectric material. As used herein, a mid-k dielectric material refers to a dielectric material having a dielectric constant of about 4 to about 7. The dielectric layers 190 and 195 can include the same or different dielectric materials.

[0067] Referring Figure 19 , a cross-sectional view of the device 100 through the line 1-1' is provided, which corresponds to a cross-section through one of the odd wire regions, and referring Figure 18 , a cross-sectional view of the device 100 through the line 2-2' is provided, which corresponds to a cross-section through one of the even wire regions. Figure 20 , a cross-sectional view of the device 100 through the line 2-2' is provided, which corresponds to a cross-section through one of the even wire regions. Figure 18 the line 2-2' is provided, which corresponds to a cross-section through one of the even wire regions.

[0068] Referring Figure 21 , a block diagram / flowchart is shown, which illustrates a system / method 200 for manufacturing a semiconductor device according to an embodiment.

[0069] At block 202, at least a first odd hard mask is formed on a first odd wire, and at least a first even hard mask is formed on a first even wire. A first dielectric layer can be formed on the first odd and even hard masks and on the exposed sidewalls of the first odd and even wires.

[0070] The first odd hard mask can be formed to include a different material from the first even hard mask. More specifically, the materials of the first odd hard mask and the even hard mask can be selected to support selective etching of the hard mask during processing. Additionally, in embodiments where a second odd hard mask and an even hard mask are formed on second odd and even wires, respectively, the first odd hard mask and the second odd hard mask can be formed to include the same or different materials, and the first even hard mask and the second even hard mask can be formed to include the same or different materials.

[0071] Examples of suitable materials for forming an odd hard mask can include silicon nitride materials (e.g., SiN), silicon carbide materials (e.g., SiC), etc. Examples of suitable materials for forming a uniform hard mask can include, but are not limited to, silicon oxide materials (SiO x ), spin-on glass (SOG) materials, etc. However, according to the embodiments described herein, the odd hard mask and the even hard mask can include any suitable material.

[0072] Examples of suitable conductive materials that can be used to form odd and even wires include, but are not limited to, copper (Cu), tungsten (W), ruthenium (Ru), cobalt (Co), aluminum (Al), etc.

[0073] See above Figures 1 - 3 for further details regarding block 202.

[0074] At block 204, a first cut region corresponding to the first even wire is formed. Forming the first cut region can include forming a first mask material over the first odd hard mask and the even hard mask, patterning the first mask material onto the first odd and even hard masks to form first odd and even openings respectively, selectively etching the first even hard mask relative to the first odd hard mask, and etching the first even wire through the first even opening to form the first cut region. The first mask material can then be removed.

[0075] According to the embodiments described herein, any suitable process can be used to form the first opening and the first cut region. In one embodiment, reactive ion etching (RIE) can be used. For example, selective RIE can be used to selectively etch the material of the first even hard mask (e.g., SiOx) relative to the material of the first odd hard mask (e.g., SiN).

[0076] According to the embodiments described herein, the first mask material can be formed to include any suitable material. In some embodiments, the first mask material can be formed to include multiple layers. For example, the first mask material can be formed to include an organic planarization layer (OPL), an anti-reflective coating (ARC) (e.g., SiARC layer), and a resist layer, which can form a three-layer lithography mask. As another example, the first mask material can be formed to include an OPL, a dielectric layer (e.g., oxide), a bottom anti-reflective coating (BARC layer), and a resist layer, which can form a four-layer lithography mask. The pattern in the first mask material can be formed using any suitable lithography stack (not shown) using any suitable lithography process (e.g., deep UV lithography or extreme UV lithography).

[0077] See above Figures 4 - 6 for further details regarding block 204.

[0078] At block 206, a second cut region corresponding to the first odd-numbered wire is formed. Forming the second cut region can include forming a second mask material on the first odd hard mask and the even hard mask, patterning the second mask material onto the first odd hard mask and the even hard mask to form second odd openings and even openings respectively, selectively etching the first even hard mask relative to the first odd hard mask, and etching the first odd-numbered wire through the second odd opening to form the second cut region. The second mask material can then be removed.

[0079] According to embodiments described herein, any suitable process can be used to form the second opening and the second cut region. In one embodiment, RIE can be used. For example, selective RIE can be used to selectively etch the material of the first uniform hard mask (e.g., SiOx) relative to the material of the first odd hard mask (e.g., SiN).

[0080] According to embodiments described herein, the second mask material can be formed to include any suitable material. In some embodiments, similar to the first mask material, the second mask material can be formed to include multiple layers. For example, the second mask material can include an OPL, an ARC (e.g., a SiARC layer), and a resist layer, which can form a three-layer photolithography mask. As another example, the second mask material can include an OPL, a dielectric layer (e.g., an oxide), a BARC layer, and a resist layer, which can form a four-layer photolithography mask. The pattern in the second mask material can be formed using any suitable photolithography stack (not shown) using any suitable photolithography process (e.g., deep UV lithography or extreme UV lithography).

[0081] The above reference Figures 7 to 9 describes further details regarding block 206.

[0082] At block 208, a first sacrificial layer is formed within the first cut region and a second sacrificial layer is formed within the second cut region. According to embodiments described herein, the sacrificial layer can be formed to include any suitable material. Examples of suitable materials that can be used to form the sacrificial layer include (but are not limited to) titanium nitride materials (e.g., TiN), titanium oxide materials (e.g., TiO x )), aluminum oxide materials (e.g., A1O x ), aluminum nitride materials (e.g., AlN), etc.

[0083] According to the embodiments described herein, any suitable process can be used to form the sacrificial layer. For example, the sacrificial layer can be formed in the cutting region by filling the cutting region with a sacrificial material, performing a planarization process (e.g., chemical mechanical planarization (CMP)), and recessing the sacrificial material in the cutting region to form the sacrificial layer. For example, if the sacrificial material includes a metal oxide, a chlorine-based etch chemistry can be used to selectively etch the sacrificial material (e.g., using RIE) relative to the first odd and even hard masks and the dielectric layer.

[0084] See above Figure 10 and Figure 11 Further details regarding block 208 are described.

[0085] At block 210, the first odd and even hard masks are recessed to form recessed odd and even hard masks. According to the embodiments described herein, any suitable process can be used to recess the first odd hard mask and the even hard mask. For example, the first odd and even hard masks can be recessed using timed RIE etching, a wet etching process, or a combination thereof, which can selectively etch the first odd and even hard masks with respect to the dielectric layer and the sacrificial layer. In one embodiment, a fluorocarbon-based RIE process can be used to recess the first odd and even hard masks.

[0086] At block 212, a first conductive hard mask and a second conductive hard mask are formed. The first conductive hard mask can be formed on the first sacrificial layer and the recessed odd hard mask, and the second conductive hard mask can be formed on the second sacrificial layer and the recessed even hard mask. More specifically, the first conductive hard mask and the second conductive hard mask can be formed by selective deposition of a first conductive hard mask material.

[0087] The first conductive hard mask and the second conductive hard mask can be formed to have a semi-circular or semi-circular cross-sectional shape along the direction of the first odd and even wires. According to the embodiments described herein, the first and second conductive hard masks can include any suitable material. Examples of suitable materials that can be used to form the first and second conductive hard masks include, but are not limited to, titanium (Ti), tantalum (Ta), titanium nitride materials (e.g., TiN), tantalum nitride materials (e.g., TaN), and the like. According to the embodiments described herein, any suitable process can be used to form the first conductive hard mask and the second conductive hard mask.

[0088] Forming the first and second conductive hard masks may further include replacing the dielectric material with a corresponding replacement layer. Replacing the dielectric material with a replacement layer may include removing the dielectric material using one or more etching processes, filling the voids with a replacement material, and planarizing (e.g., CMP) or etch-backing the replacement material to form the replacement layer. According to embodiments described herein, the replacement layer may include any suitable material. For example, the replacement layer may include, for example, an organic planarization layer (OPL) or other organic spin-on materials.

[0089] See above Figure 12 and Figure 13 Further details regarding blocks 210 and 212 are described.

[0090] At block 214, additional hard mask material is formed. Forming the additional hard mask material may include depositing the additional hard mask material on the recessed odd and even hard masks and the first and second conductive hard masks. Additionally, the additional hard mask material may be formed on the second odd and even hard masks. A planarization process (e.g., CMP) may then be performed. The planarization process may result in the first and second conductive hard masks having a flat upper surface.

[0091] At block 216, third and fourth conductive hard masks are formed based on non-line end via patterning. More specifically, an opening to the second even wire may be formed through the additional hard mask material and the second even hard mask, an opening to the second odd wire may be formed through the additional hard mask material and the second odd hard mask, second conductive hard mask material may be formed within the openings in the second even and odd wires, and a planarization process (e.g., CMP) may be performed. Examples of suitable materials that may be used to form the third and fourth conductive hard masks include, but are not limited to, titanium (Ti), tantalum (Ta), titanium nitride materials (e.g., TiN), tantalum nitride materials (e.g., TaN), etc. According to embodiments described herein, any suitable process may be used to form the third and fourth conductive hard masks.

[0092] At block 218, self-aligned top vias are formed at the line ends. The line ends correspond to the wires (e.g., the first odd and even wires). According to embodiments described herein, any suitable process may be used to form the self-aligned top vias. For example, forming the self-aligned top vias may include removing the odd and even hard masks and the additional hard mask material, and partially etching the first odd and even wires using the conductive hard masks.

[0093] See above with reference to Figures 14 to 17 Further details regarding blocks 214 - 218 are described.

[0094] At block 220, additional processing is performed.

[0095] The additional processing may include removing these replacement layers and sacrificial layers. The replacement layers may be removed using an etching process (e.g., RIE), and the sacrificial layers may be removed using another etching process (e.g., a wet etching process).

[0096] The additional processing may further include: forming a second dielectric layer in the space between the odd-numbered wires and the even-numbered wires; and forming a third dielectric layer in the space previously occupied by the replacement layers and the sacrificial layers. More specifically, the second dielectric layer may be formed by depositing a dielectric material and performing a planarization process (e.g., CMP), and the third dielectric layer may be formed by filling the space previously occupied by the replacement layers and the sacrificial layers and performing a planarization process (e.g., CMP).

[0097] The foregoing refers to Figures 18 to 20 further details regarding block 220 are described.

[0098] Preferred embodiments of a semiconductor device and a method of manufacturing the same have been described (which are intended to be illustrative and not restrictive), it should be noted that those skilled in the art can make modifications and variations based on the foregoing teachings. Accordingly, it should be understood that changes may be made in the specific embodiments disclosed within the scope of the invention as outlined in the appended claims. Thus, various aspects of the invention having the details and features required by patent law have been described, and what is claimed and desired to be protected by letters patent is set forth in the claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: Depressing a first odd hard mask and a first even hard mask to form depressed odd and even hard masks, wherein each of the depressed odd and even hard masks has a top surface lower than the top surface of an adjacent replacement layer; Forming a first conductive hard mask on the depressed odd hard mask, the first conductive hard mask including a first conductive hard mask material, and forming a second conductive hard mask on the depressed even hard mask; And Forming self-aligned top vias at line ends corresponding to first odd and even wires, at least in part based on the first conductive hard mask and the second conductive hard mask.

2. The method according to claim 1, wherein The first and second conductive hard masks are formed to have a semi-circular cross-sectional shape along the direction of the first odd and even wires.

3. The method according to claim 1, further comprising: Forming additional hard mask material on the depressed odd and even hard masks and the first and second conductive hard masks; Performing a planarization process after forming the additional hard mask material; And After the planarization process, forming third and fourth conductive hard masks based on non-line-end via patterning.

4. The method according to claim 3, wherein Forming the third and fourth conductive hard masks further comprises: Forming an opening through the additional hard mask material and a second even hard mask formed on a second even wire to the second even wire; Forming an opening through the additional hard mask material and a second odd hard mask formed on a second odd wire to the second odd wire; Forming a second conductive hard mask material within the openings to the second even and odd wires; and Performing a planarization process after forming the first and second conductive hard mask materials to form the third and fourth conductive hard masks.

5. The method according to claim 3, wherein, Forming the self-aligned top vias further comprises: Removing the depressed odd and even hard masks and the additional hard mask material; and Partially etching the first odd and even wires using the first and second conductive hard masks and the third and fourth conductive hard masks.

6. The method according to claim 1, further comprising: Forming a first odd hard mask on a first odd wire and a first even hard mask on a first even wire; Forming a first dielectric layer on the sidewalls of the first odd and even hard masks and the first odd and even wires; And Forming a first cutting region corresponding to the first even wire and a second cutting region corresponding to the first odd wire.

7. The method according to claim 6, wherein The first odd hard mask is formed to include a material different from that of the first even hard mask to support selective etching of the first odd and even hard masks.

8. The method according to claim 6, wherein, Forming the first cutting region further comprises: Forming a first mask material on the first odd and even hard masks; Patterning the first mask material to the first odd and even hard masks to respectively form first odd and even openings; Selectively etching the first even hard mask relative to the first odd hard mask; and Etching the first even wire through the first even opening to form the first cutting region.

9. The method according to claim 8, wherein Forming the second cutting region further comprises: Form a second mask material on the first odd and even hard masks and within the first cutting region; Pattern the second mask material to the first odd and even hard masks to form second odd openings and even openings respectively; Selectively etch the first even hard mask relative to the first odd hard mask; and Etch the first odd wire through the second even opening to form the first cutting region.

10. The method according to claim 6, further comprising replacing the first dielectric layer with a replacement layer.

11. The method according to claim 10, further comprising: Form a first sacrificial layer within the first cutting region; And Form a second sacrificial layer within the second cutting region.

12. The method according to claim 11, further comprising performing an additional process, including: Remove the first sacrificial layer and the second sacrificial layer to form an opening between the self-aligned top vias; Form a second dielectric layer within the opening; And Replace the replacement layer with a third dielectric layer.

13. The method according to claim 1, wherein, The first odd hard mask is formed to include a material different from that of the first even hard mask to support the selective etching of the first odd and even hard masks; And, Wherein, the first and second conductive hard masks are formed to have a semi-circular cross-sectional shape along the direction of the first odd and even wires.

14. The method according to claim 13, further comprising: Form an additional hard mask material on the recessed odd and even hard masks and the first and second conductive hard masks; Perform a planarization process after forming the additional hard mask material; And After the planarization process, form third and fourth conductive hard masks based on non-line end via patterning; Wherein, forming the third and fourth conductive hard masks further includes: Form an opening through the additional hard mask material and the second even hard mask formed on the second even wire to the second even wire; Form an opening through the additional hard mask material and the second odd hard mask formed on the second odd wire to the second odd wire; Form a second conductive hard mask material within the openings to the second even and odd wires; and Perform a planarization process after forming the first and second conductive hard mask materials to form the third and fourth conductive hard masks.

15. The method according to claim 14, wherein Forming the self-aligned top vias further includes: Remove the recessed odd and even hard masks and the additional hard mask material; and Partially etch the first odd and even wires using the first and second conductive hard masks and the third and fourth conductive hard masks.

16. The method according to claim 13, further comprising: Form a first odd hard mask on the first odd wire and a first even hard mask on the first even wire; Form a first dielectric layer on the sidewalls of the first odd and even hard masks and the first odd and even wires; And Form a first cutting region corresponding to the first even wire and a second cutting region corresponding to the first odd wire; Wherein, forming the first cutting region further includes: Form a first mask material on the first odd and even hard masks; Pattern the first mask material onto the first odd and even hard masks to form first odd and even openings respectively; Selectively etch the first even hard mask relative to the first odd hard mask; and Etch the first even wire through the first even opening to form the first cutting region; and Wherein, forming the second cutting region further includes: Form a second mask material on the first odd and even hard masks and within the first cutting region; Pattern the second mask material onto the first odd and even hard masks to form second odd and even openings respectively; Selectively etch the first even hard mask relative to the first odd hard mask; and etch the first odd wire through the second even opening to form the first cutting region.

17. The method according to claim 16, further comprising: Replace the first dielectric layer with a replacement layer; Form a first sacrificial layer within the first cutting region; And Form a second sacrificial layer within the second cutting region.

18. The method according to claim 17, further comprising performing additional processing, including: Remove the first and second sacrificial layers to form an opening between the self-aligned top vias; Form a second dielectric layer in the opening; And Replace the replacement layer with a third dielectric layer.

19. The method according to claim 1, comprising: Form a first odd hard mask on the first odd wire and a first even hard mask on the first even wire, the first odd hard mask being formed to include a material different from the first even hard mask to support selective etching of the first odd and even hard masks; Form a first dielectric layer on the sidewalls of the first odd and even hard masks and the first odd and even wires; Form a first cutting region corresponding to the first even wire and a second cutting region corresponding to the first odd wire; And, Replace the first dielectric layer with a corresponding replacement layer; Wherein, the first and second conductive hard masks are formed to have a semi-circular cross-sectional shape along the direction of the first odd and even wires.

20. The method according to claim 19, further comprising: Form an additional hard mask material on the recessed odd and even hard masks and the first and second conductive hard masks; Perform a planarization process after forming the additional hard mask material; And After the planarization process, form third and fourth conductive hard masks based on non-line end via patterning.

21. The method according to claim 20, wherein: Forming the third and fourth conductive hard masks further includes: Form an opening through the additional hard mask material and the second even hard mask formed on the second even wire to the second even wire; Form an opening through the additional hard mask material and the second odd hard mask formed on the second odd wire to the second odd wire; Form a second conductive hard mask material within the openings to the second even and odd wires; and After forming the first and second conductive hard mask materials, a planarization process is performed to form the third and fourth conductive hard masks; and Forming the self-aligned top via further includes: Removing the recessed odd and even hard masks and the additional hard mask material; and partially etching the first odd and even wires using the first and second conductive hard masks and the third and fourth conductive hard masks.

22. The method according to claim 19, wherein: Forming the first cutting region further includes: Forming a first mask material on the first odd and even hard masks; Patterning the first mask material to the first odd and even hard masks to form first odd and even openings respectively; Selectively etching the first even hard mask relative to the first odd hard mask; and etching the first even wire through the first even opening to form the first cutting region; and Forming a second cutting region further includes: Forming a second mask material on the first odd and even hard masks and within the first cutting region; Patterning the second mask material to the first odd and even hard masks to form second odd and even openings respectively; Selectively etching the first even hard mask relative to the first odd hard mask; and etching the first odd wire through the second even opening to form the first cutting region.

23. The method according to claim 19, further comprising: Forming a first sacrificial layer within the first cutting region; Forming a second sacrificial layer within the second cutting region; And Performing additional processing, including: Removing the first and second sacrificial layers to form an opening between the self-aligned top vias; Forming a second dielectric layer within the opening; and Replacing the replacement layer with a third dielectric layer.

24. The method according to claim 1, comprising: Forming a first odd hard mask on the first odd wire and a first even hard mask on the first even wire, the first odd hard mask being formed to include a material different from the first even hard mask to support selective etching of the first odd and even hard masks; Forming a first dielectric layer on the sidewalls of the first odd and even hard masks and the first odd and even wires; Forming a first cutting region corresponding to the first even wire and forming a second cutting region corresponding to the first odd wire; Forming a first sacrificial layer within the first cutting region and a second sacrificial layer within the second cutting region; And, Replacing the first dielectric layer with a corresponding replacement layer; Wherein, the first and second conductive hard masks are formed to have a semi-circular cross-sectional shape along the direction of the first odd and second even wires; Wherein, the method further includes: Forming an additional hard mask material on the recessed odd and even hard masks and the first and second conductive hard masks; Performing a planarization process after forming the additional hard mask material; After the planarization process, forming the third and fourth conductive hard masks based on the non-line end via pattern; and, Performing additional processing, including: Remove the first and second sacrificial layers to form an opening between the self-aligned top vias; Form a second dielectric layer in the opening; and, Replace the replacement layer with a third dielectric layer.

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