Durable hybrid heterostructure and method of manufacturing the same

Abstract

A hybrid heterostructure (10) includes a semiconductor layer (12) including indium antimonide, a superconductor layer (16) including aluminum, and a shield layer (14) between the semiconductor layer and the superconductor layer, the shield layer including indium arsenide. By including an indium arsenide shield layer between the indium antimonide semiconductor layer and the aluminum superconductor layer, a high performance and durable hybrid heterostructure suitable for use in a quantum computing device is provided.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to hybrid heterostructures, and in particular to superconductor / semiconductor heterostructures suitable for implementing quantum computing devices. BACKGROUND

[0002] Quantum computing is a type of computing in which quantum-mechanical phenomena, such as quantum state superposition and entanglement, are utilized to perform computations. In a topological quantum computer, computations are performed by manipulating quasi-particles, known as non-abelian anyons, that have unique physical properties that can be used to perform quantum computations.

[0003] Hybrid heterostructures, such as superconductor / semiconductor heterostructures, can be produced such that a region of non-abelian anyons is formed in the semiconductor. The non-abelian anyons formed in the hybrid heterostructure are often referred to as Majorana zero modes. Control structures, such as insulating gates, can be used with small networks of heterostructures to manipulate the non-abelian anyons and thereby create quantum computing units, such as qubits or qutrits.

[0004] Generally, it is desirable to have good registry between atoms in different materials of the hybrid heterostructure. That is, it is desirable to control the interaction of the different materials of the hybrid heterostructure at their intersection.

[0005] One hybrid heterostructure that has been investigated for quantum computing is aluminum / indium arsenide. Depositing aluminum on indium arsenide creates a clear boundary between the different materials. This in turn allows for the formation of a region of non-abelian anyons. As a result, aluminum / indium arsenide nanowires have shown promise for forming functional qubits.

[0006] Another hybrid heterostructure that has been investigated for quantum computing is aluminum / indium antimonide. Depositing aluminum on indium antimonide does not create a clear boundary between the different materials. After aluminum is deposited on indium antimonide, the aluminum reacts with the indium antimonide such that the final aluminum layer is consumed and replaced by a layer of aluminum indium antimonide. In other words, current manufacturing techniques are not able to produce a durable aluminum / indium antimonide heterostructure. The resulting aluminum indium antimonide / indium antimonide structure does not exhibit the formation of the desired region of non-abelian anyons. As a result, there has been little development in using aluminum / indium antimonide hybrid heterostructures for quantum computing applications.

[0007] In theory, indium antimonide can provide superior performance in a hybrid heterostructure over indium arsenide, including aluminum as a superconductor for quantum computing applications (e.g., due to its larger g-factor). However, as noted above, conventional manufacturing practices do not produce a durable aluminum / indium antimonide hybrid heterostructure. Accordingly, there is a need for a durable hybrid heterostructure including aluminum and indium antimonide and methods of manufacturing the same. Summary of the Invention

[0008] In one exemplary embodiment, a hybrid heterostructure includes a semiconductor layer comprising indium antimonide, a superconductor layer comprising aluminum, and a shielding layer comprising indium arsenide between the semiconductor layer and the superconductor layer. By including the indium arsenide shielding layer between the indium antimonide semiconductor layer and the aluminum superconductor layer, a high-performance and durable hybrid heterostructure suitable for quantum computing devices is provided.

[0009] In one exemplary embodiment, a method for fabricating a hybrid heterostructure includes providing a semiconductor layer comprising indium antimonide, providing a superconductor layer comprising aluminum, and providing a shielding layer comprising indium arsenide between the semiconductor layer and the superconductor layer. Providing the indium arsenide shielding layer between the indium antimonide semiconductor layer and the superconductor layer comprises aluminum provides a high-performance and durable hybrid heterostructure suitable for use in quantum computing devices.

[0010] Those skilled in the art will be able to understand the scope of the present disclosure and implement additional aspects thereof after reading the following detailed description of the preferred embodiments in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure and together with the description serve to explain the principles of the disclosure.

[0012] Figure 1 A hybrid heterostructure including a shielding layer according to one embodiment of the present disclosure is shown.

[0013] Figure 2 is a flow chart illustrating a method for fabricating a hybrid heterostructure according to one embodiment of the present disclosure.

[0014] Figures 3A to 3C A method for fabricating a hybrid heterostructure according to an embodiment of the present disclosure is shown. Figure 2 method.

[0015] Figure 4 A hybrid heterostructure according to one embodiment of the present disclosure is shown.

[0016] Figure 5 A hybrid heterostructure including one or more control structures according to one embodiment of the present disclosure is shown.

[0017] Figure 6 A hybrid heterostructure including one or more control structures according to one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0018] The embodiments set forth below represent necessary information for enabling those skilled in the art to practice the embodiments and to illustrate the best mode for practicing the embodiments. After reading the following description in light of the accompanying drawings, those skilled in the art will be able to understand the concepts of the present disclosure and will recognize the applications of these concepts not specifically mentioned herein. It should be understood that these concepts and applications fall within the scope of the present disclosure and the appended claims.

[0019] It should be understood that although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, the first element can be called the second element, and similarly, the second element can be called the first element without departing from the scope of this disclosure. As used herein, the term "and / or" includes any and all combinations of one or more related listed items.

[0020] It should be understood that when an element such as a layer, region, or substrate is referred to as being "on another element" or extending "onto another element," it can be directly on the other element or extend directly onto the other element, or there can be intervening elements. In contrast, when an element is referred to as being "directly on" or "extending directly onto" another element, there are no intervening elements. Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on another element" or "extending over another element," it can be directly on the other element or extend directly over the other element, or there can be intervening elements. In contrast, when an element is referred to as being "directly on" or "extending directly over" another element, there are no intervening elements. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0021] Relative terms, such as "below," "above," "upper," "lower," "horizontal," or "vertical," may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as illustrated in the figures. It should be understood that these terms and the terms discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0022] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the present disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and / or "including," when used herein, specify the presence of stated features, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof.

[0023] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that the terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification and the relevant art, and will not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0024] As mentioned above, while hybrid heterostructures including indium antimonide and aluminum show promise for quantum computing applications such as topological qubits, fabricating durable hybrid heterostructures using these materials has been a challenge so far due to the interactions between them. Figure 1 A hybrid heterostructure 10 is shown according to one embodiment of the present disclosure. The hybrid heterostructure 10 includes a semiconductor layer 12, a shielding layer 14 on the semiconductor layer 12, and a superconductor layer 16 on the shielding layer 14. The semiconductor layer 12 includes indium antimonide, and in some embodiments consists solely of indium antimonide. In one or more additional embodiments, the semiconductor layer 12 includes aluminum indium antimonide (InSb). x Al 1-x Sb). Superconductor layer 16 includes aluminum, and in some embodiments consists only of aluminum. Shielding layer 14 includes indium arsenide, and in some embodiments consists only of indium arsenide. By including shielding layer 14 between semiconductor layer 12 and superconductor layer 16, the interaction between semiconductor layer 12 and superconductor layer 16 can be reduced or eliminated. Therefore, the material of shielding layer 14 is selected so that it does not interact with semiconductor layer 12 or superconductor layer 16. In the above embodiment, indium arsenide does not significantly interact with indium antimonide or aluminum, and thus shielding layer 14 is provided to maintain the interface between semiconductor layer 12, shielding layer 14 and superconductor layer 16. As described above, without shielding layer 14, aluminum will react with indium antimonide, causing aluminum to be consumed to form aluminum indium antimonide, which is undesirable. Therefore, the indium arsenide shielding layer greatly improves the durability of the indium antimonide / aluminum hybrid heterostructure.

[0025] The thickness of shielding layer 14 can be very small, for example, less than 10 monolayers, more preferably less than 5 monolayers, and most preferably 2 monolayers. The thinner shielding layer 14 is, the less impact it has on the operation of the primary materials used in hybrid heterostructure 10. Therefore, it is desirable to minimize the thickness of shielding layer 14. In the above-described embodiment, the indium arsenide is very thin and has little impact on the operation of the indium antimonide / aluminum heterostructure, while still significantly improving its durability. In some embodiments, semiconductor layer 12 can form nanowires. Therefore, the thickness of semiconductor layer 12 can be between 1 nm and 10 nm, the width of semiconductor layer 12 can be between 50 nm and 200 nm, and the length of semiconductor layer 12 can be on the order of microns. Therefore, semiconductor layer 12 can form a quasi-1D structure, such that only the lowest subband is occupied in the thickness direction, while weaker confinement in the width direction provides for some occupied subbands. The thickness of superconductor layer 16 can be between 5 nm and 40 nm.

[0026] Although hybrid heterostructure 10 is shown alone for illustrative purposes, hybrid heterostructure 10 may be integrated into any number of known structures (e.g., nanowire arrays), provided on a substrate, or included in any number of other layers to form a functional quantum computing device.

[0027] Figure 2 is a flow chart illustrating a method for fabricating the hybrid heterostructure 10 according to one embodiment of the present disclosure. Figures 3A to 3C Shown Figure 2 The individual steps of the method shown are therefore discussed together below. Figure 2 and Figures 3A to 3C . Provide a semiconductor layer 12 (frame 100 and Figure 3A ). It is worth noting that the semiconductor layer 12 can be provided in any suitable manner. In one example, the semiconductor layer 12 is provided by an epitaxial process such as molecular beam epitaxy. In addition, the semiconductor layer 12 can be selectively grown, for example, by a selective area growth (SAG) process, such as the process described in International Patent Publication No. WO 2019 / 074557 A1 (the entire contents of which are incorporated herein by reference). Forming the semiconductor layer 12 using a SAG process allows the semiconductor layer 12 to be formed into nanowires, which can be used to form quantum computing devices such as topological qubits.

[0028] Provide a shielding layer 14 on the semiconductor layer (blocks 102 and Figure 3B The shielding layer 12 may be provided in any suitable manner. For example, the shielding layer 12 may be provided by an epitaxial process such as molecular beam epitaxy.

[0029] Provide a superconductor layer 16 on the shielding layer (blocks 104 and Figure 3CThe superconductor layer 16 may be provided in any suitable manner. For example, the superconductor layer 16 may be provided by a deposition process such as chemical vapor deposition, sputtering, or the like.

[0030] It is noted that the semiconductor layer 12, the shielding layer 14, and the superconductor layer 16 can be provided in any order. For example, in one embodiment, the shielding layer 14 is provided on the superconductor layer 16, and the semiconductor layer 12 is provided on the shielding layer. Different manufacturing techniques may require providing the semiconductor layer 12, the shielding layer 14, and the superconductor layer 16, all of which are contemplated herein.

[0031] Optionally, one or more control and / or interconnect structures may then be provided such that they are coupled to or otherwise proximate to one or more of the semiconductor layer 12, the shielding layer 14, and the superconductor layer 16 (block 106). These control and / or interconnect structures may enable certain functions of the hybrid heterostructure 10, for example, as a topological qubit.

[0032] Figure 4 A three-dimensional representation of a hybrid heterostructure 10 according to one embodiment of the present disclosure is shown. As described above, the semiconductor layer 12 may form nanowires. Thus, the thickness (L Z ) can be between 1 nm and 10 nm, and the width of the semiconductor layer 12 (L y ) can be between 50nm and 200nm, and the length of the semiconductor layer (L x ) 12 can be on the order of micrometers, particularly 1 μm or larger. More generally, the dimensions of semiconductor layer 12, shielding layer 14, and superconductor layer 16 are selected to provide a non-Abelian anyon region that can be used to create quantum computing devices such as topological qubits.

[0033] Figure 5 A hybrid heterostructure 10 including multiple control structures for manipulating its behavior is shown according to one embodiment of the present disclosure. In particular, Figure 5 A hybrid heterostructure 10 is shown that includes a plurality of gates 18 separated from the bottom side of the semiconductor layer 12 by an insulating layer 20. The gates 18 may include a metal layer, such as aluminum, titanium, gold, or the like. The insulating layer 20 may include an oxide layer, such as aluminum oxide. The gates 18 may be used to selectively provide an electric field to the hybrid heterostructure 10, which may cause a change in its chemical potential and thereby cause a change in its portion between a topological phase (i.e., having Majorana modes) and a non-topological phase (i.e., having no Majorana modes). More details about gate structures and how they are used to control the hybrid heterostructure 10 to provide topological qubits are described in U.S. Patent No. 9,040,959 B2, the entire contents of which are incorporated herein by reference.

[0034] Figure 6 A hybrid heterostructure 10 including multiple control structures for manipulating its behavior according to another embodiment of the present disclosure is shown. In particular, Figure 6 A hybrid heterostructure 10 is shown comprising a plurality of gate electrodes 22 separated from one side of a semiconductor layer 12 by an insulating layer 24. Figure 6 The gate electrode 22 is shown positioned along the thickness of the semiconductor layer 12, and Figure 5 The gate 18 is shown positioned along the width of the semiconductor layer 12. These gates, sometimes referred to as "side gates" and "top gates," can affect the behavior of the hybrid heterostructure 10 differently and, therefore, can be used to control different aspects of its behavior.

[0035] It is worth noting that many other control and / or interconnect structures, as well as supporting substrates, intermediate layers, etc., can be provided with the hybrid heterostructure 10 to provide quantum computing devices such as topological qubits. As mentioned above, indium antimonide shows great promise in quantum computing applications due to its large spin-orbit interaction strength and large Lande g-factor. In addition, aluminum is a preferred superconductor for quantum computing applications. By providing an indium arsenide shielding layer between indium antimonide and aluminum, a high-performance and durable hybrid heterostructure is provided that can provide high performance in quantum computing devices.

[0036] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure, and all such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the claims that follow.

Claims

1. A hybrid heterostructure comprising: A semiconductor layer comprising only indium antimonide or aluminum indium antimonide; a superconductor layer comprising aluminum; and A shielding layer, between the semiconductor layer and the superconductor layer, the shielding layer comprising only indium arsenide.

2. The hybrid heterostructure of claim 1, wherein the shielding layer has a thickness of less than 10 monolayers. The hybrid heterostructure of claim 2 , wherein the thickness of the shielding layer is less than 5 monolayers. The hybrid heterostructure of claim 3 , wherein the thickness of the shielding layer is 2 monolayers. 5 . The hybrid heterostructure according to claim 4 , wherein the semiconductor layer forms a nanowire such that a width of the semiconductor layer is between 50 nm and 200 nm and a thickness of the semiconductor layer is between 1 nm and 10 nm. The hybrid heterostructure according to claim 5 , wherein the thickness of the superconductor layer is between 5 nm and 40 nm. The hybrid heterostructure according to claim 4 , wherein the semiconductor layer comprises only aluminum indium antimonide. 8 . The hybrid heterostructure of claim 1 , wherein the semiconductor layer forms a nanowire such that a width of the semiconductor layer is between 50 nm and 200 nm and a thickness of the semiconductor layer is between 1 nm and 10 nm.

9. The hybrid heterostructure according to claim 8, wherein the thickness of the superconductor layer is between 5 nm and 40 nm.

10. The hybrid heterostructure of claim 1, wherein the semiconductor layer comprises only aluminum indium antimonide.

11. A method for fabricating a hybrid heterostructure, comprising: Providing a semiconductor layer comprising only indium antimonide or aluminum indium antimonide; providing a superconductor layer, the superconductor layer comprising aluminum; and • Providing a shielding layer between the semiconductor layer and the superconductor layer, the shielding layer comprising only indium arsenide.

12. The method of claim 11, wherein the shielding layer is provided such that the thickness of the shielding layer is less than 10 monolayers.

13. The method of claim 12, wherein the shielding layer is provided such that the thickness of the shielding layer is less than 5 monolayers.

14. The method of claim 13, wherein the shielding layer is applied such that the thickness of the shielding layer is 2 monolayers. 15 . The method of claim 14 , wherein the semiconductor layer is provided such that the semiconductor layer forms a nanowire, wherein a width of the semiconductor layer is between 50 nm and 200 nm and a thickness of the semiconductor layer is between 1 nm and 10 nm. 16 . The method according to claim 15 , wherein the superconductor layer is provided such that the thickness of the superconductor layer is between 5 nm and 40 nm. The method of claim 14 , wherein the semiconductor layer comprises only aluminum indium antimonide.

18. The method of claim 11, wherein the semiconductor layer is provided such that the semiconductor layer forms a nanowire, wherein a width of the semiconductor layer is between 50 nm and 200 nm and a thickness of the semiconductor layer is between 1 nm and 10 nm.

19. The method according to claim 18, wherein the superconductor layer is provided such that the thickness of the superconductor layer is between 5 nm and 40 nm.

20. The method of claim 11, wherein the semiconductor layer comprises only aluminum indium antimonide.

Images