Instruction transmitting unit, instruction executing unit, related apparatus and method

Abstract

The present disclosure provides an instruction transmitting unit, an instruction executing unit, related devices and methods. The instruction transmitting unit comprises: an instruction splitter configured to split a vector instruction to be executed into micro-instructions; a micro-instruction index obtainer configured to obtain an effective element number index of the micro-instruction based on an element range involved by the split micro-instruction; an index comparison subunit configured to compare the obtained effective element number index with a first index, the first index being an effective element number index of a fault-only-first micro-instruction which has not been processed completely; and a micro-instruction transmitting controller configured to transmit the split micro-instruction to a vector executing unit for execution in a case where the effective element number index is smaller than the first index. The present disclosure improves the running efficiency of subsequent vector instructions when a fault-only-first vector load instruction is involved in chain execution.

Description

Technical Field

[0001] This invention relates to the field of chips, and more specifically, to an instruction issuing unit, an instruction executing unit, related apparatus and methods. Background Technology

[0002] Chaining is a mechanism to accelerate vector execution. When a subsequent vector instruction requires the result of a preceding vector instruction written to a vector register as an operand, instead of waiting for the entire preceding instruction to complete, it breaks the instruction down into multiple micro-instructions. The results of the completed micro-instructions are output to the subsequent instruction in advance. This way, if a later instruction receives a portion of the result from a preceding instruction's micro-instruction, it doesn't need to wait for the entire preceding instruction's result, reducing waiting time and improving vector operation efficiency.

[0003] The valid element count (vl) is a control register parameter in the Vector Extensions instruction set of the freely available RISC architecture. It indicates the number of elements that a vector instruction needs to process and update. A vector instruction may not process and occupy all elements in the control register; the occupied elements are called valid elements, and the idle elements are called invalid elements. Generally, when a vector instruction is executed, it may need the results of previous vector instruction executions, and it also needs to refer to the valid element count for calculations and write-back. The difference between the Fault-Only (FOF) instruction and the normal vector load instruction is that the normal load instruction will respond with an exception if an access error occurs while loading any valid element, while the Fault-Only instruction will only respond with an exception if an access error occurs while loading the 0th element (the lowest element). If the access error occurs with a non-0th element, it will only update the valid element count to the total number of elements processed without access errors. The Fault-Only instruction is the only instruction in the freely available RISC architecture's Vector Extensions instruction set, besides the setvl / setvli instructions specifically for setting the valid element count, that can modify the valid element count.

[0004] Normally, vector instructions only need to refer to the number of valid elements set by the `setvl` / `setvli` instructions. This parameter setting instruction is simple to execute with short latency and does not cause a performance bottleneck. However, the fault-only vector load instruction, as an instruction that may change the number of valid elements, has an unpredictable execution latency. Subsequent vector instructions must wait for the fault-only vector load instruction to return whether the number of valid elements has been updated and its updated value before they can execute correctly. If all subsequent vector instructions simply wait for the fault-only vector load instruction to confirm the update status of the number of valid elements before starting execution, the efficiency of chained execution is greatly reduced. Summary of the Invention

[0005] Therefore, embodiments of the present application aim to improve the running efficiency of subsequent vector instructions when only a failure-priority vector load instruction is involved in chain execution.

[0006] To achieve this purpose, according to an aspect of the present disclosure, an instruction emission unit is provided, comprising:

[0007] an instruction splitter configured to split a to-be-executed vector instruction into micro-instructions;

[0008] a micro-instruction index obtainer configured to obtain an effective element number index of the micro-instruction based on an element range involved in the split micro-instruction;

[0009] an index comparison subunit configured to compare the obtained effective element number index with a first index, the first index being an effective element number index of an unprocessed only failure-priority micro-instruction;

[0010] a micro-instruction emission controller configured to send the split micro-instruction to a vector execution unit for execution if the effective element number index is smaller than the first index.

[0011] Optionally, the instruction emission unit further comprises an operand dependency judgment subunit configured to determine whether a first micro-instruction is executed, wherein an operand in the split micro-instruction depends on the first micro-instruction; wherein the micro-instruction emission controller sends the split micro-instruction to the vector execution unit for execution only if the first micro-instruction is executed and the effective element number index is smaller than the first index.

[0012] Optionally, the micro-instruction index obtainer obtains the effective element number index of the micro-instruction based on the element range involved in the split micro-instruction according to the following formula:

[0013] vl_index(i) = 8*(i+1) / VREG_NUM - 1,

[0014] wherein vl_index(i) is the effective element number index, VREG_NUM is a number of vector registers to be written back by the to-be-executed vector instruction, i is a serial number of the element range, i = 0, 1, 2, …, VLEN*VREG_NUM / DPLEN-1, wherein VLEN is a vector register bit width and DPLEN is a processing bit width of the vector execution unit.

[0015] Optionally, if VREG_NUM = 8, the effective element number index corresponding to the element range with the lowest serial number is 0000, and the effective element number index increases by 0001 for each higher serial number of the element range.

[0016] Optionally, if VREG_NUM = 4, the index of the number of valid elements corresponding to the element range with the lowest sequence number is 0001, and the index of the number of valid elements increases by 0010 for each higher sequence number in the element range.

[0017] Optionally, if VREG_NUM = 2, the index of the number of valid elements corresponding to the element range with the lowest sequence number is 0011, and the index of the number of valid elements increases by 0100 for each higher sequence number in the element range.

[0018] Optionally, if VREG_NUM = 1, the index of the number of valid elements corresponding to the element range with the lowest sequence number is 0111, and the index of the number of valid elements increases by 1000 for each higher sequence number in the element range.

[0019] Optionally, the instruction splitter splits the vector instruction to be executed into (VLEN·LMUL) / DPLEN microinstructions, where VLEN is the vector register bit width, LMUL is the number of vector registers occupied by the vector in the vector instruction to be executed, and DPLEN is the processing bit width of the vector execution unit.

[0020] Optionally, the operand relevance determination subunit determines whether the first microinstruction has been executed completely in the following manner:

[0021] Retrieve the operands from the split microinstructions;

[0022] Obtain the microinstruction that generates the operand from the previously separated microinstructions;

[0023] Determine whether the acquired micro-instructions have been executed.

[0024] Optionally, the microinstruction issuing controller may retain the split microinstruction if the first microinstruction has not been executed or if the number of valid elements is less than the first index.

[0025] Optionally, the vector execution unit includes multiple vector operation subunits, and the microinstruction dispatch controller sends the split microinstructions in parallel to the multiple vector operation subunits for execution.

[0026] According to one aspect of this disclosure, a vector execution unit is also provided, comprising:

[0027] The vector operation subunit is used to execute the micro-instructions after the vector instruction to be executed is decomposed.

[0028] A first index recorder is configured to record a first index and, in response to a request from an instruction issuing unit, issue the first index, wherein the first index is the index of the number of valid elements of the fault-priority microinstructions that the vector operation subunit has not yet processed.

[0029] According to an aspect of the present disclosure, there is also provided a processing unit comprising:

[0030] an instruction fetch unit configured to fetch a vector instruction to be executed;

[0031] an instruction decode unit configured to decode the vector instruction to be executed;

[0032] an instruction issue unit as described above;

[0033] a vector execution unit as described above.

[0034] According to an aspect of the present disclosure, there is also provided a computing device comprising:

[0035] a processing unit as described above;

[0036] a memory coupled to the processing unit, the memory storing the vector instruction to be executed.

[0037] According to an aspect of the present disclosure, there is also provided a data center comprising a computing device as described above.

[0038] According to an aspect of the present disclosure, there is also provided a vector execution acceleration method comprising:

[0039] splitting a vector instruction to be executed into micro-instructions;

[0040] based on a range of elements involved in the split micro-instructions, obtaining an effective element number index of the micro-instructions;

[0041] comparing the obtained effective element number index with a first index, the first index being an effective element number index of a fault-only-first micro-instruction that has not been processed completely;

[0042] in a case where the effective element number index is smaller than the first index, sending the split micro-instructions to a vector execution unit for execution.

[0043] Optionally, before sending the split micro-instructions to the vector execution unit for execution, the method further comprises determining whether a first micro-instruction has been executed, wherein an operand in the split micro-instructions depends on the first micro-instruction; and the sending the split micro-instructions to the vector execution unit for execution in the case where the effective element number index is smaller than the first index comprises: sending the split micro-instructions to the vector execution unit for execution only in a case where the first micro-instruction has been executed and the effective element number index is smaller than the first index.

[0044] Optionally, the obtaining the valid element number index of the micro instruction based on the element range involved by the split micro instruction comprises calculating the valid element number index according to the following formula:

[0045] vl_index(i) = 8*(i+1) / VREG_NUM - 1,

[0046] wherein, vl_index(i) is the valid element number index, VREG_NUM is the number of vector registers to be written back by the vector instruction to be executed, i is the serial number of the element range, i = 0, 1, 2, …, VLEN*VREG_NUM / DPLEN-1, wherein, VLEN is the bit width of the vector register, and DPLEN is the processing bit width of the vector execution unit.

[0047] Optionally, if VREG_NUM = 8, the valid element number index corresponding to the element range with the lowest serial number is 0000, and the valid element number index increases by 0001 for each higher serial number of the element range.

[0048] Optionally, if VREG_NUM = 4, the valid element number index corresponding to the element range with the lowest serial number is 0001, and the valid element number index increases by 0010 for each higher serial number of the element range.

[0049] Optionally, if VREG_NUM = 2, the valid element number index corresponding to the element range with the lowest serial number is 0011, and the valid element number index increases by 0100 for each higher serial number of the element range.

[0050] Optionally, if VREG_NUM = 1, the valid element number index corresponding to the element range with the lowest serial number is 0111, and the valid element number index increases by 1000 for each higher serial number of the element range.

[0051] Optionally, the determining whether the first micro instruction is executed completely comprises:

[0052] obtaining an operand in the split micro instruction;

[0053] obtaining a micro instruction in which the operand is generated from the micro instruction split previously;

[0054] determining whether the obtained micro instruction is executed completely.

[0055] Optionally, after determining whether the first micro instruction is executed completely, the method further comprises: maintaining the split micro instruction in a case that the first micro instruction is not executed completely or the valid element number index is less than the first index.

[0056] The disclosure embodiments ingeniously use the encoding and comparison of the valid element number index to low-cost complete the judgment of whether the valid element number index needed by a vector instruction in chain execution is ready. The disclosure embodiments obtain the valid element number index of the micro instruction based on the element range involved by the split micro instruction, and compare the obtained valid element number index with a first index, which is the valid element number index of the fault-only micro instruction that has not been processed completely. If the valid element number index is smaller than the first index, it indicates that the valid element number index needed by the to-be-executed vector instruction is ready, so it is not necessary to wait for the previous fault-only vector load instruction to be executed completely and return the updated value of the valid element number before starting the execution, which greatly improves the running efficiency of the subsequent vector instruction of the fault-only vector load instruction in chain execution. BRIEF DESCRIPTION OF DRAWINGS

[0057] The above and other objects, features and advantages of the present application will be more clearly understood from the following description taken in conjunction with the accompanying drawings, in which:

[0058] Figure 1 is a framework diagram of a data center to which the disclosure embodiments are applied;

[0059] Figure 2 shows a schematic diagram of a server according to one embodiment of the disclosure; Figure 1

[0060] Figure 3 is a schematic diagram of a processor according to one embodiment of the disclosure; Figure 2

[0061] Figure 4 shows a schematic diagram of the vector register bit width (valid element number EN);

[0062] Figure 5 shows two examples of the vector standard element bit width (SEW);

[0063] Figure 6 shows three examples of the vector occupied vector register number (LMUL);

[0064] Figure 7A -B shows different examples of different valid element numbers (valid element number) of one instruction processing, respectively;

[0065] Figure 8 shows a case of changing the valid element number after a fault-only instruction access error;

[0066] Figure 9 ​​A microinstruction execution timing table of different clock cycles is shown, which shows the dependency of microinstructions according to one instruction split into microinstructions on microinstructions of previous instructions split into microinstructions;

[0067] Figure 10 An example of microinstructions of two instructions in chain execution are shown, which are executed in different clock cycles respectively.

[0068] Figure 11 Two examples of changing the element range of elements with valid element number when the fault-priority-only instruction access is wrong are shown;

[0069] Figure 12 A list of possible element ranges processed by microinstructions split from a vector instruction to be executed in the case of different vector register numbers (VREG_NUM) to be written back by the vector instruction is shown.

[0070] Figure 13 A comparison example of the valid element number index of microinstructions split from a vector instruction after a fault-priority-only instruction and the valid element number index of microinstructions split from the fault-priority-only instruction is shown.

[0071] Figure 14 A flow chart of a vector execution acceleration method according to one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0072] The present application is described in detail below based on embodiments, but the present application is not limited to only these embodiments. In the following detailed description of the present application, some specific details are described in detail. The present application can also be completely understood without the description of these details by those skilled in the art. In order to avoid confusion of the essence of the present application, well-known methods, processes, and flows are not described in detail. In addition, the drawings are not necessarily drawn to scale.

[0073] The following terms are used herein.

[0074] Free and open RISC: RISC-V, a project initiated by the computer mecca of Berkeley, USA, is a free and open RISC. RISC is different from CISC. X86, which dominates personal computers, is a CISC interface specification. RISC simplifies some infrequently used instructions in CISC. The interface specification that dominates the embedded and mobile fields is a RISC interface specification. Of course, the free and open RISC is also a RISC interface specification, and its greatest advantage is openness and freedom, known as the Linux of the hardware field. The project is maintained by the community, and there is no need to charge for using the architecture, nor are there any hard usage restrictions. At present, many large companies have joined the foundation of the architecture to get rid of the control of industry giants. The architecture has a latecomer advantage. ARM and X-86 have been developed for many years, and large-scale commercial use needs to consider backward compatibility. The free and open RISC has no historical baggage, so the instruction set is very simple, and the performance is very good.

[0075] Vector extension instruction set of free and open RISC: In the information society, a large number of the same type of operations are often needed, such as processing the same data of a large number of users on the Internet. A large number of single instructions are needed to process them. In order to avoid the overhead of such single instruction processing, vector operation instructions are generated. The data items involved in single operation are regarded as an element in the vector, and the batch single data operation result is generated at a time through this vector operation method. Based on this idea, a number of vector operation instructions are extended to the free and open RISC to become the vector extension instruction set of the free and open RISC. The parameters such as the number of valid elements EN / SEW / LMUL / fault only priority / valid element number in the following text come from this instruction set.

[0076] Vector register bit width (VLEN): The number of bits contained in the vector register. The vector register is a register that stores the vector in the vector operation when the vector execution unit of the processor executes the vector operation. VLEN is a hardware configuration parameter defined in the vector extension instruction set of the free and open RISC. The vector extension instruction set of the free and open RISC defines 32 vector registers VR0-VR31, as shown in Figure 4 The number of bits of each register is represented by VLEN, which must be a power of 2, such as 64, 128, 256, 512, 1024, etc.

[0077] Standard Element Width (SEW) of a vector: the number of bits occupied by an element 201 in a vector. A vector is composed of elements 201, and a vector is stored in one or more vector registers. For a vector register, it generally stores more than one element 201. The number of bits occupied by each element 201 is the SEW. SEW is a software configurable parameter defined in the vector extension instruction set of the free and open source reduced instruction set computer architecture, which can support 8, 16, 32, 64, etc. Figure 5 The configuration modes of SEW = 8 and SEW = 16 are shown. When SEW = 8, each element 201 occupies 8 bits. If VLEN = 128, the vector register can accommodate 128 / 8 = 16 elements 201. When SEW = 16, each element 201 occupies 16 bits. If VLEN = 128, the vector register can accommodate 128 / 16 = 8 elements 201.

[0078] The number of vector registers occupied by a vector (LMUL), also known as the vector register group, is the number of vector registers needed to store all the elements in a vector. A vector is composed of elements, but the number of elements accommodated by each vector register is limited, so multiple vector registers may be needed to express a vector, and the number of vector registers needed to express a vector is the LMUL. LMUL is a software configurable parameter defined in the vector extension instruction set of the free and open source reduced instruction set computer architecture. Figure 6 The cases of LMUL = 1, 2, 4 are shown in the middle. Each vector register can accommodate 4 elements. When the vector includes 4 elements, LMUL = 1, i.e. 1 vector register can express the vector. When the vector includes 8 elements, LMUL = 2, i.e. 2 vector registers can express the vector. When the vector includes 16 elements, LMUL = 4, i.e. 4 vector registers can express the vector.

[0079] Number of valid elements: the number of valid elements is a control register parameter in the vector extension instruction set of the free and open source reduced instruction set computer architecture, which is used to indicate the number of valid elements that a vector instruction needs to process and update. A vector instruction may not process and occupy all the elements of the entire control register, the occupied elements are called valid elements, and the idle and unoccupied elements are called invalid elements. As shown in Figure 7A When the number of valid elements = 11, the vector instruction may only process elements 0-10, and does not process elements 12-15, which are idle. As shown in Figure 7BAs shown, when the number of valid elements = 16, the vector instruction can process all elements 0-15 in the vector registers. This parameter is of great significance, and subsequent vector instructions need to refer to this parameter for vector operation and writeback. Generally speaking, when the vector instruction is executed, on the one hand, the result of the previous vector instruction execution may be needed, and on the other hand, the number of valid elements needs to be referred to to confirm the number of valid elements for operation and writeback. The number of valid elements can only be overwritten by the vsetvli / vsetvl two write control register instructions and the fault-only vector load instruction. The fault-only vector load instruction will be described in detail below.

[0080] vsetvli / vsetvl: instructions in the freely available vector extension of the reduced instruction set architecture (RISC) to set the SEW / LMUL / number of valid elements parameters. For example, in the case of VLEN = 128, set LMUL = 4, SEW = 32, and the number of valid elements = 11, the VLEN*LMUL = 128*4 = 512-bit vector register group composed of VR0-VR3 can be regarded as being able to accommodate VLEN*LMUL / SEW = 16 elements, from low to high, elements 0 to 15, and each element has a bit width of 16 bits. However, the positions of these 16 elements are not necessarily used to place elements. The valid elements (i.e., the element positions where elements are placed) are specified by the number of valid elements. Since the number of valid elements = 11, the lowest 11 elements, i.e., elements 0-10, are valid elements, i.e., the lowest 11 element positions place elements, and the remaining element positions are idle.

[0081] Vector load instruction: an instruction for storing a vector in a vector register. When storing, each element of the vector occupies one SEW position, and the entire vector occupies LMUL vector registers, and the lowest number of valid element positions in the LMUL vector registers place elements, and the remaining positions do not place elements.

[0082] Fault-only vector load instruction: the difference between this type of instruction and the ordinary vector load instruction is that the ordinary load instruction will respond to an exception when an access error occurs when loading any valid element, while the fault-only vector load instruction will only respond to an exception when an access error occurs when loading the 0th element (the lowest element), and if an access error does not occur on the 0th element, only the number of valid elements will be updated to the total number of elements processed without an access error. For example, Figure 8As shown, when loading a vector of 11 elements, the vector should originally occupy the positions of elements 0-10. During the process of loading from low to high, no access error occurs when loading elements 0-3, but an access error occurs when loading element 4, so the number of valid elements is updated to 4, indicating that the valid elements are 0-3. The only instruction in the vector extension instruction set of the free and open RISC architecture, except setvl / setvli, that can modify the number of valid elements is the fault-priority vector load instruction.

[0083] Chaining: an acceleration mechanism for vector execution. In the case where a subsequent vector instruction needs the result of a previous vector instruction written in a vector register as an operand for operation, instead of waiting for the previous vector instruction to complete execution before executing, the instruction is divided into multiple micro-instructions, and the execution result of the micro-instruction that has been executed is output in advance to the subsequent instruction. In this way, if the subsequent instruction gets the result of a part of the micro-instructions of the previous instruction, it can run without waiting for the execution result of the entire previous instruction, reducing the waiting time and improving the efficiency of vector operation. For example, vector instruction A produces a result written in a vector register VRX, and vector instruction B needs to take the value of vector register VRX as an operand for operation. In the normal case, vector instruction B needs to wait for vector instruction A to complete before it can take the result of VRX as an operand for operation, i.e. the execution of instruction B depends on the result of instruction A, and there is a correlation between instruction B and instruction A. Since a vector is composed of elements, vector operation is in units of elements, and the result of vector operation VRX also contains multiple elements. When the number of elements is large and the execution capability of the operation unit is limited, only a part of the elements can be processed and the operation result can be output in advance to the operation unit where vector instruction B is located for processing. If the operation result of this part of elements is sufficient for some operations of vector instruction B, the waiting time of vector instruction B can be reduced, thereby accelerating the overall execution efficiency of vector operation.

[0084] Processing bit width of vector execution unit (DPLEN): As described above, when the number of elements of a vector is large and the execution capability of the vector execution unit is limited, only a part of the elements of the vector can be processed and the operation result can be generated at a time for the vector involved in the instruction, and the number of bits of this part of elements is DPLEN.

[0085] Micro-instruction: As described above, since the vector execution unit can only execute DPLEN-bit element operation at a time, the part of the instruction for DPLEN-bit element operation is divided out as a micro-instruction.

[0086] Operands: Operands are the entities on which operators in an instruction operate, specifying the quantities to be calculated. For example, the vector multiplication instruction `vmul.vv vr4,vr0,vr3` means multiplying vectors `vr4`, `vr0`, and `vr3`, with the resulting vector being the new vector `vr4`. Here, `vr4`, `vr0`, and `vr3` are all operands required by this vector multiplication instruction.

[0087] Valid Element Count Index: The valid element count index is not the actual number of valid elements. It's an index used for comparing the range of elements involved in a microinstruction. For ordinary vector instructions, this index reflects which segment of the vector register corresponds to the element range of the microinstruction it's divided into. For fault-only vector load instructions, it reflects which segment of the vector register corresponds to the element range of the microinstruction it's divided into. For example... Figure 13 As shown, instruction A is a fault-priority vector loading instruction only. Instruction B is a regular instruction that follows it. For instruction A, DPLEN is a 4-element bit width. Assuming that the microinstruction currently split from instruction A is microinstruction A-2, its effective element count index is encoded as 0101 according to the rules above. The microinstructions that have already been issued and executed are microinstruction A-0 and microinstruction A-1. Since microinstructions B-0 and B-1, which are split from instruction B, operate on the element range of 0-3, their effective element count index is encoded as 0001 according to the rules above. Because the encoded effective element count index 0001 is not less than the index 0001 of the incomplete A-0, it is necessary to wait for A-0 to finish executing and confirm the effective element count update information before issuing. For microinstructions B-2 and B-3, which are split from instruction B, their effective element count index is encoded as 0011 according to the rules above. Since 0011 is not less than the indices 0001 and 0011 of A-0 and A-1, etc., it is necessary to wait for A-0 and A-1 to finish executing and confirm the update information of the number of valid elements before issuing. The valid element index of microinstructions B-4 and B-5, which are split from instruction B, is 0101. Since it is not less than the indices 0001, 0011, and 0101 of A-0, A-1, and A-2, even if A-0 and A-1 have finished executing in vector operation subunit 1213, they cannot be executed and issued before microinstruction A-2. It is necessary to wait for A-2 to also be issued and executed.

[0088] Data center

[0089] Data centers are globally collaborative networks of specific devices used to deliver, accelerate, present, compute, and store data information over the Internet network infrastructure. In the future, data centers will also become assets for enterprise competition. Because data centers have to operate a large amount of data at all times, vector operation has emerged. Vector operation can vectorize a large amount of discrete data that needs to be operated in the same way, use discrete data to form a vector, and operate on the vector instead of calculating individual elements, thereby improving the operation efficiency of data that needs to be operated in the same way.

[0090] In a traditional large data center, the network structure is usually as shown in Figure 1 , that is, a hierarchical inter-networking model. This model includes the following parts:

[0091] Servers 10: Each server 10 is a processing and storage entity of the data center, and the processing and storage of a large amount of data in the data center are completed by these servers 10.

[0092] Access switches 3: Access switches 3 are switches used to connect servers 10 to the data center. One access switch 3 connects multiple servers 10. Access switches 3 are usually located at the top of the rack, so they are also called Top of Rack switches, which are physically connected to servers.

[0093] Aggregation switches 2: Each aggregation switch 2 connects multiple access switches 3 and provides other services such as firewalls, intrusion detection, network analysis, etc.

[0094] Core switches 1: Core switches 1 provide high-speed forwarding for packets entering and leaving the data center and provide connectivity for aggregation switches 2. The network of the entire data center is divided into L3 layer routing networks and L2 layer routing networks, and core switches 1 usually provide a resilient L3 layer routing network for the entire network of the data center.

[0095] Usually, aggregation switches 2 are the demarcation points of L2 and L3 layer routing networks, and the aggregation switches 2 below are L2 networks and the aggregation switches 2 above are L3 networks. Each group of aggregation switches manages a delivery point (POD, Point Of Delivery), and each POD is an independent VLAN network. Servers do not need to modify IP addresses and default gateways when migrating within a POD, because a POD corresponds to an L2 broadcast domain.

[0096] The Spanning Tree Protocol (STP) is typically used between the aggregation switches 2 and the access switches 3. The STP makes only one aggregation layer switch 120 available for a VLAN network, the other aggregation switches 2 are only used in case of a failure (dashed lines in the figure above). That is, at the level of the aggregation switches 2, horizontal scaling is not possible, because even if multiple aggregation switches 2 are added, only one is in operation.

[0097] Server

[0098] Figure 2 It is shown Figure 1 a schematic block diagram of one of the servers 10. The server 10 is an example of a "hub" system architecture. The server 10 can be built based on various models of processors currently on the market and driven by operating systems such as the WINDOWS™ operating system version, the UNIX operating system, the Linux operating system, etc. In addition, the server 10 can be implemented in hardware and / or software such as a PC, a desktop, a notebook, a server and a mobile communication device, etc.

[0099] As Figure 2 shown, the server 10 of the embodiment of the present application can include one or more processors 12, and a memory 14.

[0100] The memory 14 in the server 10 can be a main memory (referred to as main memory or memory for short). It is used to store instruction information and / or data information represented by data signals, for example, to store data provided by the processor 12 (for example, as an operation result), and can also be used to realize data exchange between the processor 12 and an external storage device 16 (also referred to as auxiliary memory or external memory).

[0101] In some cases, the processor 12 can need to access the memory 14 to fetch data stored in the memory 14 or to modify data stored in the memory 14. Since the memory 14 has a slow access speed, in order to alleviate the speed gap between the processor 12 and the memory 14, the server 10 further includes a cache memory 18 coupled with the bus 11, which is used to cache some data in the memory 14 that can be repeatedly invoked, such as program data or packet data. The cache memory 18 is implemented by a type of storage device such as static random access memory (SRAM). The cache memory 18 can be a multi-level structure, for example, a three-level cache structure having a level one cache (L1 Cache), a level two cache (L2 Cache) and a level three cache (L3 Cache), or a cache structure of more than three levels or other types of cache structure. In some embodiments, a part of the cache memory 18 (for example, the level one cache, or the level one cache and the level two cache) can be integrated inside the processor 12 or integrated in the same system on chip as the processor 12.

[0102] Based on this, the processor 12 can include an instruction execution unit 121 and a storage control unit 122, etc. The instruction execution unit 121 initiates a write access request when executing some instructions that need to modify the memory, the write access request specifying write data to be written into the memory and a corresponding physical address; the storage control unit 122 is used to control whether to store the write data into the storage location pointed to by the physical address mapped by the write access request, that is, when some conditions are met, the write data is allowed to be stored into the storage location pointed to by the physical address mapped by the write access request; otherwise, the write data is not allowed to be stored into the storage location pointed to by the physical address mapped by the write access request.

[0103] In addition, the server 10 can further include a storage device 16 and a communication device 17. The storage device 16 is, for example, a hard disk, an optical disk, a flash memory, etc. for information access through a corresponding interface and coupled with the bus 11. The communication device 17 is used to communicate with other devices through various means, such as a network interface card, a Bluetooth module, a wireless transceiver, etc. Figure 1The communication device 17 can include one or more communication modules, for example. By way of example, the communication device 17 can include a wireless communication module adapted for a particular wireless communication protocol. For example, the communication device 17 can include a WLAN module for implementing Wi-Fi™ communications in compliance with the 802.11 standards promulgated by the Institute of Electrical and Electronics Engineers (IEEE). The communication device 17 can also include a WWAN module for implementing wireless wide area communications in compliance with cellular or other wireless wide area protocols. The communication device 17 can also include a Bluetooth module or other communication module employing other protocols, or other custom types of communication modules. The communication device 17 can also be a port for serial transmission of data.

[0104] Of course, the structure of the various servers 10 can vary depending on the motherboard, operating system, and instruction set architecture. For example, many servers 10 are currently provided with an input / output control hub connected between the bus 11 and the various input / output devices, which can be integrated within the processor 12 or independent of the processor 12.

[0105] Processor

[0106] Figure 3 is a schematic block diagram of the processor 12 in embodiments of the present application.

[0107] In some embodiments, each processor 12 can include one or more processor cores 120 for processing instructions, which processing and execution of instructions can be controlled by a user (e.g., through an application) and / or the system platform. In some embodiments, each processor core 120 can be configured to process a particular instruction set. In some embodiments, an instruction set can support a Complex Instruction Set Computing (CISC), a Reduced Instruction Set Computing (RISC), or a Very Long Instruction Word (VLIW) computing. Different processor cores 120 can each process a different or same instruction set. In some embodiments, a processor core 120 can also include other processing modules, such as a Digital Signal Processor (DSP) or the like. By way of example, Figure 3 The processor cores 1 to m, m being a natural number other than 0, are shown in

[0108] In some embodiments, Figure 2The illustrated cache memory 18 can be integrated in whole or in part in the processor 12. And according to different architectures, the cache memory 18 can be a single or multiple levels of internal cache memory located within and / or outside the individual processor cores 101 (e.g. Figure 3 The illustrated three-level cache memory L1 to L3, Figure 3 The illustrated cache memory 18 can be integrated in whole or in part in the processor 12. And according to different architectures, the cache memory 18 can be a single or multiple levels of internal cache memory located within and / or outside the individual processor cores 101 (e.g. Figure 3 As shown, the processor cores 1 to m share, for example, the third-level cache memory L3. The processor 12 can also include an external cache (not shown), and other cache structures can also be used as the external cache of the processor 12.

[0109] In some embodiments, as shown, Figure 3 The processor 12 can include a register file 126, which can include a plurality of registers for storing different types of data and / or instructions, as shown. The registers in the register file 126 can be of different types. For example, the register file 126 can include integer registers, vector registers, floating point registers, instruction registers, and pointer registers, etc. The registers in the register file 126 can be implemented using general-purpose registers or can be designed according to the actual needs of the processor 12.

[0110] The processor 12 is used to execute a sequence of instructions (i.e. a program). The process of the processor 12 executing each instruction includes the steps of fetching the instruction from the memory storing the instruction, decoding the fetched instruction, executing the decoded instruction, saving the result of the instruction execution, and so on, until all instructions in the instruction sequence are executed or a halt instruction is encountered.

[0111] To implement the above process, the processor 12 can include a fetch unit 124, an instruction decoding unit 125, an instruction issue unit 130, an instruction execution unit 121, and an instruction retirement unit 131, etc.

[0112] The fetch unit 124 is the start engine of the processor 12, which is used to move the instructions from the memory 14 to the instruction registers (which can be registers in the register file 126) and to receive the next fetch address or calculate the next fetch address according to the fetch algorithm, which can include, for example, incrementing the address or decrementing the address according to the instruction length. Figure 3 One of the registers in the register file 126 is used to store the instructions, as shown.

[0113] After fetching the instruction, the processor 12 enters the instruction decode stage, and the instruction decode unit 125 decodes the fetched instruction according to a predetermined instruction format to obtain the operand acquisition information required by the fetched instruction, so as to prepare for the operation of the instruction execution unit 121. The operand acquisition information is, for example, a pointer to an immediate number, a register or other software / hardware capable of providing a source operand.

[0114] The instruction issue unit 130 is usually present in a high-performance processor 12 between the instruction decode unit 125 and the instruction execution unit 121, and is used for scheduling and control of instructions to efficiently allocate each instruction to different instruction execution units 121, so that parallel operation of multiple instructions is possible. After the instruction is fetched, decoded and scheduled to the corresponding instruction execution unit 121, the corresponding instruction execution unit 121 starts to execute the instruction, i.e. performs the operation indicated by the instruction and implements the corresponding function. The embodiments of the present disclosure are mainly completed by the instruction issue unit 130 and the instruction execution unit 121. The specific structure of the instruction issue unit 130 and the instruction execution unit 121 will be described in detail below.

[0115] The instruction execution unit 121 includes a vector execution unit 1211, an arithmetic operation unit 1214, and a memory instruction execution unit 1215, which are respectively used to process different types of instructions. The arithmetic operation unit (ALU) 1214 is an operation unit for performing integer number operations and logical operations. The vector execution unit 1211 is an operation unit for performing vector operations. When executing a certain type of instruction (e.g. a memory access instruction), the instruction execution unit 121 needs to access the memory 14 to obtain the information stored in the memory 14 or provide the data needed to be written into the memory 14. Such an execution unit that executes a memory access instruction is called a memory instruction execution unit 1215. Although Figure 3 The above instruction execution units are only shown as examples in the embodiment, and those skilled in the art should understand that any instruction execution unit that can execute the function required by the instruction can also be included as needed.

[0116] The instruction retirement unit 131 is mainly used to write the execution result generated by the instruction execution unit 121 back to the corresponding storage location (e.g. a register in the processor 12), so that the subsequent instruction can quickly obtain the corresponding execution result from the storage location.

[0117] In the processor 12, each instruction execution unit 121 can run in parallel and output the corresponding execution result.

[0118] After the access instruction is fetched by the instruction fetch unit 124, the instruction decode unit 125 can decode the access instruction so that the source operand of the access instruction can be fetched. The decoded access instruction is provided to the corresponding instruction execution unit 121, which can perform corresponding operation on the source operand of the access instruction (e.g., the source operand stored in a register is operated by an arithmetic logic unit) to obtain the address information corresponding to the access instruction, and initiate a corresponding request according to the address information, such as an address translation request, a write access request, etc.

[0119] The source operand of the access instruction usually includes an address operand, which is operated by the memory control unit 122 to obtain the virtual address or physical address corresponding to the access instruction. The virtual address can be converted into a physical address. Through the memory control unit 122, the cache memory 18 and / or the memory 14 can be accessed according to the translated physical address.

[0120] According to different functions, the access instruction can include a load instruction and a store instruction. The execution process of the load instruction usually does not need to modify the information in the memory 14 or the cache memory 18, and the instruction execution unit 121 only needs to read the data stored in the memory 14, the cache memory 18 or an external storage device according to the address operand of the load instruction.

[0121] Unlike the load instruction, the source operand of the store instruction includes not only the address operand but also the data information, and the execution process of the store instruction usually needs to modify the memory 14 and / or the cache memory 18. The data information of the store instruction can point to the write data, which can be the execution result of an operation instruction, a load instruction, etc., or the data provided by a register or other storage unit in the processor 12, or an immediate number.

[0122] The detailed structure of the instruction emitting unit 130 and the vector execution unit 1211 in the embodiments of the present disclosure, and the implementation process of the embodiments of the present disclosure Figure 3

[0123] Chain execution is a case where, when a later vector instruction needs the result written by a previous vector instruction in a vector register as an operand for operation, instead of waiting for the previous vector instruction to be executed completely before execution, the instruction is divided into multiple microinstructions, and the execution result of the microinstruction that has been executed is output in advance to the later instruction, so that the later instruction can run if it gets the result of part of the microinstructions of the previous instruction. Compared with the scheme of waiting for the execution result of the entire previous instruction, the vector operation efficiency is improved. However, chain execution can easily cause problems for the number of valid elements (valid element number) in the free and open reduced instruction set architecture vector extension instruction set.

[0124] The free and open RISC architecture is a project initiated by the American computer holy land of Berkeley, and its biggest advantage is open and free. The architecture has the advantage of late development, and ARM and X-86 have developed for many years. Large-scale commercial use needs to consider forward compatibility, and the free and open RISC architecture has no historical burden, so the instruction set is very simple and the performance is very good. In the information society, it is often necessary to perform a large number of the same type of operations, such as processing the same data of a large number of users on the Internet. A large number of single instructions are needed to process, in order to avoid the overhead of such single instruction processing, vector operation instructions are generated. The data items involved in single operation are regarded as an element in the vector, and the batch single data operation result is generated at a time through this vector operation method. Based on this idea, a number of vector operation instructions are extended to the free and open RISC architecture, becoming the vector extension instruction set of the free and open RISC architecture. The effective element number comes from the vector extension instruction set of the free and open RISC architecture, which is one of the control register parameters, used to indicate the number of elements that a vector instruction needs to process and update. A vector instruction may not process and occupy all elements of the entire control register, and the occupied elements are called effective elements. Generally speaking, when a vector instruction is executed, on the one hand, it may need the result of the previous vector instruction execution, and on the other hand, it needs to refer to the effective element number for operation and back writing. The only fault priority instruction is different from the ordinary vector load instruction. When any effective element is loaded, the access error occurs, and the exception is responded. The only fault priority instruction only responds to the exception when the access error occurs in the 0th element (the lowest element), and if the 0th element does not occur, the priority element number is updated to the total element number without access error. The only fault priority instruction is the only instruction in the vector extension instruction set of the free and open RISC architecture that can modify the effective element number except the setvl / setvli instruction specially used to set the effective element number. Generally, the vector instruction only needs to determine the number of effective elements according to the setvl / setvli instruction, and the parameter setting instruction execution is simple and short, which will not cause performance bottleneck. However, the only fault priority vector load instruction is an instruction that may change the effective element number, and its execution delay is uncertain. The subsequent vector instruction must wait for the only fault priority vector load instruction to return whether the effective element number is updated before it can be executed correctly. This waiting greatly reduces the effect of chain execution.

[0125] Embodiments of the present disclosure are generated to solve the problem of low running efficiency of subsequent vector instructions when only fault-priority vector load instruction is involved in chain execution, which is mainly realized by the instruction issue unit 130 and the vector execution unit 1211. The internal structure of the instruction issue unit 130 and the implementation process of embodiments of the present disclosure are discussed in detail below.

[0126] As shown in Figure 11 The instruction issue unit 130 of embodiments of the present disclosure includes an instruction splitter 1301, a micro instruction index obtainer 1303, an index comparison subunit 1304, and a micro instruction issue controller 1305.

[0127] As described above, the instruction fetch unit 124 carries the instruction from the memory 14 to one of the instruction registers in the register file 26 for storing the instruction. Then, the instruction decoding stage is entered. The instruction decoding unit 125 decodes the fetched instruction according to the predetermined instruction format to obtain the operand obtaining information required by the fetched instruction, so as to prepare for the operation of the instruction execution unit 121. If the decoding finds that the instruction is a vector operation instruction, i.e., the to-be-executed vector instruction, the to-be-executed vector instruction is sent to the instruction issue unit 130 for the instruction issue to the instruction execution unit 121.

[0128] After the to-be-executed vector instruction enters the instruction issue unit 130, the instruction splitter 1301 splits the to-be-executed vector instruction into micro instructions. As described above, when the number of elements of the vector is large and the execution capability of the vector execution unit 1211 is limited, for the vector involved in the instruction, only a part of elements of the vector can be processed and the operation result of the part of elements can be generated each time, and the number of bits of the part of elements is DPLEN. Therefore, the part of the instruction involving the operation of the elements with DPLEN bits is divided to be a micro instruction.

[0129] When splitting, the instruction splitter 1301 can split the to-be-executed vector instruction into (VLEN*LMUL) / DPLEN micro-instructions. As described above, VLEN is the vector register bit width, LMUL is the number of vector registers occupied by the vector in the to-be-executed vector instruction, and DPLEN is the processing bit width of the vector execution unit. When splitting into (VLEN*LMUL) / DPLEN micro-instructions, DPLEN bits can be sequentially taken from the low to the high in the VLEN*LMUL bit width, as a micro-instruction. In this way, (VLEN*LMUL) / DPLEN micro-instructions are formed in total. For example, when VLEN=128 and LMUL=8, the vector instruction needs to process a width of VLEN*LMUL=128*8=1024, and the processing bit width DPLEN of the vector execution unit 1211 can only be 64 for cost and utilization efficiency considerations. At this time, the to-be-executed vector instruction needs to be split into VLEN*LMUL / DPLEN=1024 / 64=16 micro-instructions for step-by-step execution and write-back. The instruction splitter 1301 takes 64 bits from the low to the high in the 1024 bits according to the above principle, for subsequent processing.

[0130] The micro-instruction index obtainer 1303 obtains the valid element number index of the micro-instruction based on the element range involved by the split micro-instruction.

[0131] The valid element number indicates the number of elements processed and updated by a vector instruction. A vector instruction does not necessarily process and occupy all elements of the entire control register, and the processed and occupied elements are called valid elements. For example, if the control register can accommodate 16 elements, but the valid element number=11, it indicates that the vector instruction only processes elements 0-10, and elements 12-15 are idle.

[0132] The valid element number index is not the valid element number, but an index for the element range processed by the micro-instruction for comparison of the valid element number. It does not focus on elements, but a range of elements. For a normal vector instruction, the index reflects which interval of the vector register the element range processed by the split micro-instruction corresponds to. For a fail-only vector load instruction, it reflects the element range in which the valid element number set after execution of the micro-instruction split by the fail-only vector load instruction is located.

[0133] Since the only fault-preferred vector load instruction needs to be split into several micro-instructions for execution, it means that the element access and write-back of each micro-instruction is related to the split DPLEN, i.e. the first split micro-instruction writes back the lowest DPLEN bit width, and the second split micro-instruction writes back the next lowest DPLEN bit width. Correspondingly, if the valid element number of a certain only fault-preferred split micro-instruction needs to be updated due to a write-back failure, the updated element interval must be the element index range corresponding to the DPLEN data currently written back by the micro-instruction.

[0134] As shown in Figure 12 , assuming that the DPLEN is a bit width of 4 elements, DPLEN = 64, and SEW = 16. The split micro-instruction A-2 occurs an access error when writing back, and the error element must be between element 8 and element 11. Assuming that the access error occurs when writing back element 10, but it is not important which element in elements 8-11 has the access error, because the element access of them is elements 8-11, and the same element range corresponds to the same valid element number index. Similarly, assuming that the DPLEN is a bit width of 2 elements, DPLEN = 64, and SEW = 32. The split micro-instruction B-2 occurs an access error when writing back, and the error element must be between element 4 and element 5. Assuming that the access error occurs when writing back element 5, but it is not important which element in elements 4-5 has the access error, because the element access of them is elements 4-5, and the same element range corresponds to the same valid element number index.

[0135] Since the update of the valid element number index of the micro-instruction split from the above only fault-preferred vector load instruction can be determined according to the SEW, LMUL and DPLEN, other ordinary vector instructions can also use this feature to transmit part of the micro-instructions in advance, instead of waiting for the complete execution of the only fault-preferred vector load instruction. As long as the element range involved in the micro-instruction split from the subsequent ordinary vector instruction is lower than the element range in the only fault-preferred vector load instruction which is confirmed not to update the valid element number, the result of the micro-instruction corresponding to the element range which is confirmed not to update the valid element number in the only fault-preferred vector load instruction can be used to process the micro-instruction split from the subsequent ordinary vector instruction. For example, when the micro-instruction A-0 split from the only fault-preferred vector load instruction has returned information confirming that the valid element number will not be updated, it means that the valid element number cannot be updated to any value of elements 0-3, and the subsequent instruction can transmit and execute the micro-instruction processing only elements 0-3, and directly obtain the current valid element number value from the control register. Similarly, if the split instruction A-1 has returned information confirming that the valid element number will not be updated, the subsequent instruction can transmit and execute the micro-instruction processing only elements 4-7. In this way, the parallelism of instruction execution is improved.

[0136] As described above, when judging whether the micro-instruction after splitting of the subsequent normal vector instruction can be issued and executed in parallel, the consideration is whether the element range of the micro-instruction processing is lower than the element range in which the valid element number is confirmed not to be updated in the only-fault-priority vector load instruction, that is, one element, and thus it is meaningless to consider the valid element number alone, and an effective element number index is adopted, which represents an element range. In the element range, the effective element number index of the elements is the same. In this way, whether the micro-instruction after splitting of the subsequent normal vector instruction can be issued and executed in parallel can be determined by comparing the effective element number index of the element range of the micro-instruction after splitting of the subsequent normal vector instruction with the first index (that is, the effective element number index of the micro-instruction after splitting of the only-fault-priority vector load instruction which has not been processed yet).

[0137] To this end, an effective element number index encoding mechanism is designed in the embodiments of the present disclosure to identify the element range involved in the current micro-instruction after splitting (including the micro-instruction after splitting of the normal vector instruction and the micro-instruction after splitting of the only-fault-priority vector load instruction), and the effective element number index obtained based on the element range involved in the current micro-instruction after splitting of the normal vector instruction is compared with the first index (the effective element number index of the micro-instruction after splitting of the only-fault-priority vector load instruction), and only when it is confirmed that the effective element number index of the micro-instruction after splitting of the normal vector instruction is less than the first index, the execution can be transmitted, otherwise, the update of the valid element number of the corresponding micro-instruction after splitting of the only-fault-priority vector load instruction needs to be confirmed before the transmission.

[0138] In the free and open reduced instruction set architecture vector extension instruction set, the maximum LMUL can be set to 8, that is, one vector instruction needs to process and write back at most 8 vector registers. In this way, the total number of effective element number indexes that can be set is INDEX_NUM = VLEN*8 / DPLEN. If the effective element number index is represented by binary, at least INDEX_LEN = log2(INDEX_NUM) is needed to represent the effective element number index. VLEN*8 / DPLEN is only the number of effective element number indexes that can be set at most, and in fact, the vector instruction often does not need to write back all 8 vector registers. If 4 are written back, only VLEN*4 / DPLEN effective element number indexes are needed. If 2 are written back, only VLEN*2 / DPLEN effective element number indexes are needed. In summary, if it is assumed that VREG_NUM is the number of vector registers to be written back by the vector instruction to be executed, the effective element number index needed is VLEN*VREG_NUM / DPLEN.

[0139] In one embodiment of the present disclosure, for the case that the number of vector registers VREG_NUM to be written back by the to-be-executed vector instruction is less than 8, a non-uniform indexing manner is adopted instead of a uniform indexing manner, so that no matter what the value of VREG_NUM is, the element range of the higher bit of the scheme under different VREG_NUM is maintained at a close effective element number index, and the element range of the lower bit is maintained at a close effective element number index. That is, if VREG_NUM is small, the effective element number index value coded by two adjacent element ranges is enlarged; if VREG_NUM is large, the effective element number index value coded by two adjacent element ranges is reduced. In this way, under different VREG_NUM values, as long as the element range is at a roughly consistent position ratio within the overall element range, it will be coded into a similar effective element number index value, so that the effective element number index of the microinstruction after the vector instruction is split and the first index are compared to have a reasonable basis, and the comparison will not be affected unreasonably because the VREG_NUM of the subsequent vector instruction and the previous fault-priority-only vector load instruction is different.

[0140] Specifically, in one embodiment, for the normal vector instruction after the fault-priority-only vector load instruction, the microinstruction index obtainer 1303 encodes the element range involved in the split microinstruction into an effective element number index based on the following formula 1:

[0141] vl_index(i) = 8*(i+1) / VREG_NUM - 1 Formula 1

[0142] wherein, vl_index(i) is the effective element number index, VREG_NUM is the number of vector registers to be written back by the to-be-executed vector instruction, i is the serial number of the element range, i = 0, 1, 2, …, VLEN*VREG_NUM / DPLEN-1 (increasing in the order of low to high bits), VLEN is the vector register bit width, and DPLEN is the processing bit width of the vector execution unit.

[0143] Since the vector register bit width is VLEN, the number of vector registers to be written back by the to-be-executed vector instruction is VREG_NUM, and the processing bit width of the vector execution unit is DPLEN, the total vector register group to be written back is divided into VLEN*VREG_NUM / DPLEN element ranges according to DPLEN, wherein the serial number of the lowest bit element range is 0, the serial number of the second lowest bit element range is 1, …, and the serial number of the highest bit element range is VLEN*VREG_NUM / DPLEN-1.

[0144] If VREG_NUM = 8, the element range number is the valid element number index, because substituting VREG_NUM = 8 into equation 1, we get valid element number_index(i) = i. When the valid element number index is expressed in binary, the micro-instructions corresponding to the lowest number of element ranges of the to-be-executed vector instruction are encoded into the valid element number index of 0000, and the valid element number index increases by 0001 for each higher number of element ranges, and the highest can increase to 1111, as shown in Figure 12 .

[0145] If VREG_NUM = 4, substituting VREG_NUM = 4 into equation 1, we get valid element number_index(i) = 2i + 1. When i = 0, the valid element number index is 1; when i = 1, the valid element number index is 3; when i = 2, the valid element number index is 5; when i = 3, the valid element number index is 7; and when i = 7, the valid element number index is 15. The possible binary valid element number index is 0001, 0011, 0101, 0111,..., 1111. The micro-instructions corresponding to the lowest number of element ranges of the to-be-executed vector instruction are encoded into the valid element number index of 0001, and the valid element number index increases by 0010 for each higher number of element ranges, and the highest can increase to 1111, as shown in Figure 12 . As can be seen, although VREG_NUM is different, the valid element number index corresponding to the high-bit element range is similar to that under VREG_NUM = 8, and the valid element number index corresponding to the low-bit element range is also similar to that under VREG_NUM = 8, except that the distance between the valid element number indexes corresponding to adjacent element ranges is enlarged.

[0146] If VREG_NUM = 2, substituting VREG_NUM = 2 into equation 1, we get valid element number_index(i) = 4i + 3. When i = 0, the valid element number index is 3; when i = 1, the valid element number index is 7; when i = 2, the valid element number index is 11; when i = 3, the valid element number index is 15. The possible binary valid element number index is 0011, 0111, 1011, 1111. The micro-instructions corresponding to the lowest number of element ranges of the to-be-executed vector instruction are encoded into the valid element number index of 0011, and the valid element number index increases by 0100 for each higher number of element ranges, and the highest can increase to 1111, as shown in Figure 12As shown in the table, it can be seen that although VREG_NUM is different, the effective element number index corresponding to the high bit element range is similar to that under VREG_NUM = 4, and the effective element number index corresponding to the low bit element range is also similar to that under VREG_NUM = 4, only the distance of the effective element number index corresponding to the adjacent element range is further expanded.

[0147] If VREG_NUM = 1, VREG_NUM = 1 is substituted into formula 1 to obtain effective element number_index(i) = 8i + 7. When i = 0, the effective element number index is 7; when i = 1, the effective element number index is 15. The possible binary effective element number index is 0111, 1111. The element range corresponding to the lowest serial number of the microinstruction divided by the vector instruction to be executed is encoded into the effective element number index 0111, and the effective element number index is increased by 1000 for each high serial number of the element range, and the highest can be increased to 1111, as shown in the table. Figure 13 As shown in the table, it can be seen that although VREG_NUM is different, the effective element number index corresponding to the high bit element range is similar to that under VREG_NUM = 4, and the effective element number index corresponding to the low bit element range is also similar to that under VREG_NUM = 4, only the distance of the effective element number index corresponding to the adjacent element range is further expanded.

[0148] The above encoding increment rule can be understood in the way of fractional ratio. When 8 vector registers are written back, each 64-bit element range accounts for 1 / 16 of the total element range, so the increment is 1 / 16 of the maximum increment 16, that is, 1 each time; when 4 registers are written back, each 64-bit element range accounts for 1 / 8 of the element range, so the increment is 1 / 8 of the maximum increment 16, that is, 2 each time; when 2 registers are written back, each 64-bit element range accounts for 1 / 4 of the total element range, so the increment is 1 / 4 of the maximum increment 16, that is, 4 each time; when 1 register is written back, each 64-bit element range accounts for 1 / 2 of the total element range, so the increment is 1 / 2 of the maximum increment 16, that is, 8 each time.

[0149] This encoding method does not encode the element range based on the absolute total number of elements, but rather on the proportion of the element range involved in each split microinstruction to the total element range. This ignores the changes in the total number of elements caused by SEW. Furthermore, using element proportions is more beneficial for handling vector extension instructions of certain special free and open-source Reduced Instruction Set Architectures, such as narrowing / widening instructions and some masked instructions. Although the total number of elements in these instructions remains the same, the number of write-back registers differs from ordinary instructions due to changes in SEW. The above encoding method can directly encode these instructions regardless of SEW changes, simplifying the process. While it is also possible to directly encode the effective element count index based on the sequence number of the element range involved in the microinstruction, the number of elements changes with SEW. The total number of indices resulting from the total number of elements is VLEN*VREG_NUM / SEW. When SEW is less than DPLEN (which is usually the case), a wider index width is required, and the encoding process must consider SEW.

[0150] like Figure 13 As shown, Figure 13 Instruction B is a normal vector instruction. PLEN is a 2-element bit width. Each microinstruction that divides instruction B involves 2 elements. When the lowest two microinstructions are executed, the element range involved by each microinstruction corresponds to the element range 0-3 (four adjacent elements form one element range), and the valid element count index is 0001. When the 3rd and 4th microinstructions from low to high are executed, the element range involved by each microinstruction corresponds to the element range 4-7, and the valid element count index is 0011.

[0151] Next, the index comparison subunit 1304 compares the encoded valid element count index with the first index, which is the valid element count index of the fault-only microinstructions that the vector execution unit 1211 has not yet finished processing. If multiple fault-only microinstructions have not been processed, they must be compared with the valid element count index of these multiple fault-only microinstructions. Only if all of them are less than the valid element count index can the instruction be issued to the vector execution unit 1211 for execution.

[0152] The vector execution unit 1211 includes a vector operation subunit 1213 and a first index recorder 1212. The vector operation subunit 1213 executes micro-instructions into which the vector instruction to be executed is decomposed and issued by the instruction issuing unit 130. The first index recorder 1212 records a first index and issues the first index in response to a request from the instruction issuing unit 130.

[0153] likeFigure 3 As shown, instruction A is a fault-only vector load instruction. Instruction B is a widening instruction that follows. Each split instruction of instruction A and instruction B processes and writes back a result of DPLEN elements. For instruction A, DPLEN is a bit width of 4 elements. Assuming that one of the micro-instructions of instruction A after splitting is micro-instruction A-2, according to the rule above, the valid element number index encoding is 0101. The split micro-instructions that have been launched to vector operator unit 1213 are micro-instruction A-0 and micro-instruction A-1. Micro-instruction B-0 and micro-instruction B-1 of instruction B split, because they operate on the element range of elements 0-3, according to the rule above, the valid element number index encoding is 0001. Index comparison sub-unit 1304 requests the valid element number index of A-0, A-1,... that are not executed from first index register 1212. Since the encoded valid element number index 0001 is not less than the index of A-0, A-0 needs to be executed to confirm the valid element number update information before the launch. For micro-instruction B-2 and B-3 of instruction B split, according to the rule above, the valid element number index encoding is 0011. Index comparison sub-unit 1304 requests the valid element number index of A-0, A-1,... that are not executed from first index register 1212. Since 0011 is not less than the index of A-0 and A-1,... 0001 and 0011, A-0 and A-1 need to be executed to confirm the valid element number update information before the launch. The valid element number index of micro-instruction B-4 and B-5 of instruction B split is 0101. Index comparison sub-unit 1304 requests the valid element number index of A-0, A-1, A-2,... that are not executed from first index register 1212. Since it is not less than the index of A-0, A-1, and A-2, even if A-0 and A-1 have been executed in vector operator unit 1213, micro-instruction A-2 cannot be executed and launched in advance, and needs to wait for A-2 to be launched and executed.

[0154] If the encoded valid element number index is less than the first index, micro-instruction launch controller 1305 sends the split micro-instruction to vector operator unit 1213 in vector execution unit 1211 for execution.

[0155] In the above embodiment, only the determination of whether the valid element number index is less than the first index is made. In another embodiment, in addition to the above determination, a determination of whether the first micro-instruction is executed is also made. For example, if the valid element number index is less than the first index, micro-instruction launch controller 1305 sends the split micro-instruction to vector operator unit 1213 in vector execution unit 1211 for execution. If the valid element number index is not less than the first index, micro-instruction launch controller 1305 waits until the first micro-instruction is executed to confirm the valid element number update information before sending the split micro-instruction to vector operator unit 1213 in vector execution unit 1211 for execution. Figure 9As shown, the instruction issue unit 130 further comprises an operand dependency judgment subunit 1302 for determining whether the first microinstruction is executed, wherein the operand of the split microinstruction depends on the first microinstruction. The microinstruction issue controller 1305 sends the split microinstruction to the vector execution unit 1211 for execution only when the first microinstruction has been executed and the valid element number index is less than the first index.

[0156] The operand of the split microinstruction depends on the execution result of the first microinstruction. That is, the split microinstruction can be executed only after the execution result of the first microinstruction is obtained. Before executing a split microinstruction, it is determined whether the preceding microinstruction on which the split microinstruction depends has been executed, which is a general condition required for chain execution. After the general condition is determined, it is further determined whether the encoded valid element number index is less than the first index, which is a specific condition of the present embodiment. Thus, the split microinstruction is executed without waiting for the preceding only-failure-first vector load instruction to be fully executed and return the updated valid element number, which greatly improves the execution efficiency of the subsequent vector instructions after the only-failure-first vector load instruction in chain execution.

[0157] If the first microinstruction is not executed or the encoded valid element number index is not less than the first index, the microinstruction issue controller 1305 cannot send the split microinstruction to the vector operation subunit 1213 in the vector execution unit 1211 for execution, but keeps the split microinstruction until the condition is met. Since the operand dependency judgment subunit 1302, the index comparison subunit 1304 and the microinstruction issue controller 1305 are periodically executed, if the condition is not met in a clock cycle, the condition can be repeatedly determined in each subsequent clock cycle. Until the condition is met, the split microinstruction is sent to the vector operation subunit 1213 for execution.

[0158] In addition, the vector execution unit 1211 can comprise a plurality of vector operation subunits 1213. The microinstruction issue controller 1305 can send a plurality of split microinstructions to the plurality of vector operation subunits 1213 for parallel execution to improve execution efficiency.

[0159] The operand dependency judgment subunit 1302 determines whether the first microinstruction is executed, wherein the operand of the split microinstruction depends on the first microinstruction.

[0160] Operands are the entities on which operators in a vector instruction are performed; they specify the quantities to be calculated in the instruction. For example, the vector multiplication instruction `vmul.vv vr4,vr0,vr3` means multiplying vectors `vr4`, `vr0`, and `vr3`, and using the resulting vector as the new vector `vr4`. Here, `vr4`, `vr0`, and `vr3` are all operands required by this vector multiplication instruction.

[0161] If an operand is the result of a microinstruction preceding the current microinstruction, then that preceding microinstruction is the first microinstruction. For example, before `vmul.vv vr4,vr0,vr3`, there is a vector addition instruction `vadd.vvvr0,vr1,vr2`, which adds vectors `vr0`, `vr1`, and `vr2`, and the resulting vector is the new vector `vr0`. Therefore, the operand `vr0` required in the vector multiplication instruction `vmul.vv vr4,vr0,vr3` is the result of `vadd.vv vr0,vr1,vr2`, and `vadd.vv vr0,vr1,vr2` is the first microinstruction. Assuming the vector execution unit 1211 can process operations on 4 elements at a time, the microinstructions for processing elements 4-7 of the vector multiplication instruction `vmul.vv vr4,vr0,vr3` depend on the execution result of the microinstructions for elements 0-3 of the vector addition instruction `vadd.vv vr0,vr1,vr2`. Therefore, when the operand dependency judgment subunit 1302 executes the microinstructions for elements 4-7 of the vector multiplication instruction `vmul.vv vr4,vr0,vr3`, it must determine whether the microinstructions for elements 0-3 of the vector addition instruction `vadd.vv vr0,vr1,vr2` have been completed. If so, it can proceed to the next judgment. Otherwise, it cannot proceed to the next judgment because the dependent microinstructions have not been processed, and the conditions for chained execution are not met. Since this step is executed periodically, although the microinstructions on which the operands required by the split microinstructions depend may not be completed in the current clock cycle, they may be completed in the next clock cycle.

[0162] like Figure 14As shown, assuming instruction B is a vector multiplication instruction vmul.vv vr4, vr0, vr3, micro instruction B-1 is the micro instruction for element 0-3 processing in instruction B, B-2 is the micro instruction for element 4-7 processing in instruction B, B-3 is the micro instruction for element 8-11 processing in instruction B,... instruction A is a vector addition instruction vadd.vv vr0, vr1, vr2, micro instruction A-1 is the micro instruction for element 0-3 processing in instruction A, A-2 is the micro instruction for element 4-7 processing in instruction A, A-3 is the micro instruction for element 8-11 processing in instruction A,... in clock cycle 1, micro instruction A-1 can be issued for processing. In clock cycle 2, micro instruction A-2 can be processed. Meanwhile, the previous micro instruction A-1 on which micro instruction B-1 depends has been processed, micro instruction B-1 can also be processed. Therefore, micro instructions A-2 and B-1 can be processed simultaneously in clock cycle 2. Micro instructions A-3 and B-2 can be processed simultaneously in clock cycle 3,... achieving the effect of chain execution, effectively reducing the waiting delay caused by operand dependency.

[0163] When the operand dependency judgment subunit 1302 determines whether the micro instructions split from the vector instruction have been executed, the operand dependency judgment subunit 1302 can first acquire the operands in the split micro instructions, then acquire the micro instructions that generate the operands in the previous split micro instructions, and finally determine whether the acquired micro instructions have been executed. For example, for the micro instruction for elements 4-7 of the vector multiplication instruction vmul.vv vr4, vr0, vr3, the operand dependency judgment subunit 1302 acquires the operands vr4, vr0, and vr3, and then finds the micro instructions for elements 0-3 of the vector addition instruction vadd.vv vr0, vr1, vr2 split from the previous split micro instructions, which involve vr4, vr0, and vr3. Finally, the operand dependency judgment subunit 1302 determines that the micro instruction for elements 0-3 of the vector addition instruction vadd.vv vr0, vr1, vr2 split from the previous split micro instructions has been executed.

[0164] As shown in FIG. 13, according to one embodiment of the present disclosure, a vector execution acceleration method is provided, which is executed by an instruction issue unit 130, and includes the following steps. ​ As shown in FIG. 13, according to one embodiment of the present disclosure, a vector execution acceleration method is provided, which is executed by an instruction issue unit 130, and includes the following steps.

[0165] Step 310: Splitting a vector instruction to be executed into micro instructions.

[0166] Step 320: Acquiring an effective element number index of the micro instruction based on an element range involved in the split micro instruction.

[0167] Step 330: Comparing the acquired effective element number index with a first index, the first index being an effective element number index of only fail-first micro instructions that have not been processed.

[0168] Step 340, in the case that the valid element number index is less than the first index, sending the split micro-instruction to the vector execution unit for execution.

[0169] Optionally, before step 340, the method further comprises: determining whether the first micro-instruction has been executed, wherein the operand in the split micro-instruction depends on the first micro-instruction; and step 340 comprises: in the case that the first micro-instruction has been executed and the valid element number index is less than the first index, sending the split micro-instruction to the vector execution unit for execution.

[0170] Optionally, step 340 comprises calculating the valid element number index according to the following formula:

[0171] vl_index(i) = 8*(i+1) / VREG_NUM - 1,

[0172] wherein vl_index(i) is the valid element number index, VREG_NUM is the number of vector registers to be written back by the to-be-executed vector instruction, i is the serial number of the element range, i = 0, 1, 2, …, VLEN*VREG_NUM / DPLEN-1, wherein VLEN is the bit width of the vector register, and DPLEN is the processing bit width of the vector execution unit.

[0173] Optionally, if VREG_NUM = 8, the valid element number index corresponding to the element range with the lowest serial number is 0000, and the valid element number index increases by 0001 for each higher serial number of the element range.

[0174] Optionally, if VREG_NUM = 4, the valid element number index corresponding to the element range with the lowest serial number is 0001, and the valid element number index increases by 0010 for each higher serial number of the element range.

[0175] Optionally, if VREG_NUM = 2, the valid element number index corresponding to the element range with the lowest serial number is 0011, and the valid element number index increases by 0100 for each higher serial number of the element range.

[0176] Optionally, if VREG_NUM = 1, the valid element number index corresponding to the element range with the lowest serial number is 0111, and the valid element number index increases by 1000 for each higher serial number of the element range.

[0177] Optionally, the determining whether the first micro-instruction has been executed comprises:

[0178] acquiring the operand in the split micro-instruction;

[0179] acquire the micro-instruction that generates the operand in the micro-instruction split before;

[0180] determine whether the acquired micro-instruction is executed.

[0181] Optionally, after determining whether the first micro-instruction is executed, the method further comprises: in the case that the first micro-instruction is not executed, or the valid element number index is less than the first index, keeping the split micro-instruction.

[0182] The present application also discloses a computer readable storage medium including computer executable instructions stored thereon, which, when executed by a processor, cause the processor to perform the method of each embodiment described herein.

[0183] It should be appreciated that the above description is only preferred embodiments of the present application, and is not intended to limit the present application. For those skilled in the art, there are many variations of the embodiments of the present application. Any modification, equivalent replacement, improvement, etc. within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0184] It should be understood that each of the embodiments in the present specification is described in a progressive manner, and the same or similar parts of each embodiment can be referred to each other, and each embodiment mainly describes the difference from other embodiments. Especially, for the method embodiments, since the method is basically similar to the method described in the device and system embodiments, the description is relatively simple, and the relevant parts can refer to the part of the description of other embodiments.

[0185] It should be understood that the above describes the specific embodiments of the present specification. Other embodiments are within the scope of the claims. In some cases, the actions or steps recited in the claims can be performed in an order different from the embodiments and still achieve the desired result. In addition, the processes depicted in the figures do not necessarily require the particular order shown or sequential order to achieve the desired results. In certain implementations, multi-task processing and parallel processing are possible or can be advantageous.

[0186] It should be understood that the element described in the singular form or only shown in the figure in the present specification does not represent the number of the element limited to one. In addition, the modules or elements described or shown as separated in the present specification can be combined as a single module or element, and the modules or elements described or shown as single in the present specification can be split into multiple modules or elements.

[0187] It is also to be understood that the terminology and phraseology employed herein is for the purpose of description and the specification one or more embodiments of the present application should not be limited to the terms used. The use of such terms and expressions does not therefore admit of any limitation on the scope of the application, it being recognized that the various needs, modifications and equivalents will be apparent to the skilled person and are to be included within the scope of a claim. Other modifications, variations and alternatives are also possible. Accordingly, the claims should be regarded as encompassing all such equivalents.

Claims

1. A command issuing unit, comprising: An instruction splitter is used to break down a vector instruction to be executed into micro-instructions; The microinstruction index retriever is used to obtain the effective element count index of the microinstruction based on the element range involved in the split microinstruction. The effective element refers to the element processed by the vector instruction and occupied by the vector register. The effective element count index is used to reflect which interval of the vector register the element range involved in the microinstruction corresponds to. The index comparison subunit is used to compare the obtained valid element count index with the first index, which is the valid element count index of the fault-only microinstruction that has not yet been processed. The fault-only microinstruction is a microinstruction divided into the fault-only vector loading instruction. The fault-only vector loading instruction will only respond to the exception when an access error occurs when loading the 0th element. If an access error occurs in a non-0th element, the valid element count will be updated to the total number of elements processed without access errors. A microinstruction dispatch controller is used to send the split microinstructions to the vector execution unit for execution when the number of valid elements is less than the first index.

2. The command issuing unit according to claim 1 further includes: An operand dependency determination subunit is used to determine whether the first microinstruction has been executed, wherein the operands in the split microinstruction depend on the first microinstruction; Specifically, the microinstruction dispatch controller sends the split microinstruction to the vector execution unit for execution only after the first microinstruction has been executed and the number of valid elements is less than the first index.

3. The command issuing unit according to claim 1, wherein, The microinstruction index retriever obtains the index of the number of valid elements of the microinstruction based on the element range involved in the split microinstruction according to the following formula: vl_index(i) = 8*(i+1) / VREG_NUM – ​​1, Where vl_index(i) is the index of the number of valid elements, VREG_NUM is the number of vector registers to be written back by the vector instruction to be executed, and i is the index of the element range, i=0,1,2,……,VLEN*VREG_NUM / DPLEN-1, where VLEN is the bit width of the vector register and DPLEN is the processing bit width of the vector execution unit.

4. The command issuing unit according to claim 3, wherein, If VREG_NUM=8, the index of the number of valid elements corresponding to the element range with the lowest sequence number is 0000. For each higher sequence number in the element range, the index of the number of valid elements increases by 0001.

5. The command issuing unit according to claim 3, wherein, If VREG_NUM=4, the index of the number of valid elements corresponding to the element range with the lowest sequence number is 0001. For each higher sequence number in the element range, the index of the number of valid elements increases by 0010.

6. The command issuing unit according to claim 3, wherein, If VREG_NUM=2, the index of the number of valid elements corresponding to the element range with the lowest sequence number is 0011. For each higher sequence number in the element range, the index of the number of valid elements increases by 0100.

7. The command issuing unit according to claim 3, wherein, If VREG_NUM=1, the index of the number of valid elements corresponding to the element range with the lowest sequence number is 0111. For each higher sequence number in the element range, the index of the number of valid elements increases by 1000.

8. The command issuing unit according to claim 1, wherein, The instruction splitter splits the vector instruction to be executed into (VLEN·LMUL) / DPLEN microinstructions, where VLEN is the vector register bit width, LMUL is the number of vector registers occupied by the vector in the vector instruction to be executed, and DPLEN is the processing bit width of the vector execution unit.

9. The command issuing unit according to claim 2, wherein, The operand correlation determination subunit determines whether the first microinstruction has been executed completely in the following manner: Retrieve the operands from the split microinstructions; Obtain the microinstruction that generates the operand from the previously separated microinstructions; Determine whether the acquired micro-instructions have been executed.

10. The command issuing unit according to claim 2, wherein, The microinstruction issuing controller retains the split microinstruction if the first microinstruction has not been completed or if the number of valid elements is less than the first index.

11. The command issuing unit according to claim 2, wherein, The vector execution unit includes multiple vector operation subunits, and the microinstruction dispatch controller sends the split microinstructions in parallel to the multiple vector operation subunits for execution.

12. A vector execution unit, comprising: The vector operation subunit is used to execute the micro-instructions after the vector instruction to be executed is decomposed. A first index recorder is configured to record a first index and, in response to a request from the instruction issuing unit according to any one of claims 1 to 11, issue the first index, wherein the first index is the valid element count index of the fault-only microinstruction that has not yet been processed by the vector operation subunit, the valid element refers to the element processed and occupied by the vector instruction in the vector register, the valid element count index is used to reflect which interval of the vector register the element range involved in the microinstruction corresponds to, the fault-only microinstruction is a microinstruction divided from the fault-only vector load instruction, the fault-only vector load instruction will only respond to an exception when an access error occurs while loading the 0th element, and if an access error occurs in a non-0th element, the valid element count will be updated to the total number of elements processed without access errors.

13. A processing unit, comprising: The instruction fetch unit is used to fetch the vector instruction to be executed. An instruction decoding unit is used to decode the vector instruction to be executed; The command issuing unit according to any one of claims 1-11; The vector execution unit according to claim 12.

14. A computing device, comprising: The processing unit according to claim 13; The memory, coupled to the processing unit, stores the vector instructions to be executed.

15. A data center comprising the computing device according to claim 14.

16. A vector execution acceleration method, comprising: Break down the vector instructions to be executed into micro-instructions; Based on the range of elements involved in the split microinstruction, the effective element count index of the microinstruction is obtained. The effective element refers to the element processed and occupied by the vector instruction in the vector register. The effective element count index is used to reflect which interval of the vector register the range of elements involved in the microinstruction corresponds to. The index of the number of valid elements is compared with the first index, which is the index of the number of valid elements of the fault-only micro-instruction that has not yet been processed. The fault-only micro-instruction is a micro-instruction divided into the fault-only vector loading instruction. The fault-only vector loading instruction will only respond to the exception when an access error occurs when loading the 0th element. If an access error occurs in a non-0th element, the number of valid elements will be updated to the total number of elements that have been processed without access errors. If the number of valid elements is less than the first index, the split micro-instructions are sent to the vector execution unit for execution.

17. The method according to claim 16, wherein, Before sending the split microinstructions to the vector execution unit for execution, the method further includes: determining whether the first microinstruction has been executed, wherein the operands in the split microinstructions depend on the first microinstruction; The step of sending the split micro-instructions to the vector execution unit for execution when the number of valid elements is less than the first index includes: sending the split micro-instructions to the vector execution unit for execution only when the first micro-instruction has been executed and the number of valid elements is less than the first index.

18. The method according to claim 16, wherein, The step of obtaining the effective element count index of the microinstruction based on the element range involved in the split microinstruction includes calculating the effective element count index according to the following formula: vl_index(i) = 8*(i+1) / VREG_NUM – ​​1, Where vl_index(i) is the index of the number of valid elements, VREG_NUM is the number of vector registers to be written back by the vector instruction to be executed, and i is the index of the element range, i=0,1,2,…..,VLEN*VREG_NUM / DPLEN-1, where VLEN is the bit width of the vector register and DPLEN is the processing bit width of the vector execution unit.

19. The method according to claim 18, wherein, If VREG_NUM=8, the index of the number of valid elements corresponding to the element range with the lowest sequence number is 0000. For each higher sequence number in the element range, the index of the number of valid elements increases by 0001.

20. The method according to claim 18, wherein, If VREG_NUM=4, the index of the number of valid elements corresponding to the element range with the lowest sequence number is 0001. For each higher sequence number in the element range, the index of the number of valid elements increases by 0010.

21. The method according to claim 18, wherein, If VREG_NUM=2, the index of the number of valid elements corresponding to the element range with the lowest sequence number is 0011. For each higher sequence number in the element range, the index of the number of valid elements increases by 0100.

22. The method according to claim 18, wherein, If VREG_NUM=1, the index of the number of valid elements corresponding to the element range with the lowest sequence number is 0111. For each higher sequence number in the element range, the index of the number of valid elements increases by 1000.

23. The method according to claim 17, wherein, Determining whether the first microinstruction has been executed includes: Retrieve the operands from the split microinstructions; Obtain the microinstruction that generates the operand from the previously separated microinstructions; Determine whether the acquired micro-instructions have been executed.

24. The method of claim 17, wherein, After determining whether the first microinstruction has been executed, the method further includes: If the first microinstruction has not been completed or the number of valid elements is less than the first index, the split microinstruction is retained.

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