A method and structure for prefetching data

Abstract

A data prefetching method and structure are applied to a cache connected between a central processing unit (CPU) and a main memory. A first effective bus width of the main memory and a second effective bus width of the CPU are set based on the ratio of the data read time of the main memory to the operating clock cycle of the CPU. The data prefetching method includes the following steps: receiving processor bus address data sent by the CPU; and reading data from the main memory into the cache based on the processor bus address data, the first effective bus width, and the second effective bus width. Based on the ratio of the data read time of the main memory to the operating clock cycle of the CPU, the ratio of the first effective bus width of the main memory to the second effective bus width of the CPU is adjusted so that when the previous data processing is completed, the new data has been read from the main memory into the cache, thereby achieving a pipeline processing method and solving the problem of low cache operation efficiency.

Description

Technical Field

[0001] The present invention belongs to the field of cache, and in particular relates to a method and structure for prefetching data. Background Art

[0002] A cache is a storage medium located between the central processing unit (CPU) and main memory. Its capacity is smaller than that of main memory, but its exchange rate is faster. Caches were created primarily to address the mismatch between the CPU's computing speed and the main memory's read rate. Because the CPU's computing speed is much faster than the main memory's read rate, the CPU spends a significant amount of time waiting for data to arrive or writing it to the main memory. Existing cache prefetching structures and methods are inflexible and cannot adapt to any CPU-to-main memory ratio, resulting in low cache efficiency. Summary of the Invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present invention provides a data pre-fetching method, which solves the problem of low operating efficiency of the cache.

[0004] The present invention also proposes a pre-fetch data structure.

[0005] The data prefetching method according to the first embodiment of the present invention is applied to a buffer, the buffer being connected between a central processing unit and a main memory, wherein a first effective bus width of the main memory and a second effective bus width of the central processing unit are set according to a ratio of a data read time of the main memory to a working clock cycle of the central processing unit;

[0006] The method for prefetching data comprises the following steps:

[0007] receiving processor bus address data sent by the central processing unit;

[0008] The data in the main memory is read into the buffer according to the processor bus address data, the first effective bus width and the second effective bus width.

[0009] The data prefetching method according to an embodiment of the present invention has at least the following technical effects: first, based on the ratio of the data read time of the main memory to the operating clock cycle of the central processing unit, the ratio of the first effective bus width of the main memory to the second effective bus width of the central processing unit is adjusted, so that the data processing cycle in the cache is adapted to the data read time of the main memory and the operating clock cycle of the central processing unit. When data needs to be read from the main memory, the cache first receives the processor bus address data sent by the central processing unit, and then reads the data from the main memory into the cache based on the processor bus address data, the first effective bus width, and the second effective bus width. This can achieve the goal that when the previous data processing is completed, the new data has been read from the main memory into the cache, thereby achieving a pipeline processing method and solving the problem of low cache operation efficiency.

[0010] According to some embodiments of the present invention, if the ratio of the data read time of the main memory to the working clock cycle of the central processing unit is a non-integer, the ratio of the first effective bus width to the second effective bus width is set by the following steps:

[0011] Calculating the ratio of the data reading time of the main memory to the working clock cycle of the central processing unit, and obtaining an integer bus adjustment ratio by rounding;

[0012] The first effective bus width and the second effective bus width are set according to the bus adjustment ratio so that a ratio of the first effective bus width to the second effective bus width is equal to the bus adjustment ratio.

[0013] According to some embodiments of the present invention, reading the data in the main memory into the cache according to the processor bus address data, the first effective bus width, and the second effective bus width comprises the following steps:

[0014] Determine a hold time between a time of receiving the processor bus address data this time and a time of receiving the processor bus address data last time;

[0015] If the holding time is less than the data reading time of the main memory, a waiting signal is sent to the central processing unit; the waiting signal is used to make the central processing unit wait until the holding time is greater than or equal to the data reading time of the main memory;

[0016] If the holding time is greater than or equal to the data reading time of the main memory, the data in the main memory is read into the buffer according to the processor bus address data, the first effective bus width and the second effective bus width received this time.

[0017] According to some embodiments of the present invention, determining the holding time between the moment of receiving the processor bus address data this time and the moment of last receiving the processor bus address data comprises the following steps:

[0018] Determine the number of working cycles that the central processing unit has worked between the time of receiving the processor bus address data this time and the time of receiving the processor bus address data last time;

[0019] The product of the number of working cycles and the working clock cycle of the central processing unit is calculated and recorded as the holding time.

[0020] According to some embodiments of the present invention, reading the data in the main memory into the cache according to the processor bus address data, the first effective bus width, and the second effective bus width further includes the following steps:

[0021] Determining a continuity state between the processor bus address data received this time and the processor bus address data received last time;

[0022] If the continuous state indicates that the addresses are continuous, increment the last processor bus address data by one and send the data to the main memory;

[0023] If the continuous state indicates that the addresses are discontinuous, the current processor bus address data is sent to the main memory.

[0024] According to some embodiments of the present invention, if the buffer receives the processor bus address data for the first time, reading the data in the main memory into the buffer according to the processor bus address data, the first effective bus width, and the second effective bus width further includes the following steps:

[0025] The waiting signal is sent to the central processing unit.

[0026] According to some embodiments of the present invention, if the data in the main memory is written into the buffer starting from the least significant bits of the address of the buffer, the method for prefetching data further includes the following steps:

[0027] The data in the buffer are sent to the central processing unit starting from the least significant bit of the address of the buffer.

[0028] A prefetch data structure according to an embodiment of a second aspect of the present invention is applied to a buffer, the buffer being connected between a central processing unit and a main memory, wherein a first effective bus width of the main memory and a second effective bus width of the central processing unit are set according to a ratio of a data read time of the main memory to a working clock cycle of the central processing unit;

[0029] The prefetch data structure includes:

[0030] A frequency processing module, configured to obtain a ratio of a data reading time of the main memory to a working clock cycle of the central processing unit;

[0031] An address processing module, configured to receive processor bus address data sent by the central processing unit and send the data to the main memory;

[0032] The data transceiver module is used to receive data sent by the main memory and send the data to the central processing unit.

[0033] The prefetch data structure according to an embodiment of the present invention has at least the following technical effects: the frequency processing module can obtain the ratio of the data read time of the main memory to the operating clock cycle of the central processing unit, and adjust the ratio of the first effective bus width of the main memory to the second effective bus width of the central processing unit based on the ratio, so that the data processing cycle in the cache is adapted to the data read time of the main memory and the operating clock cycle of the central processing unit. When data needs to be read from the main memory, the address processing module first receives the processor bus address data sent by the central processing unit, and then reads the data in the main memory into the data transceiver module based on the processor bus address data, the first effective bus width, and the second effective bus width. This can ensure that when the previous data processing is completed, the new data has been read from the main memory into the cache, thereby achieving a pipeline processing method and solving the problem of low cache operation efficiency.

[0034] According to some embodiments of the present invention, the ratio of the data reading time of the main memory to the working clock cycle of the central processing unit is an integer bus adjustment ratio obtained by rounding, and the ratio of the first effective bus width to the second effective bus width is equal to the bus adjustment ratio.

[0035] According to some embodiments of the present invention, the address processing module is further configured to determine a hold time between a time of receiving the processor bus address data this time and a time of receiving the processor bus address data last time;

[0036] The pre-fetch data structure further includes a waiting logic module, which is used to determine the relationship between the holding time and the data reading time of the main memory and send a waiting signal to the central processing unit.

[0037] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The above or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments with reference to the following drawings, in which:

[0039] Figure 1 is a flow chart of a method for prefetching data according to an embodiment of the present invention;

[0040] Figure 2 is a flow chart of a method for prefetching data according to another embodiment of the present invention;

[0041] Figure 3 is a flow chart of a method for prefetching data according to another embodiment of the present invention;

[0042] Figure 4 It is a logical structure block diagram of the prefetch data structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0043] The following describes embodiments of the present invention in detail. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended only to explain the present invention and are not to be construed as limiting the present invention.

[0044] In the description of the present invention, it should be understood that descriptions of directions, such as up, down, front, back, left, and right, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operate in a specific direction. Therefore, it should not be understood as a limitation on the present invention.

[0045] In the description of the present invention, "several" means one or more, "many" means more than two, "greater than," "less than," and "exceed" are understood to exclude the number itself, while "above," "below," and "within" are understood to include the number itself. The use of "first" and "second" in the description is solely for the purpose of distinguishing technical features and should not be construed as indicating or implying relative importance, implicitly specifying the number of the indicated technical features, or implicitly specifying the order of the indicated technical features.

[0046] In the description of the present invention, unless otherwise clearly defined, terms such as setting, installing, and connecting should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention based on the specific content of the technical solution.

[0047] Reference below Figures 1 to 3 A method for prefetching data according to an embodiment of the first aspect of the present invention is described.

[0048] A data prefetching method according to an embodiment of the present invention is applied to a cache connected between a central processing unit (CPU) and a main memory, wherein a first effective bus width of the main memory and a second effective bus width of the CPU are set according to a ratio of a data read time of the main memory to a working clock cycle of the CPU.

[0049] The method for prefetching data includes the following steps:

[0050] receiving processor bus address data sent by the central processing unit;

[0051] The data in the main memory is read into the buffer according to the processor bus address data, the first effective bus width and the second effective bus width.

[0052] Different main memories have different data read times, and different central processing units have different operating clock cycles. Therefore, if both the central processing unit and the main memory are operated at the maximum data read and write speed, the central processing unit will inevitably spend a large amount of time in a waiting state. The data prefetching method of the embodiment of the present invention adjusts the ratio of the time it takes for the cache to send data to the central processing unit and the time it takes to read data from the main memory by adjusting the first effective bus width of the main memory and the second effective bus width of the central processing unit. This can effectively reduce the waiting time of the central processing unit and improve the operating efficiency of the central processing unit. Specifically, if the data read time of the main memory is T1, the operating clock cycle of the central processing unit is T2, the first effective bus width of the main memory is set to n, and the second effective bus width of the central processing unit is set to L, then when the value of T1 / T2 is non-integer and satisfies T1 / T2+1=n / L, after the cache receives the processor bus address data sent by the central processing unit, it will take T1 / T2+1 operating clock cycle T2 to complete each read of data from the main memory. When the previous data processing is completed, the new data has been read from the main memory into the cache, thereby achieving a pipeline processing method and high cache operation efficiency. It should be noted that when the value of T1 / T2 is an integer, the integer value can be directly used without adding 1.

[0053] According to an embodiment of the present invention, the data prefetching method first adjusts the ratio of the first effective bus width of the main memory and the second effective bus width of the central processor based on the ratio of the data read time of the main memory to the operating clock cycle of the central processor, so that the data processing cycle in the cache is adapted to the data read time of the main memory and the operating clock cycle of the central processor. When data needs to be read from the main memory, the cache first receives processor bus address data sent by the central processor, and then reads the data from the main memory into the cache based on the processor bus address data, the first effective bus width, and the second effective bus width. This can ensure that when the previous data processing is completed, the new data has been read from the main memory into the cache, thereby achieving a pipeline processing method and solving the problem of low cache operation efficiency.

[0054] In some embodiments of the present invention, if the ratio of the data read time of the main memory to the working clock cycle of the central processing unit is a non-integer, the ratio of the first effective bus width to the second effective bus width is set by the following steps:

[0055] Calculate the ratio of the data read time of the main memory to the working clock cycle of the central processing unit, and obtain the integer bus adjustment ratio by rounding.

[0056] The first effective bus width and the second effective bus width are set according to the bus justification ratio so that a ratio of the first effective bus width to the second effective bus width is equal to the bus justification ratio.

[0057] The data read time of the main memory is T1, and the working clock cycle of the central processing unit is T2. If T1 / T2 is a non-integer, when processing data read from the main memory, the time T1 / T2 does not correspond to an integer cycle, and one cycle must be added to complete the data processing. T1 / T2 is integerized by rounding, that is, the bus adjustment ratio is T1 / T2+1. The product of the bus adjustment ratio and the working clock cycle T2 of the central processing unit needs to be greater than or equal to the data read time T1 of the main memory. Therefore, the first effective bus width of the main memory is set to n, and the second effective bus width of the central processing unit is set to L, so that T1 / T2+1=n / L, which can achieve high-efficiency data caching. It should be noted that in some embodiments of the present invention, the rounding method can directly adopt the rounding method.

[0058] In some embodiments of the present invention, if the data reading time of the main memory is 35ns and the working clock cycle of the central processing unit is 9ns, the bus adjustment ratio is 4. Therefore, the second effective bus width of the central processing unit can be set to 16 bits, and the first effective bus width of the main memory needs to be set to 64 bits. Then, when the last data processing is completed, the new data has been read from the main memory into the cache, thereby achieving a pipeline processing method and the cache has high operating efficiency. It should be noted that the second effective bus width and the first effective bus width are not necessarily set to 64 bits and 16 bits. The specific width values ​​need to be adjusted according to the actual widths of the central processing unit and the main memory. Specifically, for the case where the data reading time of the main memory is 35ns and the working clock cycle of the central processing unit is 9ns, it is sufficient to maintain a ratio of 4.

[0059] In some embodiments of the present invention, reference Figure 2 , reading data in the main memory into the cache according to the processor bus address data, the first effective bus width and the second effective bus width, comprising the following steps:

[0060] Determine the hold time between the moment of receiving the processor bus address data this time and the moment of receiving the processor bus address data last time;

[0061] If the holding time is less than the data reading time of the main memory, a wait signal is sent to the central processing unit; the wait signal is used to make the central processing unit wait until the holding time is greater than or equal to the data reading time of the main memory;

[0062] If the holding time is greater than or equal to the data reading time of the main memory, the data in the main memory is read into the buffer according to the processor bus address data received this time, the first effective bus width and the second effective bus width.

[0063] By determining the relationship between the hold time between the moment the processor bus address data is received and the moment the processor bus address data was previously received, and the main memory's data read time, it can be determined whether the main memory is in an active state. If the hold time is less than the main memory's data read time, the main memory is currently in an active state. By sending a wait signal to the central processing unit, the central processing unit can be placed in a wait state until the hold time is greater than or equal to the main memory's data read time. At this point, the data in the main memory can be read into the buffer based on the currently received processor bus address data.

[0064] In some embodiments of the present invention, determining the hold time between the moment of receiving the processor bus address data this time and the moment of receiving the processor bus address data last time includes the following steps:

[0065] Determine the number of working cycles that the central processing unit has worked between the time when the processor bus address data is received this time and the time when the processor bus address data was received last time;

[0066] Calculate the product of the number of working cycles and the working clock cycle of the central processing unit and record it as the hold time.

[0067] Determine the number of working cycles that the central processing unit has worked. The product of the central processing unit's working clock cycle and the number of working cycles is the duration corresponding to the hold time between the moment of receiving the processor bus address data this time and the moment of receiving the processor bus address data last time. Therefore, it is possible to determine whether the main memory is in a working state through the duration corresponding to the hold time.

[0068] In some embodiments of the present invention, reference Figure 3 , reading data in the main memory into the cache according to the processor bus address data, the first effective bus width and the second effective bus width, further comprising the following steps:

[0069] Determining a continuity state between the processor bus address data received this time and the processor bus address data received last time;

[0070] If the continuous state indicates that the addresses are continuous, the last processor bus address data is incremented by one and sent to the main memory;

[0071] If the continuous state indicates that the addresses are discontinuous, the current processor bus address data is sent to the main memory.

[0072] After receiving the new processor bus address data, by determining whether the difference between the processor bus address data received last time and the processor bus address data received this time is 1, it can be determined whether the processor bus address data received this time is continuous with the processor bus address data received last time. If the difference is 1, it indicates that the address is continuous, and then the last processor bus address data can be increased by 1 and sent to the main memory, so that the data corresponding to the next processor bus address data can be directly read from the main memory into the cache, thereby improving the efficiency of reading data from the main memory. If the difference is not 1, it indicates that the address is discontinuous, then the current processor bus address data is sent to the main memory, waiting for the data to be re-transmitted from the new address from the main memory to the cache, and the data corresponding to the current processor bus address data in the main memory is read into the cache.

[0073] In some embodiments of the present invention, if the buffer receives the processor bus address data for the first time, reading data from the main memory into the buffer according to the processor bus address data, the first effective bus width, and the second effective bus width further includes the following steps:

[0074] Sends a wait signal to the CPU.

[0075] If the buffer receives processor bus address data for the first time and there is no data in the buffer that the CPU needs to read, a wait signal is sent to the CPU, causing the buffer to complete reading data from the main memory before the CPU begins to receive data sent by the buffer. This prevents the CPU from reading empty data from the buffer during the initial process.

[0076] In some embodiments of the present invention, if the data in the main memory is written into the buffer starting from the least significant bits of the buffer address, the method for prefetching data further includes the following steps:

[0077] The data in the buffer is sent to the central processing unit starting from the least significant bit of the buffer address.

[0078] If the data in the main memory is written into the cache starting from the least significant bit of the cache address, according to the first-in-first-out principle, the data written into the cache first will be sent to the central processing unit first, that is, the data in the cache will be sent to the central processing unit starting from the least significant bit of the cache address, making the data transmission more orderly.

[0079] To better illustrate the data prefetching method of the first embodiment of the present invention, a specific embodiment is described in more detail herein, taking a main memory data read time of 35ns, a central processing unit operating clock cycle of 9ns, and a main memory bus width of 22 bits as an example.

[0080] The bus adjustment ratio obtained by rounding is 35 / 9+1=4, which means that after the buffer receives the processor bus address data sent by the CPU, it takes at least 4 working clock cycles to process the data read from the main memory. If the second effective bus width of the CPU is set to 16 bits, the first effective bus width of the main memory is set to 64 bits (16x4=64). If the processor address bus width is 22 bits (Addr[21:0]), and 64 / 16=2 2 , the low-significant bits of the address are Addr[1:0], and the high-significant bits of the address are Addr[21:2]. The high-significant bits of the address are the processor bus address data to be sent from the central processing unit to the cache.

[0081] When the central processing unit starts running, it receives the processor bus address data sent by the central processing unit and sends the current processor bus address data to the main memory; sends a wait signal to the central processing unit to delay its value, with the delay time being 4 working clock cycles; then reads 64-bit data from the main memory according to the processor bus address data, and writes it into the buffer starting from the low-significant bit of the buffer address; after the writing is completed, the 64-bit data in the buffer is sent to the central processing unit starting from the low-significant bit of the buffer address. Receive new processor bus address data sent by the central processing unit, and determine the continuity status between the processor bus address data received this time and the processor bus address data received last time; if the continuity status indicates that the address is continuous, increase the last processor bus address data by one and send it to the main memory, and determine the hold time between the time when the processor bus address data is received this time and the time when the processor bus address data is received last time; if the hold time is less than the data read time of the main memory 35ns, send a wait signal to the central processing unit to make up 4 working clock cycles; when the hold time is greater than or equal to the data read time of the main memory 35ns, read 64-bit data in the main memory into the cache according to the processor bus address data received this time, and send the 64-bit data in the cache to the central processing unit starting from the low significant bit of the cache address.

[0082] Reference below Figures 1 to 4 A prefetch data structure according to an embodiment of a second aspect of the present invention is described. The prefetch data structure is applied to a cache connected between a central processing unit (CPU) and a main memory. The first effective bus width of the main memory and the second effective bus width of the CPU are set based on the ratio of the data read time of the main memory to the operating clock cycle of the CPU. The prefetch data structure includes a frequency processing module, an address processing module, and a data transceiver module. The frequency processing module is used to obtain the ratio of the data read time of the main memory to the operating clock cycle of the CPU; the address processing module is used to receive processor bus address data sent by the CPU and send it to the main memory; and the data transceiver module is used to receive data sent by the main memory and send it to the CPU.

[0083] According to the prefetch data structure of an embodiment of the present invention, a frequency processing module can obtain the ratio of the data read time of the main memory to the operating clock cycle of the central processing unit. Based on this ratio, the ratio of the first effective bus width of the main memory to the second effective bus width of the central processing unit is adjusted, so that the data processing cycle in the cache is adapted to the data read time of the main memory and the operating clock cycle of the central processing unit. When data needs to be read from the main memory, the address processing module first receives the processor bus address data sent by the central processing unit. Then, based on the processor bus address data, the first effective bus width and the second effective bus width, the data in the main memory can be read into the data transceiver module. This can ensure that when the previous data processing is completed, the new data has been read from the main memory into the cache, thereby achieving a pipeline processing method and solving the problem of low cache operation efficiency.

[0084] In some embodiments of the present invention, the ratio of the main memory data read time to the central processing unit's operating clock cycle is an integerized bus adjustment ratio obtained by rounding, and the ratio of the first effective bus width to the second effective bus width is equal to the bus adjustment ratio. The main memory data read time is T1, and the central processing unit's operating clock cycle is T2. If T1 / T2 is a non-integer, when processing data read from the main memory, the time T1 / T2 does not correspond to an integer cycle, and one cycle must be added to complete the data processing. T1 / T2 is rounded to an integer, that is, the bus adjustment ratio is T1 / T2+1. The product of the bus adjustment ratio and the central processing unit's operating clock cycle T2 must be greater than or equal to the main memory data read time T1. Therefore, the first effective bus width of the main memory is set to n, and the second effective bus width of the central processing unit is set to L, so that T1 / T2+1=n / L, which can achieve high-efficiency data caching.

[0085] In some embodiments of the present invention, reference Figure 2 and Figure 4 The address processing module is also used to determine the holding time between the moment of receiving the processor bus address data this time and the moment of receiving the processor bus address data last time; the pre-fetch data structure also includes a waiting logic module, which is used to determine the relationship between the holding time and the data reading time of the main memory, and send a waiting signal to the central processing unit.

[0086] The address processing module determines the holding time between the moment of receiving the processor bus address data this time and the moment of receiving the processor bus address data last time, and then the waiting logic module determines the relationship between the holding time and the data reading time of the main memory. If the holding time is less than the data reading time of the main memory, it indicates that the main memory is in a working state at this time. The waiting logic module will send a waiting signal to the central processing unit, causing the central processing unit to wait until the holding time is greater than or equal to the data reading time of the main memory. At this time, the main memory is in a non-working state, and the data sent by the main memory can be received through the data transceiver module.

[0087] In some embodiments of the present invention, reference Figure 3 and Figure 4 , the address processing module is also used to determine the continuity status between the processor bus address data received this time and the processor bus address data received last time. After the address processing module receives the new processor bus address data, it can determine whether the processor bus address data received this time is continuous with the processor bus address data received last time by determining whether the difference between the processor bus address data received last time and the processor bus address data received this time is 1. If the difference is 1, it indicates that the address is continuous, and then the last processor bus address data can be added by one and sent to the main memory, so that the data corresponding to the next processor bus address data is directly read from the main memory into the cache, thereby improving the efficiency of reading data from the main memory. If the difference is not 1, it indicates that the address is discontinuous, then the current processor bus address data is sent to the main memory, waiting for the data to be re-transmitted from the new address to the cache from the main memory, and the data corresponding to the current processor bus address data in the main memory is read into the cache.

[0088] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, illustrative uses of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0089] Although the embodiments of the present invention have been described in detail above in conjunction with the accompanying drawings, the present invention is not limited to the above embodiments. Those skilled in the art will understand that various changes, modifications, substitutions and variations may be made to these embodiments without departing from the principles and purpose of the present invention. The scope of the present invention is defined by the claims and their equivalents.

Claims

1. A method for prefetching data, applied to a buffer, characterized in that: The buffer is connected between the central processing unit and the main memory, and the first effective bus width of the main memory and the second effective bus width of the central processing unit are set according to the ratio of the data reading time of the main memory to the working clock cycle of the central processing unit; The method for prefetching data comprises the following steps: receiving processor bus address data sent by the central processing unit; Reading data in the main memory into the buffer according to the processor bus address data, the first effective bus width, and the second effective bus width; If the ratio of the data read time of the main memory to the working clock cycle of the central processing unit is a non-integer, the ratio of the first effective bus width to the second effective bus width is set by the following steps: Calculating the ratio of the data reading time of the main memory to the working clock cycle of the central processing unit, and obtaining an integer bus adjustment ratio by rounding; The first effective bus width and the second effective bus width are set according to the bus adjustment ratio so that a ratio of the first effective bus width to the second effective bus width is equal to the bus adjustment ratio.

2. The method for prefetching data according to claim 1, wherein: The method of reading the data in the main memory into the buffer according to the processor bus address data, the first effective bus width, and the second effective bus width comprises the following steps: Determine a hold time between a time of receiving the processor bus address data this time and a time of receiving the processor bus address data last time; If the holding time is less than the data reading time of the main memory, a waiting signal is sent to the central processing unit; the waiting signal is used to make the central processing unit wait until the holding time is greater than or equal to the data reading time of the main memory; If the holding time is greater than or equal to the data reading time of the main memory, the data in the main memory is read into the buffer according to the processor bus address data, the first effective bus width and the second effective bus width received this time.

3. The method for prefetching data according to claim 2, wherein: Determining the holding time between the moment of receiving the processor bus address data this time and the moment of receiving the processor bus address data last time comprises the following steps: Determine the number of working cycles that the central processing unit has worked between the time of receiving the processor bus address data this time and the time of receiving the processor bus address data last time; The product of the number of working cycles and the working clock cycle of the central processing unit is calculated and recorded as the holding time.

4. The method for prefetching data according to claim 2, wherein: The step of reading the data in the main memory into the buffer according to the processor bus address data, the first effective bus width, and the second effective bus width further includes the following steps: Determining a continuity state between the processor bus address data received this time and the processor bus address data received last time; If the continuous state indicates that the addresses are continuous, increment the last processor bus address data by one and send the data to the main memory; If the continuous state indicates that the addresses are discontinuous, the current processor bus address data is sent to the main memory.

5. The method for prefetching data according to claim 2, wherein: If the cache receives the processor bus address data for the first time, reading the data in the main memory into the cache according to the processor bus address data, the first effective bus width and the second effective bus width also includes the following steps: sending the wait signal to the central processing unit.

6. The method for prefetching data according to claim 1, wherein: If the data in the main memory is written into the buffer starting from the least significant bits of the address of the buffer, the method for prefetching data further includes the following steps: The data in the buffer are sent to the central processing unit starting from the least significant bit of the address of the buffer.

7. A prefetch data structure, applied to a cache, characterized in that: The buffer is connected between the central processing unit and the main memory, and the first effective bus width of the main memory and the second effective bus width of the central processing unit are set according to the ratio of the data reading time of the main memory to the working clock cycle of the central processing unit; The prefetch data structure includes: A frequency processing module, configured to obtain a ratio of a data reading time of the main memory to a working clock cycle of the central processing unit; An address processing module, configured to receive processor bus address data sent by the central processing unit and send the data to the main memory; A data transceiver module, configured to receive data sent by the main memory and send the data to the central processing unit; If the ratio of the data read time of the main memory to the working clock cycle of the central processing unit is a non-integer, the ratio of the first effective bus width to the second effective bus width is set by the following steps: Calculating the ratio of the data reading time of the main memory to the working clock cycle of the central processing unit, and obtaining an integer bus adjustment ratio by rounding; The first effective bus width and the second effective bus width are set according to the bus adjustment ratio so that a ratio of the first effective bus width to the second effective bus width is equal to the bus adjustment ratio.

8. The prefetch data structure according to claim 7, wherein: The ratio of the data reading time of the main memory to the working clock cycle of the central processing unit is an integer bus adjustment ratio obtained by rounding, and the ratio of the first effective bus width to the second effective bus width is equal to the bus adjustment ratio.

9. The prefetch data structure according to claim 7, wherein: The address processing module is further configured to determine a hold time between a time of receiving the processor bus address data this time and a time of receiving the processor bus address data last time; The pre-fetch data structure further includes a waiting logic module, which is used to determine the relationship between the holding time and the data reading time of the main memory and send a waiting signal to the central processing unit.

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