Semiconductor device

Abstract

A semiconductor device includes a first wafer including a row decoder region in which a plurality of transfer transistors are arranged in a row direction and a column direction, a plurality of first bonding pads respectively coupled with the plurality of transfer transistors and disposed in a plurality of rows on one surface of the first wafer in the row decoder region, and a plurality of second bonding pads disposed on the one surface of the first wafer in the row decoder region, wherein the plurality of second bonding pads are disposed in different rows from the plurality of first bonding pads and are offset in the row direction with respect to the plurality of first bonding pads.

Description

Technical Field

[0001] The various implementations generally relate to semiconductor technology, and more specifically to semiconductor devices using wafer bonding technology. Background Technology

[0002] As a measure to improve integration, a technique has been disclosed in the art of separating the memory cell array and the logic circuit for controlling the memory cell array and fabricating them separately on a cell wafer and a peripheral wafer, and then bonding the cell wafer and the peripheral wafer together with each other using wafer bonding technology to form a semiconductor device.

[0003] In semiconductor devices using this wafer bonding technology, the bonding pads of the unit wafer and the bonding pads of the peripheral wafer are overlapped and bonded, thereby electrically connecting the memory cell array and logic circuits. Summary of the Invention

[0004] Various implementations relate to semiconductor devices with reduced pad bonding failures.

[0005] Various implementations involve semiconductor devices with reduced dimensions.

[0006] In one embodiment, a semiconductor device may include: a first wafer including a row decoder region in which a plurality of transmission transistors are arranged in both row and column directions; a plurality of first bonding pads respectively connected to the plurality of transmission transistors and disposed in a plurality of rows on a surface of the first wafer in the row decoder region; and a plurality of second bonding pads disposed on a surface of the first wafer in the row decoder region, wherein the plurality of second bonding pads are disposed in different rows from the plurality of first bonding pads and offset relative to the plurality of first bonding pads in the row direction.

[0007] In an embodiment, the semiconductor device may include: a cell wafer including a memory cell array and a plurality of electrode layers, the memory cell array being defined in a cell region, the plurality of electrode layers being stacked on top of each other in a vertical direction, the plurality of electrode layers being connected to the memory cell array and extending from the cell region to a row decoder region; a plurality of first bonding pads disposed on a surface of the cell wafer in the row decoder region and respectively connected to the plurality of electrode layers; a plurality of second bonding pads disposed on a surface of the cell wafer in the row decoder region; wiring configured to be spaced apart from the second bonding pads in a vertical direction, with the plurality of electrode layers interposed therebetween; and a plurality of vertical contacts disposed in the row decoder region, the plurality of vertical contacts connecting the plurality of second bonding pads and the wiring. Attached Figure Description

[0008] Figure 1This is a block diagram schematically illustrating a semiconductor device according to an embodiment of the present disclosure.

[0009] Figure 2 This is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 3 This is an exemplary layout diagram illustrating the arrangement of the transfer transistor and bonding pads according to an embodiment of the present disclosure.

[0011] Figure 4 This is a layout diagram illustrating a different arrangement of the transmission transistors and bonding pads compared to embodiments of this disclosure.

[0012] Figure 5 Part (a) is a diagram illustrating a column-direction layout structure of the bonding pads that differs from an embodiment of this disclosure, and Figure 5 Part (b) is a diagram illustrating the column-direction layout structure of the bonding pads according to an embodiment of the present disclosure.

[0013] Figure 6 This is a layout diagram illustrating a transfer transistor and bonding pad according to another embodiment of the present disclosure.

[0014] Figure 7 This is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present disclosure.

[0015] Figure 8 This is a cross-sectional view illustrating a layout of bonding pads and vertical contacts that differs from the layout of bonding pads and vertical contacts according to embodiments of the present disclosure.

[0016] Figure 9 This is a block diagram illustrating a memory system including a semiconductor device according to an embodiment of the present disclosure.

[0017] Figure 10 This is a block diagram illustrating a computing system including a semiconductor device according to an embodiment of the present disclosure. Detailed Implementation

[0018] The advantages and features of this disclosure, as well as methods for implementing them, will become apparent from the description of exemplary embodiments described below with reference to the accompanying drawings. However, this disclosure is not limited to the exemplary embodiments disclosed herein, but can be implemented in a variety of different ways. The exemplary embodiments of this disclosure convey the scope of this disclosure to those skilled in the art.

[0019] Because the number, figures, dimensions, ratios, and angles of elements given in the accompanying drawings describing embodiments of this disclosure are merely illustrative, this disclosure is not limited to what is illustrated. Throughout the specification, similar reference numerals refer to similar components. In describing this disclosure, detailed descriptions of related technologies will be omitted where it is determined that such detailed descriptions may obscure the gist or clarity of the disclosure. It is to be understood that, unless expressly stated otherwise, the terms “comprising,” “having,” “including,” etc., as used in the specification and claims should not be construed as limiting to the means listed thereafter. When referring to singular nouns with indefinite or definite articles (e.g., “a,” “an,” or “the”), the article may include the plural form of the noun unless expressly stated otherwise.

[0020] When interpreting the elements in the embodiments of this disclosure, they should be interpreted as including tolerances, even if not explicitly stated otherwise.

[0021] Additionally, in describing the components of this disclosure, terms such as first, second, A, B, (a), and (b) may be used. These are merely for distinguishing one component from another and do not limit the nature, order, sequence, or number of the components. Furthermore, the components in embodiments of this disclosure are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, as used herein, within the spirit of this disclosure, a first component may be a second component.

[0022] If a component is described as "connected," "linked," or "coupled" to another component, this can mean that the component is not only directly "connected," "linked," or "coupled," but also indirectly "connected," "linked," or "coupled" via a third component. When describing positional relationships (such as "component A on component B," "component A above component B," "component A below component B," and "component A next to component B"), one or more other components may be placed between component A and B unless the terms "directly" or "immediately" are explicitly used.

[0023] Features of the various exemplary embodiments of this disclosure can be combined, integrated, or separated, in whole or in part. Technically, various interactions and operations are possible. Various exemplary embodiments can be practiced individually or in combination.

[0024] In the following, various examples of embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0025] Figure 1 This is a block diagram schematically illustrating a semiconductor device according to an embodiment of the present disclosure.

[0026] Reference Figure 1The semiconductor device 100 according to embodiments of the present disclosure may include a memory cell array 110, a row decoder (X-DEC) 120, a page buffer circuit 130, and a peripheral circuit (PERI circuit) 140.

[0027] The memory cell array 110 may include multiple memory blocks BLK. Although not shown, each memory block BLK may include multiple memory cells. Memory cells may be volatile memory cells that lose data stored therein in the event of a power interruption, or they may be non-volatile memory cells that retain data stored therein even if the power supply is interrupted. Although the semiconductor device 100 is described below as a vertical NAND flash memory device, it should be noted that the spirit of this disclosure is not limited thereto.

[0028] A row decoder (X-DEC) 120 can be connected to the memory cell array 110 via row lines RL. Row line RL may include at least one drain select line, multiple word lines, and at least one source select line. The row decoder (X-DEC) 120 can select a memory block from the memory blocks BLK of the memory cell array 110 based on address information. The row decoder (X-DEC) 120 can transmit an operating voltage X_V (e.g., programming voltage, pass voltage, or read voltage) from peripheral circuitry 140 to the row line RL connected to the selected memory block BLK. To transmit the operating voltage X_V, the row decoder (X-DEC) 120 may include multiple transfer transistors respectively connected to the row line RL.

[0029] Page buffer circuit 130 can be connected to memory cell array 110 via bit line BL. Page buffer circuit 130 may include multiple page buffers PB respectively connected to bit line BL. Page buffer circuit 130 can receive page buffer control signal PB_C from peripheral circuit 140, and can send data signal DATA to and receive data signal DATA from peripheral circuit 140.

[0030] Page buffer circuit 130 can control bit lines BL connected to memory cell array 110 in response to page buffer control signal PB_C. For example, page buffer circuit 130 can detect data stored in memory cells of memory cell array 110 by sensing the signal of bit line BL of memory cell array 110 in response to page buffer control signal PB_C, and can send data signal DATA to peripheral circuit 140 based on the detected data. Page buffer circuit 130 can apply a signal to bit line BL based on data signal DATA received from peripheral circuit 140 in response to page buffer control signal PB_C, thereby writing data into memory cells of memory cell array 110. Page buffer circuit 130 can write data to or read data from memory cells connected to word lines activated by line decoder (X-DEC) 120.

[0031] For example, peripheral circuitry 140 can receive command signals CMD, address signals ADD, and control signals CTRL from outside semiconductor device 100, and can send data DATA to and receive data DATA from devices outside semiconductor device 100 (e.g., memory controllers). Peripheral circuitry 140 can output signals for writing data DATA to or reading data DATA from memory cell array 110 based on command signals CMD, address signals ADD, and control signals CTRL, such as row address X_A, page buffer control signal PB_C, etc. Peripheral circuitry 140 can generate various voltages required in semiconductor device 100, including operating voltage X_V.

[0032] Figure 2 This is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0033] Reference Figure 2 The semiconductor device according to embodiments of the present disclosure may include a peripheral wafer PW and a unit wafer CW bonded to the peripheral wafer PW. The unit wafer CW and the peripheral wafer PW may be fabricated separately and then bonded together and connected into a single unit by a bonding technique.

[0034] The peripheral wafer PW may include a substrate 10 and a logic circuit LOGIC defined in the substrate 10.

[0035] The substrate 10 may be a single-crystal semiconductor film. For example, the substrate 10 may be a bulk silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-on-insulator substrate, a silicon-germanium substrate, or an epitaxial thin film formed by selective epitaxial growth. The substrate 10 and / or the semiconductor device may include a cell region CR, a line decoder region XDR, and a peripheral region PR.

[0036] The logic circuit LOGIC may include multiple pass transistors (PASS TR). Although not shown, the logic circuit LOGIC may also include a page buffer circuit. Figure 1 130), peripheral circuits ( Figure 1 140) and constructing a line decoder in addition to multiple transmission transistors PASS TR ( Figure 1 120) circuits (e.g., block switch circuits).

[0037] Multiple pass transistors (PASS TRs) can be disposed in the line decoder region XDR of substrate 10. Each pass transistor (PASS TR) may include a gate dielectric layer Gox disposed on substrate 10, a gate line GE disposed on the gate dielectric layer Gox, and a source region S defined in the active region on one side of the gate line GE of substrate 10. Although not shown, the drain region of the pass transistor (PASS TR) may be formed in the active region on the other side of the gate line GE of substrate 10 and opposite to the source region S. For ease of understanding, the gate line GE and the gate dielectric layer Gox are... Figure 2 The examples are shown in the image and indicated by dashed lines to show that they do not exist. Figure 2 On the cross section.

[0038] In the line decoder region XDR, multiple first bonding pads PAD1 and multiple second bonding pads PAD2 can be set on a surface of the peripheral wafer PW that is bonded to the cell wafer CW.

[0039] Each first bonding pad PAD1 can be connected to the corresponding transmission transistor PASS TR via contacts CNT1 to CNT3 and wiring M1 to M3. The operating voltage from the transmission transistor PASS TR can be transmitted to the first bonding pad PAD1 via contacts CNT1 to CNT3 and wiring M1 to M3, and can be supplied to the cell wafer CW via the first bonding pad PAD1.

[0040] The peripheral wafer PW can be supplied with the power supply voltage from the cell wafer CW via the second bonding pad PAD2, and the second bonding pad PAD2 can correspond to a power pad for receiving the power supply voltage. Each second bonding pad PAD2 can be connected to a wiring M4, and can be connected to the logic circuit LOGIC via contacts and wiring (not shown) connected to the wiring M4. The power supply voltage supplied from the cell wafer CW to the second bonding pad PAD2 can be transmitted to the logic circuit LOGIC via the wiring M4 and contacts and wiring (not shown).

[0041] The unit wafer (CW) may include a source plate 12, and a plurality of electrode layers 20 and a plurality of interlayer dielectric layers 22 alternately stacked on the bottom surface of the source plate 12.

[0042] The source electrode 12 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, a group IV semiconductor may include silicon, germanium, or silicon-germanium. For example, the source electrode 12 may be a polycrystalline layer or an epitaxial layer.

[0043] Electrode layer 20 can be used to construct row lines ( Figure 1 (RL). Specifically, in the electrode layers 20, at least one electrode layer 20 from the uppermost electrode layer 20 can form a source select line, and at least one electrode layer 20 from the lowermost electrode layer 20 can form a drain select line. The electrode layers 20 between the source select line and the drain select line can form word lines. In the line decoder region XDR, each electrode layer 20 can have a pad area exposed through another electrode layer 20 located below it, and Figure 2 Some of these pad areas are illustrated in the example.

[0044] In the cell region CR, multiple vertical channels CH can be defined as passing through multiple alternating electrode layers 20 and multiple interlayer dielectric layers 22 in the vertical direction VD. Although not shown in detail, each vertical channel CH may include a channel layer and a gate dielectric layer. The channel layer may include polysilicon or monocrystalline silicon and may include p-type impurities such as boron (B) in some regions therein. The gate dielectric layer may have a shape surrounding the outer wall of the channel layer. The gate dielectric layer may include a tunnel dielectric layer, a charge storage layer, and a barrier layer sequentially stacked from the outer wall of the channel layer. In some embodiments, the gate dielectric layer may have an ONO (oxide-nitride-oxide) stack structure in which oxide layers, nitride layers, and oxide layers are sequentially stacked.

[0045] Source select transistors can be configured in a region or area where the source select line surrounds the vertical channel CH. Memory cells can be configured in a region or area where the word line surrounds the vertical channel CH. Drain select transistors can be configured in a region or area where the drain select line surrounds the vertical channel CH. Source select transistors, multiple memory cells, and drain select transistors arranged along a vertical channel CH can form a cell string.

[0046] Multiple bit lines BL can be disposed beneath a laminate comprising multiple electrode layers 20 and multiple interlayer dielectric layers 22. The bit lines BL can extend in the column direction CD and can be arranged in the row direction RD. Each bit line BL can be connected to a corresponding vertical channel CH via a bit line contact BLC.

[0047] In the line decoder region XDR, multiple third bonding pads PAD3 and multiple fourth bonding pads PAD4 can be set on a surface of the cell wafer CW that is bonded to the peripheral wafer PW.

[0048] Multiple third bonding pads PAD3 can be configured to have substantially the same arrangement and substantially the same shape as multiple first bonding pads PAD1, and can be bonded to the multiple first bonding pads PAD1 respectively. Each of the multiple third bonding pads PAD3 can be connected to the pad area of ​​the corresponding electrode layer 20 via a contact CNT4.

[0049] Multiple fourth bonding pads PAD4 can be configured to have substantially the same arrangement and substantially the same shape as multiple second bonding pads PAD2, and can be bonded to the multiple second bonding pads PAD2 respectively. Although the second bonding pads PAD2 and the fourth bonding pads PAD4 are... Figure 2 The sections shown do not actually exist, but they are included and indicated by dashed lines for ease of understanding.

[0050] Wiring W can be positioned above the source plate 12. Wiring W can be positioned to be spaced apart from multiple fourth bonding pads PAD4 and with electrode layers 20 inserted therebetween.

[0051] Although not shown, the cell wafer CW may include multiple pins for interfacing with external devices. These pins may include power pins, and wiring W may be power lines connected to these power pins. Wiring W may be connected to multiple fourth bonding pads PAD4 via vertical contacts (not shown).

[0052] Pad bonding failures may occur when the first and second bonding pads PAD1 and PAD2 of the peripheral wafer PW overlap and bond with the third and fourth bonding pads PAD3 and PAD4 of the unit wafer CW.

[0053] Pad bonding failure refers to a situation where, during overlap and bonding, the first bonding pad PAD1 and the second bonding pad PAD2 of the peripheral wafer PW do not overlap as expected with the third bonding pad PAD3 and the fourth bonding pad PAD4 of the unit wafer CW, resulting in the bonding pad not bonding to its corresponding bonding pad (open circuit failure) or the bonding pad bonding to the wrong adjacent bonding pad (short circuit failure).

[0054] Increasing the size of the bonding pad increases the margin within which the bonding pad is positioned to overlap with the target bonding pad, thus reducing the likelihood of open-circuit faults. However, increasing the size of the bonding pad decreases the spacing between adjacent bonding pads, increasing the likelihood of bonding pads overlapping with undesired bonding pads and thus increasing the likelihood of short-circuit faults. Conversely, decreasing the size of the bonding pad to increase the spacing between adjacent bonding pads reduces the likelihood of short-circuit faults, but increases the likelihood of open-circuit faults due to the smaller pad size.

[0055] Increasing the size of the bonding pads and the spacing between adjacent bonding pads can reduce the likelihood of both open-circuit and short-circuit faults, but this increases the size of the semiconductor device, which does not support miniaturization. Embodiments described herein disclose measures that can reduce pad bonding faults without increasing the size of the semiconductor device.

[0056] Figure 3 This is an exemplary layout diagram illustrating the arrangement of the transfer transistor and bonding pads according to an embodiment of the present disclosure.

[0057] Reference Figure 3 In the row decoder region XDR, multiple transmission transistors PASS TR can be arranged on the row direction RD and the column direction CD.

[0058] In detail, multiple active regions ACT can be arranged in a row on the row direction RD, and two gate lines GE extending on the row direction RD can be arranged parallel to each other while traversing the multiple active regions ACT arranged in a row on the row direction RD.

[0059] The drain region D can be formed in the central portion between the two gate lines GE of each active region ACT, and the two source regions S can be formed at the two ends of the active region ACT, respectively, with the source regions located opposite the drain region D relative to the gate line GE. Therefore, two transistors sharing a single drain region D can be constructed within one active region ACT. Each transmission transistor PASS TR can be one of the two transistors constructed within one active region ACT.

[0060] although Figure 3The example only illustrates two rows of transmission transistors PASS TR configured in an active region ACT within a single row. However, it should be understood that the active region ACT can be configured in multiple rows, and the transmission transistors PASS TR can be configured in a number of rows that are twice the number of rows of the active region ACT.

[0061] In the line decoder region (XDR), multiple first bonding pads (PAD1) and multiple second bonding pads (PAD2) can be configured. The multiple first bonding pads (PAD1) can be configured across multiple lines. The multiple second bonding pads (PAD2) can be configured in lines different from the lines containing the first bonding pads (PAD1), and can be configured by offsetting them relative to the first bonding pads (PAD1) in the line direction (RD). For example, the first bonding pads (PAD1) in one line and the second bonding pads (PAD2) in an adjacent line can be configured in a zigzag pattern extending in the line direction (RD).

[0062] In the layout, the first bonding pad PAD1 can have the same or substantially the same arrangement as the source region S of the transmission transistor PASS TR. For example, multiple first bonding pads PAD1 can also be arranged in multiple rows in the same way as the source regions S are arranged in multiple rows.

[0063] Multiple first bonding pads PAD1 can overlap with the source region S of the transmission transistor PASS TR in the vertical direction VD. The first bonding pads PAD1 and the source region S can be connected to each other via an electrical connection path (not shown). The electrical connection path connecting the first bonding pads PAD1 and the source region S can be configured to have the same length as the shortest distance between the first bonding pads PAD1 and the source region S that are set to overlap in the vertical direction VD.

[0064] When viewed from above, each of the plurality of second bonding pads PAD2 can be positioned in the same or substantially the same row as the drain region D of the transmission transistor PASS TR. The plurality of second bonding pads PAD2 can be offset relative to the drain region D in the row direction RD. Because the drain region D is not offset relative to the first bonding pad PAD1 in the row direction RD, if each second bonding pad PAD2 is offset relative to the drain region D in the row direction RD, it can be understood that each second bonding pad PAD2 is also offset relative to the first bonding pad PAD1 in the row direction RD.

[0065] In other words, the second bonding pad PAD2 can be located at the central portion of a quadrilateral region surrounded by a virtual line L connecting four adjacent first bonding pads PAD1 in the row direction RD and column direction CD. For example, the second bonding pad PAD2 can be located at the point where the two diagonals connecting the vertices of the quadrilateral region defined by the virtual line L intersect each other, and the spacing between the first bonding pads PAD1 and their adjacent corresponding second bonding pads PAD2 can have a dimension D1. In this example, the vertex can be located at the center of each first bonding pad PAD1; however, other locations referencing the first bonding pads PAD1 are also possible.

[0066] Figure 4 This is a layout diagram illustrating a different arrangement of the transmission transistors and bonding pads compared to embodiments of this disclosure.

[0067] Reference Figure 4 The second bonding pad PAD2 can be located between two adjacent first bonding pads PAD1 in the column direction CD. The second bonding pad PAD2 is not offset relative to the first bonding pads PAD1 in the row direction RD, therefore the second bonding pad PAD2 can be located between two adjacent first bonding pads PAD1 in the column direction CD. Figure 4 In the process, the spacing between the first bonding pad PAD1 and the second bonding pad PAD2, which are adjacent to each other, is D2, which is smaller than D1.

[0068] As referenced above Figure 3 In the embodiments described in this disclosure, if the second bonding pad PAD2 is set to be offset relative to the first bonding pad PAD1 in the row direction RD, then the spacing between adjacent first bonding pads PAD1 and second bonding pads PAD2 is... Figure 4 Compared to the situation in the middle, it can be increased, in Figure 4 The second bonding pad PAD2 is positioned without offset relative to the first bonding pad PAD1 in the row direction RD. Therefore, in Figure 3 In the middle, when the outer wafer ( Figure 2 The first bonding pad and the second bonding pad of the PW) Figure 2 PAD1 and PAD2) and unit wafers ( Figure 2 The third and fourth bonding pads of the CW) Figure 2 When PAD3 and PAD4 overlap and are joined, the likelihood of pad bonding failure can be reduced.

[0069] Figure 5 Part (a) is a diagram illustrating a column-direction layout structure of the bonding pads that differs from an embodiment of this disclosure, and Figure 5Part (b) is a diagram illustrating the column-direction layout structure of the bonding pads according to an embodiment of the present disclosure.

[0070] As referenced above Figure 4 The second bonding pad PAD2 can be positioned without offset relative to the first bonding pad PAD1 in the row direction RD. For example... Figure 5 As shown in part (a) Figure 4 The second bonding pad PAD2 can be located between two first bonding pads PAD1 that are adjacent to each other in the column direction CD.

[0071] As referenced above Figure 3 According to an embodiment of this disclosure, a second bonding pad PAD2 is disposed at an offset relative to the first bonding pad PAD1 in the row direction RD. As a result, the second bonding pad PAD2 is disposed in a column different from the column where the first bonding pad PAD1 is disposed. Figure 5 As shown in part (b), the second bonding pad PAD2 is not located between the first bonding pads PAD1 that are adjacent to each other in the column direction CD. Therefore, with Figure 5 Compared to the case shown in part (a), the spacing between adjacent bonding pads PAD1 and PAD2 is increased.

[0072] Figure 6 This is a layout diagram illustrating a transfer transistor and bonding pad according to another embodiment of the present disclosure.

[0073] Reference Figure 6 Each of the first bonding pad PAD1 and the second bonding pad PAD2 can have a polygonal shape. For example, the sides of the first bonding pad PAD1 and the sides of the second bonding pad PAD2, which are facing each other, can be parallel to each other.

[0074] Each of the first bonding pads PAD1 and the second bonding pads PAD2 can be polygonal in shape, and in the layout diagram, the sides of the polygon can each form an angle with respect to the row direction RD or the column direction CD. The angles formed relative to the row direction RD and the column direction CD can vary and can be angles other than 90 degrees and 180 degrees. That is, the shape of each of the first bonding pads PAD1 and the second bonding pads PAD2 can be implemented such that each of its sides is neither perpendicular nor horizontal with respect to the row direction RD and the column direction CD, or is not parallel to the row direction RD and the column direction CD. For example, a polygon with such a shape can be a rhombus in which each side forms an acute or obtuse angle with respect to the row and column directions. For another example, the shape of each of the first bonding pads PAD1 and the second bonding pads PAD2 is a square polygon, and one side of the second bonding pads PAD2 is rotated forty-five (45) degrees relative to the nearest side of the adjacent first bonding pad PAD1 in the first bonding pads PAD1.

[0075] In this way, if the shape of each of the first bonding pad PAD1 and the second bonding pad PAD2 is implemented such that the sides of the first bonding pad PAD1 and the sides of the second bonding pad PAD2 that are closest to each other are also parallel to each other, then the spacing between the adjacent first bonding pads PAD1 and the second bonding pads PAD2 can be increased to D3 even without reducing the size of the first bonding pads PAD1 and the second bonding pads PAD2.

[0076] According to this embodiment of the present disclosure, the spacing between adjacent first bonding pads PAD1 and second bonding pads PAD2 can be additionally increased by changing the shape of each of the first bonding pads PAD1 and second bonding pads PAD2 without changing the size or area of ​​the first bonding pads PAD1 and the second bonding pads PAD2, which makes it possible to further reduce the possibility of pad bonding failure.

[0077] Figure 7 This is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present disclosure. Elements not fully described below are related to those referenced above. Figure 2 The equivalent elements described are basically the same.

[0078] Reference Figure 7 In the line decoder region (XDR), multiple vertical contacts (CNT5) of the connection wiring W and multiple fourth bonding pads (PAD4) can be configured. The multiple fourth bonding pads (PAD4) can be configured only in the line decoder region (XDR) and not in the peripheral region (PR). The multiple second bonding pads (PAD2) bonded to the multiple fourth bonding pads (PAD4) can also be configured only in the line decoder region (XDR) and not in the peripheral region (PR).

[0079] The unit wafer CW may include power pins (not shown) for receiving power supply voltage from an external device, and wiring W may be power lines connected to the power pins.

[0080] The vertical contact CNT5 can pass through the source plate 12, multiple electrode layers 20, and multiple interlayer dielectric layers 22 in the vertical direction VD within the line decoder region XDR. The vertical contact CNT5 can be disposed only in the line decoder region XDR, and not in the peripheral region PR. To insulate the source plate 12 and the multiple electrode layers 20 from the vertical contact CNT5, a dielectric layer can be formed to surround the vertical contact CNT5.

[0081] Each vertical contact CNT5 can be configured to have a shape that extends in the vertical direction VD and overlaps with the corresponding fourth bonding pad PAD4. Therefore, each vertical contact CNT5 can be configured to have a length that is the same as or substantially the same as the shortest distance between the corresponding fourth bonding pad PAD4 and the wiring W.

[0082] although Figure 7 Each vertical contact CNT5 is illustrated as a through hole, but it should be noted that this disclosure is not limited thereto. The vertical contacts CNT5 can be formed as multiple through holes connected to each other and arranged in a row in the vertical direction VD.

[0083] Figure 8 This is a diagram illustrating a layout of bonding pads and vertical contacts that differs from the layout of bonding pads and vertical contacts according to embodiments of this disclosure. Components not fully described below are referenced above. Figure 2 and Figure 7 The equivalent elements described are basically the same.

[0084] Reference Figure 8 The fourth bonding pad PAD4 and the vertical contact CNT5 can be located in the peripheral region PR. The peripheral region PR is not used to house the transmission transistor PASS TR, therefore, in order to reduce the size of the semiconductor device, the area of ​​the peripheral region PR needs to be reduced.

[0085] like Figure 8 As shown, if the fourth bonding pad PAD4 and the vertical contact CNT5 are disposed in the peripheral region PR, the area of ​​the peripheral region PR will increase due to the area occupied by the fourth bonding pad PAD4 and the vertical contact CNT5, thereby increasing the size of the semiconductor device.

[0086] As referred above Figure 7In the embodiments of this disclosure described herein, if the fourth bonding pad PAD4 and the vertical contact CNT5 are disposed in the line decoder region XDR for setting the transmission transistor PASS TR, then it is not necessary to consume separate areas to set the fourth bonding pad PAD4 and the vertical contact CNT5, which allows for a reduction in the size of the semiconductor device.

[0087] Figure 9 This is a block diagram illustrating a memory system including a semiconductor device according to an embodiment of the present disclosure.

[0088] Reference Figure 9 The memory system 600 according to the embodiment may include a non-volatile memory device (NVM device) 610 and a memory controller 620.

[0089] The non-volatile memory device (NVM device) 610 can be constructed from the aforementioned semiconductor device and can operate in the manner described above. The memory controller 620 can be configured to control the non-volatile memory device (NVM device) 610. The combination of the non-volatile memory device (NVM device) 610 and the memory controller 620 can provide a memory card or solid-state drive (SSD). SRAM 621 serves as the working memory for the processing unit (CPU) 622. The host interface (host I / F) 623 includes a data exchange protocol for the host connected to the memory system 600.

[0090] Error correction code block (ECC) 624 detects and corrects errors included in data read from non-volatile memory device (NVM device) 610.

[0091] The memory interface (memory I / F) 625 is interfaced with the non-volatile memory device (NVM device) 610 of this embodiment. The processing unit (CPU) 622 performs overall control operations for data exchange with the memory controller 620.

[0092] Although not shown in the accompanying drawings, it will be apparent to those skilled in the art that the memory system 600 according to the embodiment may additionally include a ROM storing code data for connection to a host interface. The non-volatile memory device (NVM device) 610 may be provided as a multi-chip package comprising multiple flash memory chips.

[0093] The memory system 600 according to the above embodiment can be provided as a highly reliable storage medium with a low probability of error occurrence. Specifically, the non-volatile memory device of this embodiment can be included in memory systems that are currently under active research, such as solid-state drives (SSDs). In this case, the memory controller 620 can be configured to communicate with an external (e.g., a host) via one of various interface protocols such as USB (Universal Serial Bus) protocol, MMC (Multimedia Card) protocol, PCI-E (Rapid Peripheral Component Interconnect) protocol, SATA (Serial Advanced Technology Attached) protocol, PATA (Parallel Advanced Technology Attached) protocol, SCSI (Small Computer System Interface) protocol, ESDI (Enhanced Small Data Center Interface) protocol, and IDE (Integrated Drive Electronics) protocol.

[0094] Figure 10 This is a block diagram illustrating a computing system including a semiconductor device according to an embodiment of the present disclosure.

[0095] Reference Figure 10 The computing system 700 according to an embodiment may include a memory system 710, a microprocessor (CPU) 720, RAM 730, a user interface 740, and a modem 750 such as a baseband chipset, all electrically connected to a system bus 760. In the case where the computing system 700 according to an embodiment is a mobile device, a battery (not shown) may be additionally provided to provide the operating voltage for the computing system 700. Although not shown in the figures, it will be apparent to those skilled in the art that the computing system 700 according to an embodiment may additionally include an application chipset, a camera image processor (CIS), mobile DRAM, etc. The memory system 710 may be constructed, for example, using non-volatile memory to store data, as an SSD (Solid State Drive / Disk). Alternatively, the memory system 710 may be configured as a converged flash memory (e.g., OneNAND flash memory).

[0096] Although exemplary embodiments of this disclosure have been described for illustrative purposes, those skilled in the art will recognize that various modifications, additions, and substitutions can be made without departing from the scope and spirit of this disclosure. Therefore, the embodiments disclosed above and in the accompanying drawings should be considered in a descriptive sense only and not as limiting the scope of the technology. The scope of this disclosure is not limited by the embodiments and the accompanying drawings. The spirit and scope of this disclosure should be interpreted by the appended claims and cover all equivalents falling within the scope of the appended claims.

[0097] Cross-references to related applications

[0098] This application claims priority to Korean Patent Application No. 10-2020-0141856, filed with the Korean Intellectual Property Office on October 29, 2020, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor device, the semiconductor device comprising: A first wafer, the first wafer including a row decoder region, wherein a plurality of transmission transistors are arranged in the row direction and the column direction in the row decoder region; A plurality of first bonding pads, the plurality of first bonding pads being respectively connected to the plurality of transmission transistors and disposed in a plurality of rows on a surface of the first wafer in the row decoder region; as well as A plurality of second bonding pads are disposed on one surface of the first wafer in the row decoder region. The plurality of second bonding pads are disposed in a different row than the plurality of first bonding pads, and are offset relative to the plurality of first bonding pads in the row direction. The first wafer further includes a peripheral region in which the transmission transistor is not disposed, and wherein the plurality of second bonding pads are not disposed in the peripheral region.

2. The semiconductor device according to claim 1, wherein, The plurality of second bonding pads include power pads for transmitting power.

3. The semiconductor device according to claim 1, wherein, Each of the plurality of first bonding pads is configured to overlap with the source region of the corresponding transfer transistor in the vertical direction.

4. The semiconductor device according to claim 1, further comprising a plurality of active regions, in, A pair of transfer transistors from the plurality of transfer transistors are disposed in corresponding active regions of the plurality of active regions and share a drain region. Wherein, two first bonding pads from the plurality of first bonding pads that are adjacent to each other in the column direction are configured to overlap with two corresponding source regions of the pair of transfer transistors sharing a drain region in the vertical direction, and From a top-down view, one of the plurality of second bonding pads is configured to be offset relative to the drain region in the row direction.

5. The semiconductor device according to claim 1, wherein, From a top view, four of the plurality of first bonding pads form a quadrilateral region, and one of the plurality of second bonding pads is located at the central portion of the quadrilateral region.

6. The semiconductor device according to claim 1, wherein, Each of the plurality of first bonding pads and the plurality of second bonding pads is rhomboid in shape when viewed from above, wherein each side of the rhomboid shape forms an acute or obtuse angle relative to the row direction and the column direction.

7. The semiconductor device according to claim 1, wherein, Each of the plurality of first bonding pads and the plurality of second bonding pads is polygonal in shape, and the side of one of the first bonding pads is parallel to the nearest side of the adjacent second bonding pad among the plurality of second bonding pads.

8. The semiconductor device according to claim 1, further comprising: A second wafer, the second wafer being bonded to said one surface of the first wafer, The second wafer includes: A memory cell array, wherein the memory cell array is defined in a cell region; Multiple electrode layers extend from the cell region to the line decoder region, and the multiple electrode layers are stacked in the vertical direction and connected to the memory cell array; Multiple third bonding pads are respectively connected to the multiple electrode layers. The multiple third bonding pads have the same arrangement structure as the multiple first bonding pads and are respectively bonded to the multiple first bonding pads. A plurality of fourth bonding pads, the plurality of fourth bonding pads having the same arrangement as the plurality of second bonding pads and respectively bonding to the plurality of second bonding pads; and The wiring is coupled to the plurality of fourth bonding pads.

9. The semiconductor device according to claim 8, wherein, The wiring includes power lines.

10. The semiconductor device according to claim 4, wherein, Each of the plurality of first bonding pads and the plurality of second bonding pads is a square polygon, and the side of one of the plurality of second bonding pads is rotated forty-five degrees relative to the nearest side of the adjacent first bonding pad among the plurality of first bonding pads.

11. The semiconductor device according to claim 8, wherein, The second wafer also includes the peripheral region, and the plurality of fourth bonding pads are not located in the peripheral region.

12. A semiconductor device comprising: A cell wafer, the cell wafer including a memory cell array and a plurality of electrode layers, the memory cell array being defined in a cell region, the plurality of electrode layers being stacked on top of each other in a vertical direction, the plurality of electrode layers being connected to the memory cell array, and the plurality of electrode layers extending from the cell region to a line decoder region; A plurality of first bonding pads are disposed on a surface of the cell wafer in the row decoder region and are respectively connected to the plurality of electrode layers; A plurality of second bonding pads are disposed on one surface of the cell wafer in the row decoder region; The wiring is configured to be spaced apart from the second bonding pad in the vertical direction, and the plurality of electrode layers are interposed between the second bonding pad and the wiring; as well as Multiple vertical contacts are disposed in the line decoder area, and the multiple vertical contacts connect the multiple second bonding pads and the wiring. The unit wafer further includes a peripheral region, wherein the plurality of second bonding pads and the plurality of vertical contacts connecting the wiring to the plurality of second bonding pads are not located in the peripheral region.

13. The semiconductor device according to claim 12, wherein, The wiring includes power lines.

14. The semiconductor device of claim 12, further comprising: A peripheral wafer, which is bonded to one surface of the unit wafer. The peripheral wafer includes: Multiple transmission transistors are arranged in the row decoder region in both row and column directions; A plurality of third bonding pads, each of which is connected to a plurality of transmission transistors and is also bonded to a plurality of first bonding pads; and A plurality of fourth bonding pads, wherein the plurality of fourth bonding pads are respectively bonded to the plurality of second bonding pads.

15. The semiconductor device according to claim 14, in, The third bonding pad is set in multiple rows, and Each of the plurality of fourth bonding pads is located in a different row than the plurality of third bonding pads, and the plurality of fourth bonding pads are offset relative to the plurality of third bonding pads in the row direction.

16. The semiconductor device according to claim 15, wherein, From a top view, one of the plurality of fourth bonding pads is located at the central portion of a quadrilateral region defined by lines connecting four third bonding pads that are adjacent to each other in the row and column directions.

17. The semiconductor device according to claim 15, wherein, Each of the plurality of third bonding pads and the plurality of fourth bonding pads is rhomboid in shape, and each side of the rhomboid forms an acute or obtuse angle relative to the row direction and the column direction.

18. The semiconductor device according to claim 15, wherein, Each of the plurality of third bonding pads and the fourth bonding pad is polygonal in shape, such that the sides of the third bonding pads and the sides of the fourth bonding pads facing each other are parallel to each other.

19. The semiconductor device according to claim 12, wherein, The plurality of vertical contacts directly connect the plurality of second bonding pads and the wiring with the shortest possible distance.

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