Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the same, including: providing a substrate; forming a first dielectric layer on the substrate, a plurality of gate structures in the first dielectric layer, and a sidewall on sidewalls of the gate structures, and forming source-drain structures in the substrate on both sides of the gate structures, the first dielectric layer also being on surfaces of the source-drain structures, the sidewall including a first region and a second region on the first region; after forming the sidewall, etching the first dielectric layer to form a plurality of conductive openings in the first dielectric layer, the conductive openings exposing the surfaces of the source-drain structures, and the etching rate of the sidewall of the second region being less than the etching rate of the sidewall of the first region in the etching process of the first dielectric layer; and forming conductive structures in the conductive openings. Thus, the reliability of the semiconductor structure is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the rapid development of integrated circuit manufacturing technology, the size of semiconductor devices in integrated circuits is constantly shrinking, which effectively improves the operating speed of the entire integrated circuit. As the size requirements of components become smaller and smaller, the size of the conductive structures formed to connect with semiconductor devices also becomes smaller and smaller.

[0003] However, the reliability of existing semiconductor structures still needs to be improved. Summary of the Invention

[0004] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the reliability of the formed semiconductor structure.

[0005] To solve the above-mentioned technical problems, the present invention provides a semiconductor structure, comprising: a substrate; a plurality of gate structures located on the substrate; source and drain structures located in the substrate on both sides of the gate structures; a sidewall located on the sidewall of the gate structures, the sidewall comprising a first region and a second region located on the first region, wherein the first region and the second region are made of different materials; a first dielectric layer located on the substrate, the first dielectric layer also located on the sidewall of the sidewall; and a conductive structure located within the first dielectric layer and on the surface of the source and drain structures.

[0006] Optionally, the sidewall is made of a dielectric material containing silicon, and the silicon content in the material of the first region is less than the silicon content in the material of the second region.

[0007] Optionally, the silicon content in the material of the sidewall of the second zone is 20% to 50%.

[0008] Optionally, the sidewall is made of a dielectric material containing carbon, and the carbon content in the material of the first region is less than the carbon content in the material of the second region.

[0009] Optionally, the carbon content in the material of the sidewall of the second zone is 5% to 20%.

[0010] Optionally, the sidewalls of the first zone may be made of a low-k medium material.

[0011] Optionally, the material of the sidewall of the first region includes at least one of SiOC, SiOCN, and SiOCH.

[0012] Optionally, the top surface of the gate structure is lower than the top surface of the sidewall; the semiconductor structure further includes a gate protection structure located on the top surface of the gate structure.

[0013] Optionally, the bottom surface of the gate protection structure is lower than or flush with the top surface of the sidewall of the first region.

[0014] Optionally, the substrate includes a substrate and a plurality of fin structures located on the substrate, the gate structure spanning the fin structures, and the source / drain structures located within the fin structures on both sides of the gate structure.

[0015] Accordingly, the present invention also provides a method for forming the above-mentioned semiconductor structure, comprising: providing a substrate; forming a first dielectric layer, a plurality of gate structures located within the first dielectric layer, and sidewalls located on the sidewalls of the gate structures on the substrate, and forming source / drain structures in the substrate on both sides of the gate structures, wherein the first dielectric layer is also located on the surface of the source / drain structures, and the sidewalls include a first region and a second region located on the first region; after forming the sidewalls, etching the first dielectric layer to form a plurality of conductive openings within the first dielectric layer, wherein the conductive openings expose the surface of the source / drain structures, and wherein, in the process of etching the first dielectric layer, the etching rate of the sidewalls of the second region is less than the etching rate of the sidewalls of the first region; and forming conductive structures within the conductive openings.

[0016] Optionally, the sidewall is made of a dielectric material containing silicon, and the silicon content in the material of the first region is less than the silicon content in the material of the second region.

[0017] Optionally, the silicon content in the material of the sidewall of the second zone is 20% to 50%.

[0018] Optionally, the sidewall is made of a dielectric material containing carbon, and the carbon content in the material of the first region is less than the carbon content in the material of the second region.

[0019] Optionally, the carbon content in the material of the sidewall of the second zone is 5% to 20%.

[0020] Optionally, the sidewalls of the first zone may be made of a low-k medium material.

[0021] Optionally, the material of the sidewall of the first region includes at least one of SiOC, SiOCN, and SiOCH.

[0022] Optionally, the method for forming the sidewalls includes: forming a plurality of mutually discrete dummy gate structures on the substrate surface before forming the first dielectric layer and the gate structure; forming initial sidewalls on the sidewalls of the dummy gate structures; after forming the first dielectric layer, etching back the dummy gate structures until the initial sidewalls of the second region are exposed; using the first dielectric layer and the dummy gate structures as masks, modifying the initial sidewalls of the second region using a remote plasma processing technology to form the sidewalls.

[0023] Optionally, the material of the initial sidewall includes oxygen atoms, and the gas used in the remote plasma processing includes at least one of NH3 and H2.

[0024] Optionally, the parameters of the remote plasma processing process also include: the gas used includes one or all of N2 and NF3; the radio frequency power ranges from 500 watts to 2000 watts; and the gas flow rate of NH3 ranges from 500 sccm to 1500 sccm.

[0025] Optionally, the plasma includes capacitively coupled plasma, inductively coupled plasma, or electron cyclotron resonance plasma.

[0026] Optionally, the method of forming a plurality of the gate structures includes: after forming the sidewalls, removing the dummy gate structure and forming a plurality of gate openings in the first dielectric layer; filling the gate openings with the material of the gate structure to form the gate structure.

[0027] Optionally, it further includes: etching back the gate structure before forming the conductive opening to form a gate protection structure opening in the first dielectric layer; forming a gate protection structure in the protection structure opening, wherein the gate protection structure is also located on the top surface of the gate structure.

[0028] Optionally, the bottom surface of the gate protection structure is lower than or flush with the top surface of the sidewall of the first region.

[0029] Optionally, the method for forming the conductive opening includes: forming a conductive opening mask layer on the first dielectric layer, the sidewalls, and the gate structure, wherein the conductive opening mask layer exposes the surface of the first dielectric layer and part of the top surface of the sidewalls on the source / drain structure; using the conductive opening mask layer as a mask, etching the first dielectric layer until the surface of the source / drain structure is exposed.

[0030] Optionally, it further includes forming a second dielectric layer on the surface of the first dielectric layer, the top surface of the gate structure, and the top surface of the sidewall before forming the conductive opening mask layer.

[0031] Optionally, the material of the first dielectric layer includes silicon oxide, and the process parameters for etching the first dielectric layer include: a source power range of 500 watts to 1500 watts; a bias power range of 1000 watts to 3000 watts; a pressure range of 5 millitors to 80 millitors; and the gas used includes a gas containing carbon and fluorine elements, wherein the ratio of fluorine atoms to carbon atoms in the gas containing carbon and fluorine elements ranges from 1 to 2.

[0032] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0033] In the semiconductor structure formation method provided by the technical solution of the present invention, a sidewall located on the sidewall of the gate structure is formed on the substrate. The sidewall includes a first region and a second region located on the first region. In the process of etching the first dielectric layer, the etching rate of the sidewall of the second region is less than the etching rate of the sidewall of the first region. Therefore, the sidewall of the second region can increase the barrier capability of the material at the top of the sidewall to the etching process, thereby reducing the damage to the material at the top of the sidewall during the formation of the conductive structure, reducing the risk of short circuit between the conductive structure and the gate structure, and improving the reliability of the semiconductor structure.

[0034] Furthermore, since the sidewall material is a dielectric material including silicon, and the silicon content in the first region material is less than the silicon content in the second region material, increasing the silicon content in the second region material improves the etching selectivity of the etching process for the first dielectric layer on the material at the top of the sidewall (the material in the second region), thereby increasing the blocking ability of the material at the top of the sidewall (the material in the second region) on the etching process.

[0035] Furthermore, since the initial sidewalls of the second region are modified before the gate structure is formed, the impact of the modification process on the material of the gate structure is reduced, thereby improving the stability of the electrical characteristics of the semiconductor device.

[0036] Furthermore, since the initial sidewall material includes oxygen atoms, and the gas used in the remote plasma processing includes at least one of NH3 and H2, the hydrogen ions dissociated in the remote plasma processing can react with the oxygen atoms in the initial sidewall of the second region, reducing the oxygen atoms in the initial sidewall material of the second region. Thus, by reducing the oxygen atoms in the initial sidewall material of the second region, the silicon content ratio in the formed second region sidewall material is increased, thereby increasing the barrier capability of the material at the top of the sidewall (the material of the second region) against the etching process.

[0037] Furthermore, since the gas used in the remote plasma processing technology also includes one or all of N2 and NF3, after the dissociation of fluoride ions or nitrogen ions, the reaction between hydrogen ions and oxygen atoms can be accelerated by the fluoride ions or nitrogen ions, thereby improving the efficiency of oxygen atom reduction.

[0038] Furthermore, since the bottom surface of the gate protection structure is lower than or flush with the top surface of the sidewall of the first region, that is, the top surface of the gate structure is lower than or flush with the top surface of the sidewall of the first region, it is possible to improve the blocking ability of the top of the sidewall (the material of the second region) while reducing the influence on the material of the initial sidewall of the gate structure sidewall. That is, the sidewall of the gate structure sidewall (the sidewall of the first region) retains the material properties (dielectric constant, etc.) of the initial sidewall, thereby reducing the impact of the modification treatment on the electrical properties of the semiconductor device. Attached Figure Description

[0039] Figures 1 to 3 This is a schematic diagram of the steps involved in forming a semiconductor structure.

[0040] Figures 4 to 13 This is a cross-sectional structural schematic diagram of each step in a method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0041] As described in the background section, the reliability of existing semiconductor structures still needs to be improved.

[0042] The following detailed explanation, in conjunction with the accompanying drawings, explains why the reliability of semiconductor structures still needs improvement.

[0043] Figures 1 to 3 This is a schematic diagram of the steps involved in forming a semiconductor structure.

[0044] Please refer to Figure 1 A substrate 100 is provided, the substrate 100 including a substrate (not shown) and a plurality of fin structures (not shown) disposed on the substrate and disposed therebetween; a first dielectric layer (not shown) is formed on the surface of the substrate 100, the first dielectric layer covering a portion of the sidewalls of the fin structures.

[0045] Please continue to refer to this. Figure 1 A second dielectric layer 110 is formed on the surface of the first dielectric layer. The second dielectric layer 110 has a plurality of gate openings (not shown) that span the fin structure. The gate openings expose the surface and part of the sidewall of the fin structure. A gate structure 120, a gate protection structure 130 located on the top surface of the gate structure 120, and sidewalls 140 located on the sidewalls of the gate structure 120 and the sidewalls of the gate protection structure 130 are formed in the gate openings.

[0046] To reduce the parasitic capacitance of semiconductor devices, the sidewall 140 is made of low-k material.

[0047] Please refer to Figure 2 A third dielectric layer 150 is formed on the top surface of the gate protection structure 130, the top surface of the sidewall 140, and the surface of the second dielectric layer 110. A conductive opening mask layer 151 is formed on the surface of the third dielectric layer 150, and the conductive opening mask layer 151 has a plurality of conductive mask openings 152. Using the conductive opening mask layer 151 as a mask, the third dielectric layer 150 and the second dielectric layer 110 are etched until the surface of the substrate 100 is exposed, forming a conductive opening 111.

[0048] To reduce process complexity while forming small interconnect openings 111, on one hand, the process window size of the conductive opening mask layer 151 is increased by making the width D2 of the conductive mask opening 152 larger than the width D1 of the conductive opening 111, thereby reducing process complexity. On the other hand, while etching the third dielectric layer 150 and the second dielectric layer 110 using the conductive opening mask layer 151 as a mask, the edges of the sidewalls 140 and the gate protection structure 130 are exposed. Thus, through the sidewalls 140 and the gate protection structure 130, self-aligned contact (SAC) is achieved during the etching process of forming the conductive opening 111.

[0049] Please refer to Figure 3 An interconnection structure 160 is formed within the interconnection opening 111.

[0050] However, since the sidewall 140 is made of low-k material, which is typically porous and has a low dielectric constant, it also has a relatively loose material structure. Furthermore, because the edges of the sidewall 140 and the gate protection structure 130 are exposed, the top of the sidewall 140 is easily damaged. Therefore, when forming the interconnect opening 111, region A (such as...) Figure 2 and Figure 3 The gate structure 120 is easily exposed at the location shown, which can lead to a short circuit between the interconnect structure 160 and the gate structure 120, resulting in poor reliability of the semiconductor structure.

[0051] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure. Since a sidewall located on the sidewall of the gate structure is formed on the substrate, the sidewall includes a first region and a second region located on the first region. Furthermore, in the subsequent etching process of the first dielectric layer, the etching rate of the sidewall of the second region is less than the etching rate of the sidewall of the first region, thus improving the reliability of the semiconductor structure.

[0052] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0053] Figures 4 to 13 This is a cross-sectional structural schematic diagram of each step in a method for forming a semiconductor structure according to an embodiment of the present invention.

[0054] Please refer to Figure 4 Provides a base.

[0055] In this embodiment, the substrate includes a substrate 200 and a plurality of fin structures 201 disposed on the substrate 200.

[0056] The substrate 200 is made of semiconductor materials.

[0057] In this embodiment, the substrate 200 is made of silicon.

[0058] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI), etc. The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, etc.

[0059] In other embodiments, the fin structure includes: a plurality of fin sacrificial layers arranged in a direction perpendicular to the substrate surface, and nanosheets located between adjacent fin sacrificial layers.

[0060] Next, a first dielectric layer, a plurality of gate structures located within the first dielectric layer, and sidewalls located on the sidewalls of the gate structures are formed on the substrate. Source / drain structures are formed within the substrate on both sides of the gate structures. The first dielectric layer is also located on the surface of the source / drain structures. The sidewalls include a first region and a second region located on the first region. For specific steps on forming the first dielectric layer, gate structures, sidewalls, and source / drain structures, please refer to [link to documentation]. Figures 5 to 8 .

[0061] Please refer to Figure 5 A plurality of mutually independent pseudo-gate structures 210 are formed on the surface of the substrate; an initial sidewall 220 is formed on the sidewall of the pseudo-gate structure 210; after the initial sidewall 220 is formed, a source / drain structure 202 is formed in the substrate on both sides of the pseudo-gate structure 210; a first dielectric layer 230 is formed on the surface of the substrate, the surface of the source / drain structure 202, the top surface of the pseudo-gate structure 210, and the surface of the initial sidewall 220.

[0062] The initial sidewall 220 is used to form the sidewall in the subsequent process.

[0063] In this embodiment, the dummy gate structure 210 includes: a dummy gate dielectric film (not shown) located on the surface of the substrate, and a dummy gate (not shown) located on the surface of the dummy gate dielectric layer.

[0064] In other embodiments, the pseudo-gate structure is directly used as the gate structure, that is, the material of the gate structure includes polysilicon.

[0065] In this embodiment, the material of the dummy gate dielectric film includes silicon oxide, and the material of the dummy gate includes polysilicon.

[0066] In this embodiment, the method for forming the pseudo-gate structure 210 includes: forming a pseudo-gate material film (not shown) covering the surface of the fin structure 201 on the substrate; patterning the pseudo-gate material film until the substrate surface is exposed, so as to form a plurality of mutually discrete pseudo-gate structures 210 on the substrate, the pseudo-gate structures 210 spanning the fin structure 201, and the top surface of the pseudo-gate structure 210 being higher than the top surface of the fin structure 201.

[0067] The formation process of the pseudogate material film includes epitaxial growth or deposition processes, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0068] In this embodiment, the method for forming the initial sidewall 220 includes: depositing a sidewall material film (not shown) on the substrate surface and the surface of the dummy gate structure 210; using an anisotropic etching process, etching back the sidewall material film until the sidewall material film on the substrate surface and the top surface of the dummy gate structure 210 is removed, thereby forming an initial sidewall 220 on the sidewall of the dummy gate structure 210. The initial sidewall 220 includes a first region I and a second region II located on the first region I.

[0069] In this embodiment, the material of the initial sidewall 220 includes silicon.

[0070] In this embodiment, the material of the initial sidewall 220 also includes carbon.

[0071] Specifically, the material of the initial sidewall 220 includes a low-k dielectric material (k less than 3.9) or a combination of multiple low-k dielectric materials. The low-k dielectric material includes SiOC, SiOCN, and SiOCH, etc.

[0072] In other embodiments, the material of the initial sidewall includes silicon or carbon.

[0073] In this embodiment, the method for forming the source / drain structure 202 includes: after forming the initial sidewall 220, forming source / drain openings (not shown) within the fin structures 201 on both sides of the pseudo-gate structure 210; and forming the source / drain structure 202 within the source / drain openings using an epitaxial growth process. During the formation of the source / drain structure 202, the initial sidewall 220 is used to define the formation location of the source / drain structure 202.

[0074] The first dielectric layer 230 provides support for the formation of the gate structure and the first protective structure.

[0075] In this embodiment, the material of the first dielectric layer 230 is silicon oxide.

[0076] In this embodiment, the method for forming the first dielectric layer 230 includes: forming a first dielectric material layer (not shown) on the surface of the dummy gate structure 210 and the substrate, wherein the surface of the first dielectric material layer is higher than the top surface of the dummy gate structure 210; and planarizing the first dielectric material layer until the top surface of the dummy gate structure 210 is exposed.

[0077] The formation process of the first dielectric material layer includes spin coating or deposition processes, such as chemical vapor deposition, physical vapor deposition or atomic layer deposition.

[0078] The process for planarizing the first dielectric material layer includes: etch-back process or chemical mechanical polishing process, etc.

[0079] In this embodiment, before forming the first dielectric material layer, an etch stop layer 231 is formed on the substrate surface, the source / drain structure 202 surface, and the sidewalls of the initial sidewall 220. Therefore, the etch stop layer 231 protects the sidewalls and source / drain structure 202 during the subsequent etching process to form conductive openings, thereby reducing damage to the surfaces of the sidewalls and source / drain structure 202 caused by the etching process and improving the performance of the semiconductor structure.

[0080] In this embodiment, the material of the etch stop layer 231 includes silicon nitride.

[0081] In other embodiments, the material of the etch stop layer includes SiCN or SiOCN.

[0082] In this embodiment, before forming the dummy gate structure 210, a substrate dielectric layer (not shown) is also formed on the surface of the substrate 200. The substrate dielectric layer is also located on a portion of the sidewall of the fin structure 201. The function of the substrate dielectric layer is to provide electrical insulation between adjacent fin structures 201 and between the semiconductor device and the substrate.

[0083] Please refer to Figure 6 After the first dielectric layer 230 is formed, the pseudo gate structure 210 is etched back until the initial sidewall 220 of the second region II is exposed; using the first dielectric layer 230 and the pseudo gate structure 210 as a mask, the initial sidewall 220 of the second region II is modified by a remote plasma processing technology to form sidewall 221.

[0084] In this embodiment, the sidewall 221 includes a first zone I and a second zone II located on the first zone I.

[0085] It should be noted that the material of the sidewall 221 in the first zone I is the same as the material of the initial sidewall 220 that has not undergone the modification treatment, while the material of the sidewall 221 in the second zone II is the same as the material of the initial sidewall 220 that has undergone the modification treatment.

[0086] In this embodiment, the sidewall 221 is made of a dielectric material containing silicon, and the silicon content in the material of the first region I is less than the silicon content in the material of the second region II.

[0087] Since the sidewall 221 is a dielectric material containing silicon, and the silicon content in the material of the first region I is less than the silicon content in the material of the second region II, by increasing the silicon content in the material of the second region II in the formed sidewall 221, the etching selectivity of the material on top of the sidewall 221 (the material of the second region II) in the subsequent etching process of etching the first dielectric layer 230 to form a conductive opening is improved. That is, the etching rate of the etching process on the material of the second region II is reduced, thereby increasing the blocking ability of the material on top of the sidewall 221 to the etching process.

[0088] In this embodiment, the sidewall 221 is made of a dielectric material that also includes carbon elements, and the carbon content in the material of the first region I is less than the carbon content in the material of the second region II.

[0089] Since the material of the sidewall 221 is a dielectric material that also includes carbon, and the carbon content in the material of the first region I is less than the carbon content in the material of the second region II, by increasing the carbon content in the material of the second region II in the formed sidewall 221, the etching selectivity of the material on top of the sidewall 221 (the material of the second region II) in the subsequent etching process of etching the first dielectric layer 230 to form a conductive opening is improved. That is, the etching rate of the etching process on the material of the second region II is reduced, thereby increasing the blocking ability of the material on top of the sidewall 221 to the etching process.

[0090] In other embodiments, the sidewall is made of a dielectric material comprising silicon or carbon. Furthermore, when the sidewall material comprises silicon, the silicon content in the first region is less than the silicon content in the second region. When the sidewall material comprises carbon, the carbon content in the first region is less than the carbon content in the second region.

[0091] Specifically, in this embodiment, the material of the sidewall 221 of the first region I includes a low-k dielectric material or a combination of multiple low-k dielectric materials. The low-k dielectric material includes SiOC, SiOCN, and SiOCH, etc.

[0092] Specifically, the silicon content in the material of the sidewall 221 of the second zone II is 20% to 50%.

[0093] On the one hand, if the silicon content in the sidewall 221 of the second region II is too low, it will hinder the material at the top of the sidewall 221 from hindering the etching process of the first dielectric layer 230. In other words, the improvement in the barrier effect of the sidewall 221 of the second region II on the etching process of the first dielectric layer 230 will be relatively small. On the other hand, since the modification process is performed using a remote plasma processing technique, it is necessary to increase the temperature to achieve a higher silicon content in the material of the sidewall 221 of the second region II. When the silicon content in the material of the sidewall 221 of the second region II is too high, the high temperature during the remote plasma processing will affect the material of the fin structure 101 or other semiconductor devices, impacting the electrical performance of the semiconductor devices and causing a deterioration in the performance of the semiconductor structure. Therefore, by selecting an appropriate silicon content ratio, that is, when the silicon content ratio in the material of the sidewall 221 of the second region II is 20% to 50%, on the one hand, the material of the second region II is ensured to have the ability to block the etching process of the first dielectric layer 230, and on the other hand, the impact on the electrical performance of semiconductor devices and the like is reduced, thereby improving the performance of the semiconductor structure.

[0094] Specifically, the carbon content in the material of the sidewall 221 of the second zone II is 5% to 20%.

[0095] Similarly, by selecting an appropriate carbon content ratio, i.e., when the carbon content ratio in the material of the sidewall 221 of the second region II is 5% to 20%, on the one hand, the material of the second region II is ensured to have the ability to block the etching process of the first dielectric layer 230, and on the other hand, the impact on the electrical performance of semiconductor devices and the like is reduced, thereby improving the performance of the semiconductor structure.

[0096] In this embodiment, the gas used in the remote plasma processing technology includes at least one of NH3 and H2.

[0097] Since the initial sidewall material contains oxygen atoms, and the gases used in the remote plasma processing technology include NH3 and H2.

[0098] Furthermore, since the gas used in the remote plasma processing technology also includes one or all of N2 and NF3, after the dissociation of fluoride ions or nitrogen ions, the reaction between hydrogen ions and oxygen atoms can be accelerated by the fluoride ions or nitrogen ions, thereby improving the efficiency of oxygen atom reduction.

[0099] Specifically, since the material of the initial sidewall 220 includes oxygen atoms, and the gas used in the remote plasma processing includes at least one of NH3 and H2, the hydrogen ions dissociated in the remote plasma processing can react with the oxygen atoms in the initial sidewall 220 of the second region II, reducing the oxygen atoms in the material of the initial sidewall 220 of the second region II. Thus, by reducing the oxygen atoms in the material of the initial sidewall 220 of the second region II, the proportion of silicon in the material of the formed sidewall 221 of the second region II is increased, thereby increasing the barrier capability of the material on top of the sidewall 221 (the material of the second region II) against the etching process.

[0100] In this embodiment, the parameters of the remote plasma processing technology also include: the gas used includes one or all of N2 and NF3; the radio frequency power ranges from 500 watts to 2000 watts; and the gas flow rate of NH3 ranges from 500 sccm to 1500 sccm.

[0101] Therefore, by adjusting the parameters within the specified range, the silicon and carbon content in the material of the second region II can be adjusted to adjust the degree of increase in the silicon content ratio and the degree of increase in the carbon content ratio, so that the silicon content ratio in the material of the second region II is in the range of 20% to 50% and the carbon content ratio is in the range of 5% to 20%.

[0102] Furthermore, since the gas used in the remote plasma processing process also includes one or all of N2 and NF3, after the dissociation of fluoride ions or nitrogen ions, the reaction between hydrogen ions and oxygen atoms can be accelerated by the fluoride ions or nitrogen ions, thereby improving the efficiency of oxygen atom reduction.

[0103] In the remote plasma processing technology, the plasma includes capacitively coupled plasma, inductively coupled plasma, or electron cyclotron resonance plasma.

[0104] Please refer to Figure 7 After the sidewall 221 is formed, the pseudo-gate structure 210 is removed, and a plurality of gate openings 211 are formed in the first dielectric layer 230.

[0105] The gate opening 211 provides space for the subsequent formation of the gate structure.

[0106] Specifically, in this embodiment, after the sidewall 221 is formed, the pseudo-gate structure 210 is etched back until the pseudo-gate structure 210 is removed.

[0107] In this embodiment, the etching process of the pseudo-gate structure 210 includes at least one of dry etching or wet etching.

[0108] Please refer to Figure 8 The material of the gate structure 212 is filled in the gate opening 211 to form a plurality of gate structures 212 located in the first dielectric layer 230 on the substrate. The gate structure 212 spans the fin structure 201, and the source-drain structure 202 is located in the substrate on both sides of the gate structure 212.

[0109] Since the gate structure 212 is formed after the sidewall 221 is formed, that is, before the gate structure 212 is formed, the initial sidewall 220 of the second region II is modified to form the sidewall 221, thus reducing the impact of the modification process on the material of the gate structure 212 and improving the stability of the electrical characteristics of the semiconductor device.

[0110] In this embodiment, the gate structure 212 includes: a gate dielectric layer (not shown) located on the inner wall of the gate opening 211, a work function layer (not shown) located on the surface of the gate dielectric layer, and a gate electrode layer (not shown) located on the surface of the work function layer and filling the gate opening 211.

[0111] The gate dielectric layer is made of a high dielectric constant material (dielectric constant greater than 3.9). The high dielectric constant material includes: hafnium dioxide, hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, or aluminum oxide, etc.

[0112] The material of the gate electrode layer includes metallic materials, such as one or a combination of tungsten, copper, aluminum, titanium and tantalum.

[0113] The material of the work function layer includes titanium nitride, tantalum nitride, or titanium aluminum.

[0114] In this embodiment, the method for forming the gate structure 212 includes: forming a gate dielectric material layer (not shown) on the surface of the first dielectric layer 230 and the inner wall surface of the gate opening 211; forming a work function material layer (not shown) on the surface of the gate dielectric material layer; forming a gate electrode material layer (not shown) on the surface of the work function material layer, wherein the gate electrode material layer fills the gate opening 211; planarizing the gate electrode material layer, the work function material layer and the gate dielectric material layer until the surface of the first dielectric layer 230 is exposed, thereby forming the gate structure 212.

[0115] Next, in this embodiment, after forming the gate structure and before forming the conductive opening, a gate protection structure is formed on the top surface of the gate structure. For specific steps on forming the gate protection structure, please refer to [link to documentation]. Figures 9 to 10 .

[0116] Please refer to Figure 9 After the gate structure 212 is formed and before the conductive opening is formed, the gate structure 212 is etched back to form a gate protection structure opening 213 in the first dielectric layer 230.

[0117] The gate protection opening 213 provides space for the subsequent formation of the gate protection structure.

[0118] In this embodiment, the process of etching back the gate structure 212 includes at least one of dry etching process or wet etching process.

[0119] In this embodiment, the bottom surface of the gate protection structure opening 213 is lower than or flush with the top surface of the sidewall 221 of the first region I, so that the bottom surface of the subsequently formed gate protection structure is lower than or flush with the top surface of the sidewall 221 of the first region I.

[0120] Please refer to Figure 10 A gate protection structure 214 is formed within the opening 213 of the gate protection structure, and the gate protection structure 214 is also located on the top surface of the gate structure 212.

[0121] The gate protection structure 214 enhances the protection of the top surface of the gate structure 212 during the subsequent etching of the first dielectric layer 230 and formation of the conductive opening. This reduces the impact of the etching process on the gate structure 212, improving the performance of the semiconductor structure. Furthermore, the gate protection structure 214 increases the spacing between the top surface of the gate structure 212 and the top surface of the sidewall 221, reducing the risk of the gate structure 212 surface being exposed during the formation of the conductive opening. This reduces the risk of short circuits between the gate structure 212 and the conductive structures subsequently formed within the conductive opening, improving the reliability of the semiconductor structure. Moreover, the gate protection structure 214 and the sidewall 221 enable self-alignment (SAC) of the conductive opening pattern during the etching process.

[0122] In this embodiment, the bottom surface of the gate protection structure 214 is lower than or flush with the top surface of the sidewall 221 of the first region I.

[0123] Since the bottom surface of the gate protection structure 214 is lower than or flush with the top surface of the sidewall 221 of the first region I, that is, the top surface of the gate structure 212 is lower than or flush with the top surface of the sidewall 221 of the first region I, it is possible to improve the blocking ability of the top of the sidewall 221 (the material of the second region II) while reducing the influence on the material of the initial sidewall 220 of the sidewall of the gate structure 212. That is, the sidewall 221 of the sidewall of the gate structure 212 (the sidewall 221 of the first region I) retains the material properties (dielectric constant, etc.) of the initial sidewall 221, thereby reducing the impact of the modification treatment on the electrical properties of the semiconductor device.

[0124] In this embodiment, the method of forming the gate protection structure 214 further includes: forming a gate protection structure material layer (not shown) in the gate protection structure opening 213 and on the surface of the first dielectric layer 230; planarizing the gate protection structure material layer until the surface of the first dielectric layer 230 is exposed.

[0125] The process for forming the gate protection structure material layer includes spin coating or deposition processes, such as chemical vapor deposition, physical vapor deposition or atomic layer deposition.

[0126] The process for planarizing the gate protection structure material layer includes chemical mechanical polishing, dry etching, or wet etching.

[0127] In this embodiment, the material of the gate protection structure 214 includes silicon nitride.

[0128] In other embodiments, the material of the gate protection structure includes silicon carbide.

[0129] In other embodiments, after the gate structure is formed and before the gate protection structure is formed, the initial sidewall of the second region is modified to form a sidewall comprising a first region and a second region located on the first region, and in a subsequent process of etching the first dielectric layer to form a conductive opening within the first dielectric layer, the etching rate of the sidewall of the second region is less than the etching rate of the sidewall of the first region.

[0130] In other embodiments, no gate protection structure is formed.

[0131] In this embodiment, after forming the sidewall 221, the first dielectric layer 230 is etched to form a plurality of conductive openings within the first dielectric layer 230. For specific steps on forming the conductive openings, please refer to [link to documentation]. Figures 11 to 12 .

[0132] Please refer to Figure 11 A conductive opening mask layer 240 is formed on the first dielectric layer 230, the sidewall 221, and the gate structure 212. The conductive opening mask layer 240 exposes the surface of the first dielectric layer 230 and part of the top surface of the sidewall 221 on the source-drain structure 202.

[0133] By exposing not only the surface of the first dielectric layer 230 on the source / drain structure 202, but also the top surface of a portion of the sidewall 221, the process window for forming the pattern of the conductive opening mask layer 240 can be increased, thereby reducing the difficulty of the semiconductor structure formation process.

[0134] In this embodiment, before forming the conductive opening mask layer 240, a second dielectric layer 241 is formed on the surface of the first dielectric layer 230, the top surface of the gate structure 212, and the top surface of the sidewall 221.

[0135] Forming the second dielectric layer 241 helps improve the flatness of the semiconductor structure surface, thereby forming a conductive aperture mask layer 240 with higher pattern precision. Furthermore, during the subsequent formation of the conductive structure, the second dielectric layer 241 provides partial support for the material forming the conductive structure, and also serves as a sacrificial layer in the planarization process to meet the height requirements of etching or polishing in the planarization process.

[0136] In this embodiment, the material of the second dielectric layer 241 is silicon oxide.

[0137] In other embodiments, the material of the second dielectric layer includes at least one of SiOCH, SiOH, and SiCN.

[0138] Please refer to Figure 12 Using the conductive opening mask layer 240 as a mask, the first dielectric layer 230 is etched until the surface of the source / drain structure 202 is exposed. A plurality of conductive openings 242 are formed in the first dielectric layer 230, and the conductive openings 242 expose the surface of the source / drain structure 202. In the process of etching the first dielectric layer 230, the etching rate of the sidewall 221 of the second region II is less than the etching rate of the sidewall 221 of the first region I.

[0139] Since a sidewall 221 is formed on the substrate located on the sidewall of the gate structure 212, the sidewall 221 includes a first region I and a second region II located on the first region I. In the process of etching the first dielectric layer 230, the etching rate of the sidewall 221 of the second region II is less than the etching rate of the sidewall 221 of the first region I. Therefore, the sidewall 221 of the second region II can increase the barrier capability of the material on top of the sidewall 221 to the etching process, thereby reducing the damage to the material on top of the sidewall 221 during the subsequent formation of the conductive structure, reducing the risk of short circuit between the conductive structure and the gate structure 212, and improving the reliability of the semiconductor structure.

[0140] The etching process for the first dielectric layer 230 includes at least one of dry etching or wet etching.

[0141] In this embodiment, the process parameters for etching the first dielectric layer 230 include: a source power range of 500 watts to 1500 watts; a bias power range of 1000 watts to 3000 watts; a pressure range of 5 millitors to 80 millitors; and the gas used includes a gas containing carbon and fluorine elements, wherein the ratio of fluorine atoms to carbon atoms in the gas containing carbon and fluorine elements ranges from 1 to 2.

[0142] Specifically, in this embodiment, the method for forming the conductive opening 242 further includes: after etching the first dielectric layer 230, etching the etch stop layer 231 until the surface of the source / drain structure 202 is exposed.

[0143] In this embodiment, after the conductive opening 242 is formed, the conductive opening mask layer 240 is removed.

[0144] Please refer to Figure 13 A conductive structure 250 is formed within the conductive opening 242.

[0145] The method of forming the conductive structure 250 includes: forming a conductive structure material layer (not shown) inside the conductive opening 242 and on the surface of the second dielectric layer 241, the conductive structure material layer filling the conductive opening 242, and the surface of the conductive structure material layer being higher than the surface of the second dielectric layer 241; planarizing the conductive structure material layer until the gate protection structure 214 is exposed.

[0146] In this embodiment, the method for forming the conductive structure 250 further includes: after planarizing the conductive structure material layer until the gate protection structure 214 is exposed, continuing to planarize the conductive structure material layer and simultaneously planarizing the gate protection structure 214 until the width of the conductive structure 250 is consistent in the direction perpendicular to the extension direction of the gate structure 212.

[0147] In other embodiments, the conductive structure material layer and the gate protection structure are not further planarized after the gate protection structure is exposed.

[0148] The process for forming the conductive structural material layer includes deposition, electroplating, or electroless plating.

[0149] The process for planarizing the conductive structural material layer includes chemical mechanical polishing, dry etching, or wet etching.

[0150] In this embodiment, the material of the conductive structure 250 includes a metallic material, such as tungsten, copper, aluminum, titanium, or tantalum.

[0151] Accordingly, embodiments of the present invention also provide a semiconductor structure formed by the above method; please refer to [further details]. Figure 13 The system includes: a substrate 200; a plurality of gate structures 212 located on the substrate; source / drain structures 202 located in the substrate on both sides of the gate structures 212; sidewalls 214 located on the sidewalls of the gate structures 212, the sidewalls 214 including a first region I and a second region II located on the first region I, wherein the first region I and the second region II are made of different materials; and a first dielectric layer 230 located on the substrate (e.g., ...). Figure 12 As shown), the first dielectric layer 230 is also located on the side wall of the side wall 214; the conductive structure 250 is located within the first dielectric layer 230 and on the surface of the source / drain structure 202.

[0152] In this embodiment, the substrate includes a substrate 200 and a plurality of fin structures 201 disposed on the substrate 200. The gate structure 212 spans the fin structures 201, and the source / drain structure 202 is located within the fin structures 201 on both sides of the gate structure 212.

[0153] The substrate 200 is made of semiconductor materials.

[0154] In this embodiment, the substrate 200 is made of silicon.

[0155] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI), etc. The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, etc.

[0156] In other embodiments, the fin structure includes: a plurality of fin sacrificial layers arranged in a direction perpendicular to the substrate surface, and nanosheets located between adjacent fin sacrificial layers.

[0157] In this embodiment, the material of the first dielectric layer 230 is silicon oxide.

[0158] In this embodiment, the sidewall 221 is made of a dielectric material containing silicon, and the silicon content in the material of the first region I is less than the silicon content in the material of the second region II.

[0159] In this embodiment, the sidewall 221 is made of a dielectric material that also includes carbon elements, and the carbon content in the material of the first region I is less than the carbon content in the material of the second region II.

[0160] In other embodiments, the sidewall is made of a dielectric material comprising silicon or carbon. Furthermore, when the sidewall material comprises silicon, the silicon content in the first region is less than the silicon content in the second region. When the sidewall material comprises carbon, the carbon content in the first region is less than the carbon content in the second region.

[0161] Specifically, the material of the sidewall 221 of the first region I includes one low-k dielectric material or a combination of multiple low-k dielectric materials. The low-k dielectric material includes SiOC, SiOCN, and SiOCH, etc.

[0162] Specifically, the silicon content in the material of the sidewall 221 of the second zone II is 20% to 50%.

[0163] The carbon content in the material of the sidewall 221 of the second zone II is 5% to 20%.

[0164] In this embodiment, the gate structure 212 includes: located at the gate opening 211 (e.g., Figure 7The gate dielectric layer (not shown) on the inner wall surface, the work function layer (not shown) on the surface of the gate dielectric layer, and the gate electrode layer (not shown) on the surface of the work function layer and filling the gate opening 211.

[0165] The gate dielectric layer is made of a high dielectric constant material (dielectric constant greater than 3.9). The high dielectric constant material includes: hafnium dioxide, hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, or aluminum oxide, etc.

[0166] The material of the gate electrode layer includes metallic materials, such as one or a combination of tungsten, copper, aluminum, titanium and tantalum.

[0167] The material of the work function layer includes titanium nitride, tantalum nitride, or titanium aluminum.

[0168] In this embodiment, the top surface of the gate structure 212 is lower than the top surface of the sidewall 221.

[0169] In this embodiment, the semiconductor structure further includes a gate protection structure 214 located on the top surface of the gate structure 212.

[0170] In this embodiment, the bottom surface of the gate protection structure 214 is lower than or flush with the top surface of the sidewall 221 of the first region I.

[0171] In this embodiment, the material of the gate protection structure 214 includes silicon nitride.

[0172] In other embodiments, the material of the gate protection structure includes silicon carbide.

[0173] In other embodiments, the semiconductor structure does not include a gate protection structure.

[0174] In this embodiment, the material of the conductive structure 250 includes a metallic material, such as tungsten, copper, aluminum, titanium, or tantalum.

[0175] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: Provide a base; A first dielectric layer, a plurality of gate structures located within the first dielectric layer, and sidewalls located on the sidewalls of the gate structures are formed on the substrate, and source / drain structures are formed in the substrate on both sides of the gate structures. The first dielectric layer is also located on the surface of the source / drain structures, and the sidewalls include a first region and a second region located on the first region. After the sidewalls are formed, the first dielectric layer is etched to form a plurality of conductive openings in the first dielectric layer, the conductive openings exposing the source / drain structure surface, and in the process of etching the first dielectric layer, the etching rate of the sidewalls of the second region is less than the etching rate of the sidewalls of the first region. A conductive structure is formed within the conductive opening; The sidewall is made of a dielectric material containing silicon, and the silicon content in the material of the first region is less than the silicon content in the material of the second region. Alternatively, the sidewall is made of a dielectric material containing silicon, and the proportion of silicon in the material of the first region is less than the proportion of silicon in the material of the second region. The method for forming the sidewalls includes: forming a plurality of mutually discrete dummy gate structures on the surface of the substrate before forming the first dielectric layer and the gate structure; forming initial sidewalls on the sidewalls of the dummy gate structures; after forming the first dielectric layer, etching back the dummy gate structures until the initial sidewalls of the second region are exposed; using the first dielectric layer and the dummy gate structures as masks, modifying the initial sidewalls of the second region using a remote plasma processing technology to form the sidewalls.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, When the sidewall material is a dielectric material including silicon, the silicon content in the sidewall material of the second region is 20% to 50%.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, When the sidewall material is a dielectric material including silicon, the carbon content in the sidewall material of the second region is 5% to 20%.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The sidewalls of the first zone are made of low-k dielectric material.

5. The method for forming a semiconductor structure as described in claim 4, characterized in that, The sidewall material of the first region includes at least one of SiOC, SiOCN and SiOCH.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the initial sidewall includes oxygen atoms, and the gas used in the remote plasma processing includes at least one of NH3 and H2.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The parameters of the remote plasma processing technology also include: the gas used includes one or all of N2 and NF3; the radio frequency power ranges from 500 watts to 2000 watts; and the gas flow rate of NH3 ranges from 500 sccm to 1500 sccm.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The plasma in the remote plasma processing technology includes capacitively coupled plasma, inductively coupled plasma, or electron cyclotron resonance plasma.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, A method for forming a plurality of the gate structures includes: after forming the sidewalls, removing the dummy gate structure, forming a plurality of gate openings in the first dielectric layer; and filling the gate openings with the material of the gate structure to form the gate structure.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, Also includes: Before forming the conductive opening, the gate structure is etched back to form a gate protection structure opening within the first dielectric layer; A gate protection structure is formed within the opening of the gate protection structure, and the gate protection structure is also located on the top surface of the gate structure.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The bottom surface of the gate protection structure is lower than or flush with the top surface of the sidewall of the first region.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the conductive opening includes: forming a conductive opening mask layer on the first dielectric layer, the sidewalls, and the gate structure, wherein the conductive opening mask layer exposes the surface of the first dielectric layer and part of the top surface of the sidewalls on the source / drain structure; and etching the first dielectric layer using the conductive opening mask layer as a mask until the surface of the source / drain structure is exposed.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, Also includes: Before forming the conductive opening mask layer, a second dielectric layer is formed on the surface of the first dielectric layer, the top surface of the gate structure, and the top surface of the sidewall.

14. The method for forming a semiconductor structure as described in claim 9, characterized in that, The material of the first dielectric layer includes silicon oxide, and the process parameters for etching the first dielectric layer include: a source power range of 500 watts to 1500 watts; a bias power range of 1000 watts to 3000 watts; a pressure range of 5 millitors to 80 millitors; and the gas used includes a gas containing carbon and fluorine elements, wherein the ratio of fluorine atoms to carbon atoms in the gas containing carbon and fluorine elements ranges from 1 to 2.

15. A semiconductor structure, characterized in that, The semiconductor structure is formed using the semiconductor structure forming method according to any one of claims 1 to 14.

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