Ion implantation process optimization method and device, semiconductor structure and preparation method thereof

Abstract

The invention relates to the technical field of semiconductors, and discloses an ion implantation process optimization method and device, a semiconductor structure and a preparation method thereof.The ion implantation process optimization method comprises the steps that the current position of a current wafer in furnace tube equipment is obtained, the multiple wafers are arranged in the furnace tube equipment, polycrystalline silicon layers are formed on the wafers, and the polycrystalline silicon layers are arranged in the furnace tube equipment; the current wafer is a wafer to be subjected to ion implantation processing at the current moment in the plurality of wafers; according to the current position and a resistance deviation model, the resistance deviation of the polycrystalline silicon layer of the current wafer is determined, and the resistance deviation model is the corresponding relation between the position of the wafer and the resistance under the target temperature and the target gas flow field; according to the resistance deviation, optimization process parameters of the current wafer during ion implantation processing are determined, and the optimization process parameters are used for compensating the resistance deviation. According to the method, the resistance trend caused by the position of the furnace tube can be specifically compensated, the resistance uniformity between sheets is improved, the furnace tube equipment of the LPCVD does not need to be modified, and the production cost is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to an ion implantation process optimization method and device, a semiconductor structure and a preparation method thereof. BACKGROUND

[0002] In the manufacturing of Silicon On Insulator (SOI) based Complementary Metal Oxide Semiconductor (CMOS) radio frequency devices, High-Resistance Polysilicon (HRP) is deposited in a furnace tube by Low Pressure Chemical Vapor Deposition (LPCVD) to form Poly, and the resistance is adjusted by Ion Implantation (IMP) to meet the demand of high-precision resistance for radio frequency devices.

[0003] However, due to temperature gradient, gas flow field distribution and doping efficiency difference, the wafer at different positions (such as top, center and bottom) in the furnace tube has different grain size, thickness and doping concentration of Poly, which causes resistance fluctuation and inconsistent device performance, affecting the signal-to-noise ratio of radio frequency signals and manufacturing yield.

[0004] In related technologies, the position difference is reduced by improving the furnace tube design (such as increasing the uniformity of the heating zone) or optimizing the gas flow field, but these solutions require high-cost equipment upgrades and are difficult to completely eliminate the deviation. Another method is to rely on post-processing adjustment (such as annealing or trimming), but it lacks systematic optimization and has limited effect. SUMMARY

[0005] The present application provides an ion implantation process optimization method and device, a semiconductor structure and a preparation method thereof, which can improve the resistance unevenness problem caused by position difference in the LCPVD growth of Poly at a low cost.

[0006] In a first aspect, the present application provides an ion implantation process optimization method, comprising: obtaining a current position of a current wafer in a furnace tube device, wherein the furnace tube device is provided with a plurality of wafers, a polysilicon layer is formed on the wafer, and the current wafer is a wafer to be subjected to ion implantation treatment at the current time among the plurality of wafers; determining a resistance deviation of the polysilicon layer of the current wafer according to the current position and a resistance deviation model, wherein the resistance deviation model is a corresponding relationship between the position of the wafer and the resistance under a target temperature and a target gas flow field; and determining an optimized process parameter of the current wafer when subjected to ion implantation treatment according to the resistance deviation, wherein the optimized process parameter is used to compensate for the resistance deviation.

[0007] The embodiment can monitor the position of the wafer in the furnace tube device in real time, dynamically adjust the ion implantation parameters in combination with the pre-calibrated resistance deviation model, and compensate for the resistance trend caused by the position of the furnace tube in a targeted manner, so that the Poly resistance of each wafer in the furnace tube after ion implantation processing tends to be the target resistance, the resistance uniformity between wafers is improved, and the signal-to-noise ratio and manufacturing yield of the radio frequency device are improved. At the same time, the scheme can be implemented through the existing ion implantation equipment without modifying the furnace tube device of the LPCVD, thereby reducing the production cost.

[0008] In an optional embodiment, the resistance deviation of the polysilicon layer of the current wafer is determined according to the current position and the resistance deviation model, including: inputting the current position into the resistance deviation model, determining the initial resistance of the polysilicon layer of the current wafer according to the output of the resistance deviation model; and determining the resistance deviation according to the initial resistance and the reference resistance.

[0009] In an optional embodiment, the optimization of the process parameters includes optimization of the implantation dose, and the optimization of the process parameters of the current wafer during ion implantation processing is determined according to the resistance deviation, including: determining the target implantation dose according to the resistance deviation and a first correspondence relationship, wherein the first correspondence relationship is a correspondence relationship between a plurality of preset resistance deviations and implantation doses; and determining the target implantation dose as the optimized implantation dose.

[0010] In an optional embodiment, the optimization of the process parameters includes optimization of the implantation energy and optimization of the implantation angle, and the ion implantation process optimization method further includes: determining the resistance uniformity of the polysilicon layer of the current wafer after ion implantation processing on the current wafer; and in the case that the resistance uniformity is less than a preset uniformity, determining the optimized implantation energy and the optimized implantation angle of the current wafer of the next batch during ion implantation processing according to the resistance uniformity, so that the resistance of the polysilicon layer of the current wafer of the next batch at each position tends to be consistent.

[0011] In the embodiment, the resistance uniformity of the polysilicon layer of the current wafer is further determined after ion implantation processing on the current wafer, and in the case that the resistance uniformity is less than a preset uniformity, the optimized implantation energy and the optimized implantation angle of the current wafer of the next batch during ion implantation are determined according to the resistance uniformity, so that the resistance uniformity between wafers is improved while the resistance uniformity within a wafer is improved.

[0012] In an optional embodiment, the ion implantation process optimization method further includes: in the case that the structure of the furnace tube device changes or in the case that the target temperature and the target gas flow field change, updating the resistance deviation model.

[0013] In the embodiment, the resistance deviation model is updated based on the environmental change, the accuracy of the determined initial resistance is ensured, and the optimization accuracy is improved.

[0014] In an alternative embodiment, the ion doping type during the ion implantation process is phosphorus or boron.

[0015] In a second aspect, the present application provides a method for preparing a semiconductor structure, comprising: providing a plurality of wafers; depositing a polysilicon layer on each wafer in the plurality of wafers; and performing ion implantation processing on a current wafer according to an optimized process parameter, wherein the current wafer is a wafer in the plurality of wafers to be processed by ion implantation at a current time, and the optimized process parameter is obtained by the ion implantation process optimization method of the first aspect or any of the corresponding embodiments thereof.

[0016] In a third aspect, the present application provides a semiconductor structure prepared by the method for preparing a semiconductor structure of the second aspect or any of the corresponding embodiments thereof.

[0017] In a fourth aspect, the present application provides an ion implantation process optimization device, comprising: a position acquisition module configured to acquire a current position of a current wafer in a furnace tube device, wherein the furnace tube device is provided with a plurality of wafers, the wafers are formed with a polysilicon layer, and the current wafer is a wafer in the plurality of wafers to be processed by ion implantation at a current time; a deviation determination module configured to determine a resistance deviation of the polysilicon layer of the current wafer according to the current position and a resistance deviation model, wherein the resistance deviation model is a correspondence between the position of the wafer and the resistance under a target temperature and a target gas flow field; and an optimization module configured to determine an optimized process parameter of the current wafer during ion implantation processing according to the resistance deviation, and the optimized process parameter is used to compensate for the resistance deviation.

[0018] In a fifth aspect, the present application provides an electronic device, comprising: a memory and a processor, which are in communication connection with each other, and the memory stores computer instructions, and the processor executes the computer instructions to perform the ion implantation process optimization method of the first aspect or any of the corresponding embodiments thereof.

[0019] In a sixth aspect, the present application provides a computer readable storage medium, which stores computer instructions, and the computer instructions are used to make a computer execute the ion implantation process optimization method of the first aspect or any of the corresponding embodiments thereof.

[0020] In a seventh aspect, the present application provides a computer program product, which comprises computer instructions, and the computer instructions are used to make a computer execute the ion implantation process optimization method of the first aspect or any of the corresponding embodiments thereof. BRIEF DESCRIPTION OF DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the specific embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the specific embodiments or prior art description. Obviously, the drawings described below are some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0022] Figure 1 is a schematic diagram of an LPCVD process processing system according to an embodiment of the present application; Figure 2 is a flowchart of an ion implantation process optimization method according to an embodiment of the present application; Figure 3 is a flowchart of another ion implantation process optimization method according to an embodiment of the present application; Figure 4 is a flowchart of a semiconductor structure preparation method according to an embodiment of the present application; Figure 5 is a structural block diagram of an ion implantation process optimization device according to an embodiment of the present application; Figure 6 is a hardware structure schematic diagram of an electronic device according to an embodiment of the present application.

[0023] Reference signs: 11, furnace microcontroller; 12, pressure controller; 13, vacuum pump; 14, temperature controller; 15, heater; 16, furnace tube device; 17, gas flow controller; 20, wafer; 501, position acquisition module; 502, deviation determination module; 503, optimization module; 601, processor; 602, read-only memory; 603, random access memory; 604, bus; 605, input / output interface; 606, input device; 607, output device; 608, memory; 609, communication device. DETAILED DESCRIPTION

[0024] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the following will describe the technical solutions in the embodiments of the present application clearly and completely with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0025] In the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concepts of the present invention. Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. These drawings are not to scale, and some details are enlarged for clarity, and some details may be omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed. In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0026] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0027] The ion implantation process optimization method provided by this invention can be applied to the ion implantation process of HRP in 90nm node SOI-based CMOS RF devices to compensate for the resistance non-uniformity caused by positional differences during the low-pressure chemical vapor deposition (LPCVD) growth of polysilicon.

[0028] Low-pressure chemical vapor deposition (LPCVD) is a vapor deposition technique that uses sub-atmospheric pressure conditions to allow gaseous chemical precursors (reactant gases) to react chemically on the wafer surface, depositing a thin film. The low-pressure environment allows for more controlled reactions and provides more uniform film deposition.

[0029] For ease of understanding of the present invention, please refer to the accompanying drawings. Figure 1 The LPCVD process system shown illustrates the process of growing polycrystalline silicon using LPCVD.

[0030] like Figure 1As shown, the LPCVD process system includes a furnace microcontroller 11, a pressure controller 12, a vacuum pump 13, a temperature controller 14, a heater 15, a furnace tube device 16, and a gas flow controller 17. The furnace tube device 16 has a reaction chamber, in which a plurality of wafers 20 (substrates) that have been cleaned and surface-treated are first placed during processing, and then a reaction precursor gas (such as silane) is delivered to the reaction chamber after the flow rate thereof is adjusted by the gas flow controller 17. Thereafter, the reaction chamber is continuously pumped by the vacuum pump 13 to maintain a low pressure (a gas pressure lower than atmospheric pressure) in the reaction chamber, and the real-time pressure in the reaction chamber is detected and determined by the pressure controller 12. The low pressure environment helps to increase the gas diffusion length and reduce the generation of gaseous byproducts, thereby improving the uniformity of the thin film.

[0031] After the low pressure environment is established, the wafers 20 are heated to a specific temperature (such as 300-800°C) by the heater 15, and the gaseous precursor undergoes a chemical reaction (such as decomposition, combination, etc.) under thermal activation to generate a solid-state substance. The solid-state substance generated by the reaction nucleates and grows on the surface of the wafers 20, and gradually forms a uniform polysilicon thin film. The real-time temperature of the reaction chamber can be detected and determined by the temperature controller 14, and the excess gas and byproducts after the reaction can be pumped out by the vacuum pump 13 and discharged after treatment to avoid pollution.

[0032] The furnace microcontroller 11 is connected to a computer terminal through a computer terminal work interface, and precisely controls process parameters (such as pressure, temperature) through the pressure controller 12, the temperature controller 14, and the gas flow controller 17, so as to ensure that the thickness, composition, uniformity, and other performance indicators of the deposited thin film meet the requirements.

[0033] In the LPCVD process, the deposition of Poly is jointly affected by temperature, gas flow field, and doping efficiency, and there are differences in the temperature gradient and gas flow field distribution at different positions (such as the top, center, and bottom) in the furnace tube device, which leads to uneven grain size, thickness, and doping concentration of the Poly grown by the wafers 20 at different positions in the furnace tube device, and further causes fluctuations in the resistance value, usually in the range of ±10% or higher.

[0034] Specifically, the Poly deposition rate and temperature follow the Arrhenius equation, as shown in formula (1):

[0035] In formula (1), represents the deposition rate (nm / min), represents the pre-exponential factor, represents the activation energy, which is about 1.5 eV , represents the Boltzmann constant (8.617 x 10-5 ), represents absolute temperature (T) (K), K ).

[0036] Temperature distribution within the furnace tube apparatus is uneven (typically the top and bottom temperatures are about 5°C lower than the center), resulting in deposition rate differences. For example, the deposition rate is about 10 nm / min at 620°C, and decreases to 9.5 nm / min at 615°C, affecting the Poly thickness. In addition, temperature also determines the grain size, at lower temperature, the grain nucleation rate increases, the size decreases (e.g., from 25 nm to 20 nm), the grain boundary scattering is enhanced, and the carrier mobility is reduced.

[0037] The resistivity is related to the mobility and the doping concentration, which can be shown in equation (2):

[0038] wherein, represents resistivity (p) (ohm-cm), ), represents electronic charge (1.602 x 10 -19 Coulomb), represents carrier mobility (m ), represents carrier concentration. As can be seen from equation (2), when the temperature decreases, the carrier mobility decreases, and the resistivity of the Poly also decreases accordingly.

[0039] The HRP adjusts the resistance by in-situ doping (e.g., phosphorus or boron), and the incorporation rate of the dopant varies with temperature and gas concentration. The top wafer has a lower doping concentration due to the lower temperature and thinner gas, further exacerbating the resistance deviation.

[0040] The distribution of the gas (e.g., SiH4, nitrogen (N2), or dopant phosphine (PH3)) within the furnace tube apparatus is controlled by diffusion and convection, which can be approximately described by Fick's first law shown in equation (3).

[0041]

[0042] wherein, represents diffusion flux (J) (mol / m ), represents diffusion coefficient (m 2 / s), represents gas concentration (C) (mol / m ), represents axial position of the furnace tube apparatus (x) (m), m ​Fick's first law is the core law describing diffusion phenomenon, which is that the diffusion flux of a substance is proportional to the concentration gradient of the substance, and the direction is opposite, that is, diffusion always occurs from the high concentration area to the low concentration area.

[0043] In the reaction chamber, the bottom wafer close to the gas inlet contacts a higher concentration of SiH4 and dopant, the deposition rate and doping efficiency increase, resulting in a lower resistance; the top wafer is due to the depletion of the precursor, the deposition quality is reduced, resulting in a high resistance. As shown in Table 1, the experimental data, the Poly characteristics of the wafers at different positions in the furnace tube device are different.

[0044] Table 1 Distribution of each parameter at different positions

[0045] In order to improve the resistance uneven problem caused by position difference in the process of growing Poly by LPCVD, the present application provides an ion implantation process optimization method and device, a semiconductor structure and a preparation method thereof, which can monitor the position of the wafer in the furnace tube device in real time, combine the pre-calibrated resistance deviation model, dynamically adjust the ion implantation parameters, and realize the high consistency of HRP resistance.

[0046] The ion implantation process optimization method provided by the present application will be described in detail below with reference to the accompanying drawings. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a group of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0047] In this embodiment, an ion implantation process optimization method is provided, which can be used in a computer terminal or furnace microcontroller connected with the above furnace microcontroller, Figure 2 is a flowchart of an ion implantation process optimization method according to an embodiment of the present application, as Figure 2 shown, the flowchart includes the following steps: Step S201, obtaining the current position of the current wafer in the furnace tube device.

[0048] Among them, a plurality of wafers are arranged in the furnace tube device, and a polysilicon layer is formed on the wafer, the current wafer is a wafer in the plurality of wafers to be subjected to ion implantation processing at the current time, and the current position is the position of the current wafer in the furnace tube device.

[0049] Specifically, as Figure 1As shown, the furnace tube equipment 16 has a reaction chamber, in which multiple wafers 20 are placed at different positions. Before ion implantation, the current position of the wafer can be tracked by the Manufacturing Execution System (MES).

[0050] Each of the 20 wafers is assigned an identification identifier, which is bound to the wafer's basic information (such as batch, specifications, and target process) and stored in the MES system's database. During the wafer processing, the MES system monitors and records the wafer's flow path, location, processing status, and processing quality in real time.

[0051] Step S202: Determine the resistance deviation of the polysilicon layer of the current wafer based on the current position and the resistance deviation model.

[0052] The resistance deviation model represents the relationship between the wafer's position and resistance under target temperature and target gas flow field. Multiple resistance deviation models are pre-configured on the computer terminal. Each model corresponds to a different temperature range and gas flow field, with the target temperature being the temperature range currently occupied by the wafer and the target gas flow field being the gas flow field currently occupied by the wafer.

[0053] Resistance deviation is used to characterize the degree to which the resistance of the polysilicon layer on the current wafer deviates from the reference resistance. Resistance deviation can be expressed as a percentage, ratio, or difference. The reference resistance is the ideal resistance of the polysilicon grown on the wafer under the target temperature and target gas flow field. Designers divide the reaction chamber into a top region, a central region, and a bottom region. The average resistance of the polysilicon grown on the wafer located in the central region can be denoted as the reference resistance.

[0054] Specifically, after determining the current position and the resistance deviation model, based on the correspondence between the wafer position and the resistance represented by the resistance deviation model, the resistance value of the current wafer Poly corresponding to the current position can be obtained (denoted as the current resistance or the initial resistance); the difference between the current resistance and the reference resistance is determined as the resistance deviation.

[0055] For example, by combining data on different temperatures and gas distributions, poly can be deposited on the wafer using the LPCVD process. After LPCVD, the poly resistance at different locations on the wafer can be measured. Then, a resistance deviation model can be established based on the poly resistance at different locations on the wafer under different temperatures and gas distributions.

[0056] Step S203: Determine the optimized process parameters for the current wafer during ion implantation based on the resistance deviation.

[0057] The ion doping type during ion implantation is phosphorus or boron. The optimized process parameters during ion implantation can include at least one of optimized implantation dose, optimized implantation energy, and optimized implantation angle. The optimized process parameters are used to compensate for resistance deviations, so that the resistance of the polysilicon layer of the current wafer after ion implantation (denoted as the first resistance) is consistent with the target resistance, thereby making the resistance of the polysilicon layer of multiple wafers consistent after ion implantation. The target resistance is a preset value that can be determined by the designer according to process requirements.

[0058] When the first resistance and the target resistance are the same, they can be considered to be consistent. When the deviation between the first resistance and the target resistance is less than the preset deviation (such as 1% or 5%), they can also be considered to be consistent.

[0059] Specifically, the computer terminal is configured with reference process parameters (reference recipe) for the reference resistor. After determining the resistance deviation, the reference process parameters are optimized based on the resistance deviation to obtain the optimized process parameters.

[0060] For example, the baseline process parameters include a baseline implantation dose. If the current resistance is greater than the baseline resistance, and the resistance deviation is 20% of the baseline resistance, the baseline implantation dose can be increased by a first percentage as the optimized implantation dose. The polysilicon layer of the current wafer is then ion-implanted according to this optimized dose to reduce the current resistance. Here, the first percentage corresponds to the resistance deviation; after determining the resistance deviation, the first percentage can be obtained based on this correspondence.

[0061] If the current resistance is less than the reference resistance, and the resistance deviation is 20% of the reference resistance, the reference implantation dose can be reduced by the second percentage as the optimized implantation dose, and the polysilicon layer of the current wafer can be ion implanted according to the optimized implantation dose to improve the current resistance; if the current resistance is equal to the reference resistance, the reference implantation dose can be directly used as the optimized implantation dose.

[0062] The ion implantation process optimization method provided in this embodiment, after obtaining the current position of the current wafer in the furnace tube equipment, determines the resistance deviation of the polysilicon layer of the current wafer based on the current position and the resistance deviation model, and determines the optimized process parameters for the current wafer during ion implantation based on the resistance deviation.

[0063] This embodiment monitors the wafer's position within the furnace tube in real time and dynamically adjusts ion implantation parameters using a pre-calibrated resistance deviation model. This allows for targeted compensation of resistance trends caused by the furnace tube's position, ensuring that the poly resistance of each wafer in the furnace tube after ion implantation approaches the target resistance. This improves inter-wafer resistance uniformity, thereby enhancing the signal-to-noise ratio and manufacturing yield of RF devices. Furthermore, this solution can be implemented using existing ion implantation equipment without modifying the LPCVD furnace tube, reducing production costs.

[0064] In one example, using a SiH4 flow rate of 200 sccm and a temperature of 620°C, polysilicon layers were grown on multiple wafers via LPCVD to form polycrystalline silicon layers. Taking a target resistance of 2 kΩ as an example, without the ion implantation process optimization method provided by this invention, the resistance deviation of the polycrystalline silicon layers on different wafers was ±10%. After using the ion implantation process optimization method provided by this invention, the resistance of the polycrystalline silicon layer on the wafer located in the top region was approximately 2.05 kΩ, the resistance of the polycrystalline silicon layer on the wafer located in the center region was approximately 2 kΩ, and the resistance of the polycrystalline silicon layer on the wafer located in the bottom region was approximately 1.95 kΩ, with a resistance deviation of ±2.5%.

[0065] As can be seen, the present invention can reduce the inter-chip resistance deviation from ±10% to within ±2.5%, improve the inter-chip resistance uniformity, and improve the signal-to-noise ratio of RF devices by about 5% and the manufacturing yield by 5%-10%.

[0066] This embodiment also provides another ion implantation process optimization method, which can be used in a computer terminal or furnace microcontroller connected to the aforementioned furnace microcontroller. Figure 3 This is a flowchart of another ion implantation process optimization method according to an embodiment of the present invention, such as... Figure 3 As shown, the process includes the following steps: Step S301: Obtain the current position of the wafer in the furnace tube equipment.

[0067] Please see details Figure 2 Step S201 of the illustrated embodiment will not be described again here.

[0068] Step S302: Determine the resistance deviation of the polysilicon layer of the current wafer based on the current position and the resistance deviation model.

[0069] Specifically, step S302 above may include: Step S3021: Input the current position into the resistance deviation model, and determine the initial resistance of the polysilicon layer of the current wafer based on the output of the resistance deviation model.

[0070] For example, the resistance deviation model can be a machine learning model trained to convergence, the input of the resistance deviation model can be a position vector, and the output of the resistance deviation model can be the resistance value.

[0071] Specifically, after obtaining the current position, the current position is input into the resistance deviation model, and the output of the resistance deviation model is determined as the initial resistance of the polysilicon layer of the current wafer.

[0072] Step S3022: Determine the resistance deviation based on the initial resistance and the reference resistance.

[0073] In some embodiments, the ratio of the initial resistance to the reference resistance can be determined as the resistance deviation.

[0074] In other embodiments, the resistance deviation can be determined by the following formula (4).

[0075]

[0076] In the formula, Indicates resistance deviation. Indicates the initial resistance. This indicates the reference resistor.

[0077] It should be understood that when the structure of the furnace tube equipment changes or the target temperature and target gas flow field change, it is necessary to obtain the poly resistance of the wafer at different locations in the new environment through experiments, and update the resistance deviation model based on the newly obtained poly resistance of the wafer at different locations to ensure the accuracy of the determined initial resistance.

[0078] Step S303: Determine the optimized process parameters for the current wafer during ion implantation based on the resistance deviation.

[0079] Among these optimizations, the process parameters include optimizing the injection dosage. In this case, step S303 may include: Step S3031: Determine the target injection dose based on the resistance deviation and the first correspondence.

[0080] Step S3032: The target injection dose is determined as the optimized injection dose.

[0081] The first correspondence is the correspondence between multiple preset resistance deviations and injection doses.

[0082] Specifically, after obtaining the resistance deviation, the implantation dose corresponding to the resistance deviation can be determined based on the first correspondence. The implantation dose corresponding to the resistance deviation is the target implantation dose. Then, the target implantation dose is used as the optimized implantation dose, and the current wafer is subjected to ion implantation treatment according to the optimized implantation dose.

[0083] Step S304: After performing ion implantation on the current wafer, determine the resistance uniformity of the polysilicon layer on the current wafer.

[0084] In some embodiments, the resistance of the polysilicon layer of the current wafer at multiple measurement points can be obtained, and the resistance uniformity can be characterized by the average resistance at multiple measurement points.

[0085] In other embodiments, the resistance uniformity of the polysilicon layer of the current wafer can be characterized by formula (5).

[0086]

[0087] In the formula, This indicates the resistance uniformity of the polysilicon layer on the current wafer. This represents the standard deviation of the resistance at all measurement points. This represents the average resistance of the polycrystalline silicon layer.

[0088] Step S305: If the resistance uniformity is less than the preset uniformity, determine the optimized implantation energy and optimized implantation angle for the current wafer in the next batch during ion implantation based on the resistance uniformity.

[0089] Here, "next batch" refers to the next batch of wafers entering the furnace tube equipment, and "current wafer of the next batch" is the wafer in the same position as the current wafer of the current batch. Optimizing injection energy and injection angle is used to make the resistance of the polysilicon layer of the current wafer in the next batch more consistent at various locations, thereby improving the resistance uniformity within the wafer.

[0090] Specifically, the reference process parameters include reference implantation energy and reference implantation angle. When the resistance uniformity is less than the preset uniformity, the resistance uniformity input parameter adjustment model can be used. The target implantation energy and target implantation angle are determined based on the output of the parameter adjustment model. The target implantation energy is determined as the optimized implantation energy and the target implantation angle is determined as the optimized implantation angle. The next batch of the current wafer is then subjected to ion implantation treatment according to the optimized implantation energy and optimized implantation angle.

[0091] The parameter adjustment module is a trained machine learning model. The input of the parameter adjustment model is the resistance uniformity, and the output is the target injection energy and the target injection angle.

[0092] When the resistance uniformity is greater than or equal to the preset uniformity, the current wafer in the next batch is subjected to ion implantation treatment according to the reference implantation energy and reference implantation angle.

[0093] In this embodiment, after performing ion implantation on the current wafer, the resistance uniformity of the polysilicon layer of the current wafer is also determined. If the resistance uniformity is less than the preset uniformity, the optimized implantation energy and optimized implantation angle for the next batch of current wafers are determined based on the resistance uniformity. This can improve the resistance uniformity between wafers while improving the resistance uniformity within wafers.

[0094] This embodiment also provides a method for fabricating a semiconductor structure, such as... Figure 4 As shown, the method for fabricating a semiconductor structure includes the following steps: Step S401: Provide multiple wafers.

[0095] Step S402: A polycrystalline silicon layer is deposited on each of the plurality of wafers.

[0096] Specifically, through, as Figure 1 The LPCVD process system shown deposits polysilicon on each of the multiple wafers 20 to form a polysilicon layer.

[0097] Step S403: Perform ion implantation on the current wafer according to the optimized process parameters.

[0098] Here, the current wafer is the wafer to be ion implanted at the current moment among multiple wafers, and the optimized process parameters are obtained by the ion implantation process optimization method provided in any of the above embodiments.

[0099] This embodiment also provides a semiconductor structure, which is prepared by the semiconductor structure preparation method provided in the above embodiment.

[0100] This embodiment also provides an ion implantation process optimization apparatus for implementing the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0101] This embodiment provides an ion implantation process optimization device, such as... Figure 5 As shown, it includes: The position acquisition module 501 is used to acquire the current position of the current wafer in the furnace tube equipment, wherein the furnace tube equipment is provided with multiple wafers, and a polycrystalline silicon layer is formed on the wafers. The current wafer is the wafer that is to be ion implanted at the current moment among the multiple wafers. The deviation determination module 502 is used to determine the resistance deviation of the polysilicon layer of the current wafer based on the current position and the resistance deviation model, wherein the resistance deviation model is the correspondence between the position of the wafer and the resistance under the target temperature and the target gas flow field. The optimization module 503 is used to determine the optimized process parameters for the current wafer during ion implantation based on the resistance deviation. The optimized process parameters are used to compensate for the resistance deviation.

[0102] In some alternative implementations, the deviation determination module 502 includes: The first determining unit is used to input the current position into the resistance deviation model and determine the initial resistance of the polysilicon layer of the current wafer based on the output of the resistance deviation model. The second determining unit is used to determine the resistance deviation based on the initial resistance and the reference resistance.

[0103] In some optional implementations, optimizing process parameters includes optimizing the injection dose, and the optimization module 503 includes: The third determining unit is used to determine the target injection dose based on the resistance deviation and the first correspondence, wherein the first correspondence is a plurality of preset correspondences between resistance deviation and injection dose; The fourth determining unit is used to determine the target injection dose as the optimized injection dose.

[0104] In some alternative implementations, optimizing process parameters includes optimizing injection energy and optimizing injection angle, and the apparatus further includes: The uniformity determination module is used to determine the resistance uniformity of the polysilicon layer of the current wafer after ion implantation. The energy optimization module is used to determine the optimal implantation energy and optimal implantation angle for the next batch of current wafers during ion implantation when the resistance uniformity is less than the preset uniformity. The optimized implantation energy and optimal implantation angle are used to make the resistance of the polysilicon layer at various locations of the next batch of current wafers more uniform.

[0105] In some alternative embodiments, the apparatus further includes: An update module is used to update the resistance deviation model in the event of structural changes in the furnace tube equipment or changes in the target temperature and target gas flow field.

[0106] In some alternative implementations, the ion doping type during ion implantation is phosphorus or boron.

[0107] The ion implantation process optimization apparatus provided in this embodiment of the invention can execute the ion implantation process optimization method provided in any embodiment of the invention, and has the corresponding functional modules and beneficial effects for executing the method. Further functional descriptions of the above modules and units are the same as in the corresponding embodiments described above, and will not be repeated here.

[0108] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention.

[0109] The following is a detailed reference. Figure 6 This diagram illustrates a suitable structural design for implementing an electronic device according to embodiments of the present invention. The electronic device may include a processor (e.g., a central processing unit, graphics processor, etc.) 601, which can perform various appropriate actions and processes based on a program stored in read-only memory (ROM) 602 or a program loaded from memory 608 into random access memory (RAM) 603. RAM 603 also stores various programs and data required for the operation of the electronic device. The processor 601, ROM 602, and RAM 603 are interconnected via a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0110] Typically, the following devices can be connected to I / O interface 605: input devices 606 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 607 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; memory devices 608 including, for example, magnetic tapes, hard disks, etc.; and communication devices 609. Communication device 609 allows electronic devices to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 6 Electronic devices with various devices are shown, but it should be understood that it is not required to implement or have all of the devices shown, and more or fewer devices may be implemented or have instead.

[0111] In particular, according to embodiments of the present invention, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of the present invention include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 609, or installed from a memory 608, or installed from a ROM 602. When the computer program is executed by the processor 601, it performs the functions defined in the ion implantation process optimization method of the embodiments of the present invention.

[0112] Figure 6The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments of the present invention.

[0113] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as recordable on a storage medium, or implemented as computer code originally stored on a remote storage medium or a non-transitory machine-readable storage medium and subsequently stored on a local storage medium after being downloaded via a network. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code. When the software or computer code is accessed and executed by the computer, processor, or hardware, the ion implantation process optimization method shown in the above embodiments is implemented.

[0114] A portion of this invention can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to the invention through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions, or the computer compiling the instructions and then executing the corresponding compiled program, or the computer reading and executing the instructions, or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0115] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A method for optimizing an ion implantation process, characterized in that, include: The current position of the wafer in the furnace tube equipment is obtained, wherein the furnace tube equipment is provided with multiple wafers, and a polycrystalline silicon layer is formed on the wafers. The current wafer is the wafer among the multiple wafers that is to be subjected to ion implantation at the current moment. Based on the current position and the resistance deviation model, the resistance deviation of the polysilicon layer of the current wafer is determined, wherein the resistance deviation model is the correspondence between the position of the wafer and the resistance under the target temperature and the target gas flow field; Based on the resistance deviation, optimized process parameters are determined for the current wafer during ion implantation, and these optimized process parameters are used to compensate for the resistance deviation.

2. The ion implantation process optimization method according to claim 1, characterized in that, The step of determining the resistance deviation of the polysilicon layer of the current wafer based on the current position and the resistance deviation model includes: The current position is input into the resistance deviation model, and the initial resistance of the polysilicon layer of the current wafer is determined based on the output of the resistance deviation model. The resistance deviation is determined based on the initial resistance and the reference resistance.

3. The ion implantation process optimization method according to claim 1, characterized in that, The optimized process parameters include optimized implantation dose. Determining the optimized process parameters for the current wafer during ion implantation based on the resistance deviation includes: The target injection dose is determined based on the resistance deviation and the first correspondence, wherein the first correspondence is a plurality of preset correspondences between resistance deviations and injection doses; The target injection dose is determined as the optimized injection dose.

4. The ion implantation process optimization method according to any one of claims 1 to 3, characterized in that, The optimized process parameters include optimized implantation energy and optimized implantation angle, and the ion implantation process optimization method further includes: After performing ion implantation on the current wafer, the resistance uniformity of the polysilicon layer on the current wafer is determined; If the resistance uniformity is less than the preset uniformity, the optimized implantation energy and the optimized implantation angle for the next batch of current wafers during ion implantation are determined based on the resistance uniformity. The optimized implantation energy and the optimized implantation angle are used to make the resistance of the polysilicon layer at each location of the next batch of current wafers more consistent.

5. The ion implantation process optimization method according to any one of claims 1 to 3, characterized in that, The ion implantation process optimization method further includes: The resistance deviation model is updated in the event of structural changes in the furnace tube equipment or changes in the target temperature and target gas flow field.

6. The ion implantation process optimization method according to any one of claims 1 to 3, characterized in that, The ion doping type during ion implantation is phosphorus or boron.

7. A method for fabricating a semiconductor structure, characterized in that, include: Provide multiple wafers; A polycrystalline silicon layer is deposited on each of the plurality of wafers; Ion implantation is performed on the current wafer according to the optimized process parameters, wherein the current wafer is the wafer to be ion implanted at the current moment among the plurality of wafers, and the optimized process parameters are obtained by the ion implantation process optimization method according to any one of claims 1 to 6.

8. A semiconductor structure, characterized in that, The semiconductor structure is prepared by the semiconductor structure preparation method described in claim 7.

9. An ion implantation process optimization device, characterized in that, include: The position acquisition module is used to acquire the current position of the current wafer in the furnace tube equipment, wherein the furnace tube equipment is provided with multiple wafers, and a polycrystalline silicon layer is formed on the wafers. The current wafer is the wafer among the multiple wafers that is to be subjected to ion implantation at the current moment. The deviation determination module is used to determine the resistance deviation of the polysilicon layer of the current wafer based on the current position and the resistance deviation model, wherein the resistance deviation model is the correspondence between the position of the wafer and the resistance under the target temperature and the target gas flow field; An optimization module is used to determine optimized process parameters for the current wafer during ion implantation based on the resistance deviation, the optimized process parameters being used to compensate for the resistance deviation.

10. An electronic device, characterized in that, include: A memory and a processor are interconnected, the memory storing computer instructions, and the processor executing the computer instructions to perform the ion implantation process optimization method according to any one of claims 1 to 6.

11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing a computer to execute the ion implantation process optimization method according to any one of claims 1 to 6.

12. A computer program product, characterized in that, Includes computer instructions for causing a computer to execute the ion implantation process optimization method according to any one of claims 1 to 6.

Images