Bidirectional diode structure and method of manufacturing the same

Abstract

The application relates to a bidirectional diode structure and a preparation method thereof. The bidirectional diode structure comprises a first gate structure, a second gate structure located on one side of the first gate structure and having a spacing with the first gate structure, an anode located on one side of the first gate structure away from the second gate structure and having a spacing with the first gate structure, a cathode located on one side of the second gate structure away from the first gate structure and having a spacing with the second gate structure, a first capacitor, a first plate of the first capacitor being connected with the anode, and a second plate of the first capacitor being connected with the first gate structure, and a second capacitor, a first plate of the second capacitor being connected with the cathode, and a second plate of the second capacitor being connected with the second gate structure. The bidirectional diode can effectively release the accumulated static electricity caused by ESD, avoid the damage of ESD to the device structure, and enhance the ESD robustness of the device structure.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to a bidirectional diode structure and a preparation method thereof. BACKGROUND

[0002] In recent years, although GaN-based HEMTs (high electron mobility transistors) and MICs (monolithic integrated circuits) have superior working performance, they still face the threat of failure caused by ESD (electrostatic discharge) events, especially the gate of p-GaN (p-type gallium nitride) HEMTs and MOS (metal oxide semiconductor)-HEMTs is more fragile. In the prior art, due to the lack of discharge path of the gate of the p-GaN HEMT, the ESD robustness of the device under the condition of the gate to the source is poor, and in some fields, the ESD protection diode needs to have bidirectional protection capability, that is, in the positive and negative transient ESD events, the ESD protection diode needs to be triggered by a lower voltage. Therefore, there is still an urgent need for a bidirectional ESD protection diode to improve the ESD robustness of the GaN power system. SUMMARY

[0003] To solve the above technical problems, the present application designs a bidirectional diode structure and a preparation method thereof to reduce ESD static electricity and improve the ESD robustness of the device structure.

[0004] The present application designs a bidirectional diode structure, which comprises:

[0005] a first gate structure;

[0006] a second gate structure located on one side of the first gate structure and having a spacing with the first gate structure;

[0007] an anode located on a side of the first gate structure away from the second gate structure and having a spacing with the first gate structure;

[0008] a cathode located on a side of the second gate structure away from the first gate structure and having a spacing with the second gate structure;

[0009] a first capacitor, a first plate of the first capacitor being connected with the anode, and a second plate of the first capacitor being connected with the first gate structure;

[0010] a second capacitor, a first plate of the second capacitor is connected to the cathode, a second plate of the second capacitor is connected to the second gate structure.

[0011] In one embodiment, the first gate structure comprises:

[0012] a first gate;

[0013] a first gate contact layer on a surface of the first gate;

[0014] a first floating gate on a surface of the first gate contact layer away from the first gate, connected to the second plate.

[0015] In one embodiment, the second gate structure comprises:

[0016] a second gate;

[0017] a second gate contact layer on a surface of the first gate;

[0018] a second floating gate on a surface of the second gate contact layer away from the second gate, connected to the second plate of the second capacitor.

[0019] In one embodiment, the bidirectional diode structure further comprises:

[0020] a substrate;

[0021] an epitaxial layer on a surface of the substrate;

[0022] a barrier layer on a surface of the epitaxial layer away from the substrate; the first gate structure, the second gate structure, the anode, the cathode and the capacitor are all on a surface of the barrier layer away from the epitaxial layer.

[0023] In one embodiment, the bidirectional diode structure further comprises:

[0024] a floating electrode on a surface of the barrier layer away from the epitaxial layer, and between the first gate structure and the second gate structure, with a spacing from both the first gate structure and the second gate structure.

[0025] In one embodiment, the bidirectional diode structure further comprises:

[0026] a first passivation layer on a surface of the barrier layer away from the epitaxial layer, between the anode and the cathode, and surrounding the first gate structure, the second gate structure and the floating electrode;

[0027] a second passivation layer on a surface of the first passivation layer away from the barrier layer.

[0028] The application also provides a preparation method of a bidirectional diode structure, which comprises the following steps:

[0029] forming a first gate structure, a second gate structure, an anode, a cathode, a first capacitor and a second capacitor; the second gate structure is located on one side of the first gate structure and has a spacing with the first gate structure; the anode is located on one side of the first gate structure away from the second gate structure and has a spacing with the first gate structure; the cathode is located on one side of the second gate structure away from the first gate structure and has a spacing with the second gate structure; a first plate of the first capacitor is connected with the anode, and a second plate of the first capacitor is connected with the first gate structure; a first plate of the second capacitor is connected with the cathode, and a second plate of the second capacitor is connected with the second gate structure.

[0030] In one of the embodiments, before the forming of the first gate structure, the second gate structure, the anode, the cathode, the first capacitor and the second capacitor, the method further comprises:

[0031] providing a substrate;

[0032] forming an epitaxial layer on the surface of the substrate;

[0033] forming a barrier layer on the surface of the epitaxial layer away from the substrate.

[0034] In one of the embodiments, the first gate structure comprises a first gate, a first gate contact layer and a first floating gate; the second gate structure comprises a second gate, a second gate contact layer and a second floating gate; the forming of the first gate structure, the second gate structure, the anode, the cathode, the first capacitor and the second capacitor comprises:

[0035] forming the first gate and the second gate on the surface of the barrier layer away from the epitaxial layer;

[0036] forming a first passivation layer on the surface of the barrier layer away from the epitaxial layer, the first passivation layer being located on the periphery of the first gate and the periphery of the second gate;

[0037] forming the anode and the cathode on the surface of the barrier layer away from the epitaxial layer; the anode is located on one side of the first passivation layer, and the cathode is located on one side of the first passivation layer;

[0038] forming the first gate contact layer on the surface of the first gate away from the barrier layer; forming the second gate contact layer on the surface of the second gate away from the barrier layer; forming the first plate of the first capacitor and the first plate of the second capacitor on the surface of the barrier layer away from the epitaxial layer, the first plate of the first capacitor being connected with the anode, and the first plate of the second capacitor being connected with the cathode;

[0039] forming a dielectric material layer covering the first passivation layer, the anode, the cathode, the first gate contact layer, the second gate contact layer, the first plate of the first capacitor and the first plate of the second capacitor;

[0040] etching the dielectric material layer to form a second passivation layer on the surface of the first passivation layer away from the barrier layer, a first capacitor dielectric layer on the surface of the first plate of the first capacitor away from the barrier layer, and a second capacitor dielectric layer on the surface of the first plate of the second capacitor away from the barrier layer;

[0041] forming the first floating gate on the surface of the first gate contact layer away from the first gate, the second floating gate on the surface of the second gate contact layer away from the second gate, the second plate of the first capacitor on the surface of the first capacitor dielectric layer away from the first plate of the first capacitor, and the second plate of the second capacitor on the surface of the second capacitor dielectric layer away from the first plate of the second capacitor, the second plate of the first capacitor being connected with the first floating gate, and the second plate of the second capacitor being connected with the second floating gate.

[0042] In one embodiment, the forming the anode and the cathode on the surface of the barrier layer away from the epitaxial layer also forms a first floating electrode layer on the surface of the barrier layer away from the epitaxial layer, the first floating electrode layer being located in the first passivation layer and between the first gate and the second gate, and having a spacing with the first gate and the second gate; the forming the first floating gate, the second floating gate, the second plate of the first capacitor and the second plate of the second capacitor also forms a second floating electrode layer on the surface of the first floating electrode layer away from the barrier layer, the first floating electrode layer and the second floating electrode layer together constituting a floating electrode.

[0043] The present application has the following advantages:

[0044] The bidirectional diode structure of the application comprises: a first gate structure; a second gate structure located on one side of the first gate structure and having a spacing with the first gate structure; an anode located on one side of the first gate structure away from the second gate structure and having a spacing with the first gate structure; a cathode located on one side of the second gate structure away from the first gate structure and having a spacing with the second gate structure; a first capacitor, a first pole plate of the first capacitor being connected with the anode, and a second pole plate of the first capacitor being connected with the first gate structure; and a second capacitor, a first pole plate of the second capacitor being connected with the cathode, and a second pole plate of the second capacitor being connected with the second gate structure. The first capacitor connects the anode and the first gate structure, and the second capacitor connects the cathode and the second gate structure. The first capacitor and the second capacitor can reduce the opening voltage of ESD to below 10V. During a forward transient ESD event, a high dv / dt (voltage change rate) can induce a capacitive coupling current, which carries a certain amount of positive transition charge to the first gate structure and the second gate structure. The positive transition charge is stored in the first gate structure and the second gate structure, which can pull down the energy band in the first gate structure and the second gate structure, and force electrons to gather under the first gate structure and the second gate structure. When the gate potential generated by the positive transition charge reaches a certain value, a large current can pass through the first gate structure and the second gate structure, so that the accumulated static charge caused by the ESD event can be effectively released, and the damage of the ESD event to the first gate structure and the second gate structure can be avoided, thereby enhancing the ESD robustness of the first gate structure and the second gate structure. BRIEF DESCRIPTION OF DRAWINGS

[0045] Figure 1 FIG. 1 is a structural schematic diagram of a bidirectional diode structure in an embodiment of the application;

[0046] Figure 2 FIG. 2 is an equivalent circuit diagram of the bidirectional diode structure in the embodiment of the application;

[0047] Figure 3 FIG. 3 is a flowchart of a preparation method of the bidirectional diode structure in the embodiment of the application;

[0048] Figure 4 FIG. 4 is a flowchart of forming a first gate structure, a second gate structure, an anode, a cathode, a first capacitor and a second capacitor in the preparation method of the bidirectional diode structure in the embodiment of the application;

[0049] Figure 5 FIG. 5 is a sectional structural schematic diagram of a structure obtained in steps S301 to S303 in the preparation method of the bidirectional diode structure in the embodiment of the application;

[0050] Figure 6is a cross-sectional structure schematic diagram of a structure obtained in step S401 in a preparation method of a bidirectional diode structure in one embodiment of the present application;

[0051] Figure 7 is a cross-sectional structure schematic diagram of a structure obtained after depositing a dielectric material layer on the barrier layer in a preparation method of a bidirectional diode structure in one embodiment of the present application;

[0052] Figure 8 is a cross-sectional structure schematic diagram of a structure obtained in step S402 in a preparation method of a bidirectional diode structure in one embodiment of the present application;

[0053] Figure 9 is a cross-sectional structure schematic diagram of a structure obtained in step S403 in a preparation method of a bidirectional diode structure in one embodiment of the present application;

[0054] Figure 10 is a cross-sectional structure schematic diagram of a structure obtained in step S404 in a preparation method of a bidirectional diode structure in one embodiment of the present application;

[0055] Figure 11 is a cross-sectional structure schematic diagram of a structure obtained in step S405 in a preparation method of a bidirectional diode structure in one embodiment of the present application;

[0056] Figure 12 is a cross-sectional structure schematic diagram of a structure obtained in step S406 in a preparation method of a bidirectional diode structure in one embodiment of the present application;

[0057] Figure 13 is a cross-sectional structure schematic diagram of a structure obtained in step S407 in a preparation method of a bidirectional diode structure in one embodiment of the present application.

[0058] BRIEF DESCRIPTION OF THE DRAWINGS

[0059] 1, substrate; 2, epitaxial layer; 3, two-dimensional electron gas channel; 4, barrier layer; 5, first gate structure; 51, first gate; 52, first gate contact layer; 53, first floating gate; 6, second gate structure; 61, second gate; 62, second gate contact layer; 63, second floating gate; 7, first passivation layer; 8, second passivation layer; 9, anode; 10, cathode; 11, floating electrode; 111, first floating electrode layer; 112, second floating electrode layer; 12, first capacitor; 121, first plate of the first capacitor; 122, first capacitor dielectric layer; 123, second plate of the first capacitor; 13, second capacitor; 131, first plate of the second capacitor; 132, second capacitor dielectric layer; 133, second plate of the second capacitor; 14, gate material layer; 151, dielectric material layer; 152, dielectric material layer. DETAILED DESCRIPTION

[0060] In order to make the above objectives, features and advantages of the present application more clear and comprehensible, the specific embodiments of the present application will be described below in detail with reference to the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, the present application can be practiced in many different manners without the specific details, and it is to be understood that the present application is not limited to the specific embodiments described below and that the specific embodiments are given for the purposes of exemplification only.

[0061] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0062] In addition, the terms "first", "second", "third" and the like are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined with "first", "second" and the like can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "a plurality of" is at least two, for example, two, three, etc., unless otherwise explicitly specified and limited.

[0063] In the present application, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection", "fixing" and the like should be understood broadly, for example, it can be fixed connection, or detachable connection, or integral; it can be mechanical connection, or electrical connection; it can be direct connection, or indirect connection through intermediate medium, it can be the internal communication of two elements or the interaction relationship between two elements, unless otherwise explicitly limited. For ordinary skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0064] In the present application, unless otherwise explicitly specified and limited, the first feature "on" or "under" the second feature can be direct contact between the first and second features, or indirect contact between the first and second features through intermediate medium. Moreover, the first feature "above", "above" and "above" the second feature can be directly above or obliquely above the first feature, or only indicate that the horizontal height of the first feature is higher than that of the second feature. The first feature "below", "below" and "below" the second feature can be directly below or obliquely below the first feature, or only indicate that the horizontal height of the first feature is less than that of the second feature.

[0065] It is to be understood that when an element such as a layer, region or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element or intervening elements can be present. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0066] In order to make the purposes, technical solutions and advantages of the present application clearer, further detailed description will be made to the present application in combination with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.

[0067] In recent years, although GaN-based HEMTs (high electron mobility transistors) and MICs (monolithic integrated circuits) have superior operating performance, they still face the threat of failure caused by ESD (electrostatic discharge) events, especially the gate of p-GaN (p-type gallium nitride) HEMTs and MOS (metal oxide semiconductor)-HEMTs is more fragile. In the prior art, due to the lack of discharge path of the gate of the p-GaN HEMT, the ESD robustness of the device under the condition of the gate to the source is poor, and in some fields, the ESD protection diode needs to have bidirectional protection capability, that is, in the positive and negative transient ESD events, the ESD protection diode needs to be triggered by a lower voltage. Therefore, there is still an urgent need for a bidirectional ESD protection diode to improve the ESD robustness of the GaN power system.

[0068] ESD (electrostatic discharge): due to the surface of the object under the action of friction, induction, conduction and other effects, when the distance between two charged bodies is within the discharge distance of the electric charge, discharge occurs. Robust is the transliteration of Robust, and robustness in this paper refers to the characteristics of a control system to maintain certain performance under certain (structure, size) parameter perturbations.

[0069] To solve the above technical problems, the present application designs a bidirectional diode structure and a preparation method thereof to reduce ESD static electricity and improve the ESD robustness of the device structure.

[0070] The application designs a bidirectional diode structure, which comprises a first gate structure 5, a second gate structure 6, an anode 9, a cathode 10, a first capacitor 12 and a second capacitor 13; the second gate structure 6 is located on one side of the first gate structure 5 and has a spacing with the first gate structure 5; the anode 9 is located on one side of the first gate structure 5 away from the second gate structure 6 and has a spacing with the first gate structure 5; the cathode 10 is located on one side of the second gate structure 6 away from the first gate structure 5 and has a spacing with the second gate structure 6; the first plate 121 of the first capacitor 12 is connected with the anode 9, and the second plate 123 of the first capacitor 12 is connected with the first gate structure 5; the first plate 131 of the second capacitor 13 is connected with the cathode 10, and the second plate 133 of the second capacitor 13 is connected with the second gate structure 6.

[0071] The bidirectional diode structure of the application comprises the first gate structure 5, the second gate structure 6, the anode 9, the cathode 10, the first capacitor 12 and the second capacitor 13; by arranging the first capacitor 12 and the second capacitor 13, the opening voltage of ESD can be reduced to below 10V; and during a forward transient ESD event, a high dv / dt (voltage change rate) can induce a capacitive coupling current, the capacitive coupling current will carry a certain amount of positive transition charge to the first gate structure 5 and the second gate structure 6, the positive transition charge will be stored in the first gate structure 5 and the second gate structure 6, which can pull down the energy band in the first gate structure 5 and the second gate structure 6 and force the electrons to gather under the first gate structure 5 and the second gate structure 6, when the gate potential generated by the positive transition charge reaches a certain value, a large current can pass through the first gate structure 5 and the second gate structure 6, so that the accumulated static charge caused by the ESD event can be effectively released, and the damage of the ESD event to the first gate structure 5 and the second gate structure 6 can be avoided, thereby enhancing the ESD robustness of the first gate structure 5 and the second gate structure 6.

[0072] Specifically, the material of the anode 9 can include but is not limited to titanium aluminum nickel gold; the material of the cathode 10 can include but is not limited to titanium aluminum nickel gold; the material of the first plate 121 of the first capacitor 12 and the second plate 123 of the first capacitor 12 can each include but is not limited to nickel gold; the material of the first plate 131 of the second capacitor 13 and the second plate 133 of the second capacitor 13 can each include but is not limited to nickel gold.

[0073] Specifically, still referring to Figure 1 The first capacitor 12 further has a first capacitor dielectric layer 122 between the first plate 121 of the first capacitor 12 and the second plate 123 of the first capacitor 12, which is used to connect the first plate 121 of the first capacitor 12 and the second plate 123 of the first capacitor 12, and the first capacitor dielectric layer 122 can include but is not limited to SiN xa first capacitor dielectric layer 132 between the first plate 131 of the second capacitor 13 and the second plate 133 of the second capacitor 13 for connecting the first plate 131 of the second capacitor 13 and the second plate 133 of the second capacitor 13, the first capacitor dielectric layer 132 can include but is not limited to SiN x layer.

[0074] In one embodiment, the first gate structure 5 includes: a first gate 51; a first gate contact layer 52 on the surface of the first gate 51; a first floating gate 53 on the surface of the first gate contact layer 52 away from the first gate 51, connected to the second plate.

[0075] In one embodiment, the second gate structure 6 includes: a second gate 61; a second gate contact layer 62 on the surface of the first gate 51; a second floating gate 63 on the surface of the second gate contact layer 62 away from the second gate 61, connected to the second plate 133 of the second capacitor 13.

[0076] Specifically, the material of the first gate 51 can include p-GaN (p-type gallium nitride); the material of the first gate contact layer 52 can include but is not limited to nickel gold; the material of the first floating gate 53 can include but is not limited to nickel gold; the material of the second gate 61 can include p-GaN (p-type gallium nitride); the material of the second gate contact layer 62 can include but is not limited to nickel gold; the material of the second floating gate 63 can include but is not limited to nickel gold.

[0077] In one embodiment, the bidirectional diode structure further includes:

[0078] a substrate 1; an epitaxial layer 2 on the surface of the substrate 1; a barrier layer 4 on the surface of the epitaxial layer 2 away from the substrate 1; the first gate structure 5, the second gate structure 6, the anode 9, the cathode 10 and the capacitor are all on the surface of the barrier layer 4 away from the epitaxial layer 2.

[0079] Specifically, the epitaxial layer 2 and the barrier layer 4 can both include III-nitride layers, for example, the epitaxial layer 2 can include but is not limited to: AlN (aluminum nitride), GaN (gallium nitride) or InN (indium nitride); the barrier layer 4 can include but is not limited to: AlGaN (aluminum gallium nitride) or InGaN (indium gallium nitride); in this embodiment, the epitaxial layer 2 is preferably a GaN layer; the barrier layer 4 is preferably an AlGaN layer.

[0080] Specifically, still referring to Figure 1, the two-dimensional electron gas channel 3 is generated at the interface of the epitaxial layer 2 and the barrier layer 4. 2DEG (Two-Dimensional Electron Gas): When two III-nitride semiconductor materials with different lattice constants form a heterojunction, a large stress will occur due to lattice mismatch, which will in turn cause the generation of piezoelectric polarization effect. The strong polarization electric field will change the band structure of the III-nitride semiconductor heterojunction (such as AlGaN / GaN heterojunction), and will cause a high concentration of electrons to be bound in the quantum well on the GaN side of the heterojunction interface, and these bound electrons are called two-dimensional electron gas.

[0081] In combination Figure 1 and in reference to Figure 2 During a forward transient ESD event, a high dv / dt (voltage change rate) can induce a capacitive coupling current from the anode 9 to the cathode 10, which will carry a certain amount of Qtran (positive transition charge) to the first floating gate 53 and the second floating gate 63, and the positive transition charge will be stored in the first floating gate 53 and the second floating gate 63, which can pull down the energy band in the region of the first floating gate 53 and the second floating gate 63, and force the electrons to gather under the first floating gate 53 and the second floating gate 63, when the gate potential generated by the positive transition charge exceeds the threshold voltage of the 2DEG channel, the 2DEG channel under the first gate structure 5 and the second gate structure 6 will be turned on, then a large current can pass through the 2DEG channel under the first gate structure 5 and the second gate structure 6, which can effectively release the accumulated static charge caused by the ESD event, effectively avoid the damage of the ESD event to the first gate structure 5 and the second gate structure 6 in the semiconductor device structure, thereby enhancing the ESD robustness of the bidirectional diode structure.

[0082] In one of the embodiments, the bidirectional diode structure further comprises:

[0083] The floating electrode 11 is located on the surface of the barrier layer 4 away from the epitaxial layer 2, and is located between the first gate structure 5 and the second gate structure 6, and has a spacing with the first gate structure 5 and the second gate structure 6.

[0084] In one of the embodiments, the bidirectional diode structure further comprises: the first passivation layer 7 is located on the surface of the barrier layer 4 away from the epitaxial layer 2, is located between the anode 9 and the cathode 10, and is located at the periphery of the first gate structure 5, the periphery of the second gate structure 6 and the periphery of the floating electrode 11; the second passivation layer 8 is located on the surface of the first passivation layer 7 away from the barrier layer 4.

[0085] Specifically, the first passivation layer 7, the second passivation layer 8, the first capacitor dielectric layer 122 and the second capacitor dielectric layer 132 can each include SiN xThe thickness of the first passivation layer 7 and the second passivation layer 8 can each include 50nm-120nm; in the embodiment, the first capacitor dielectric layer 122 and the second capacitor dielectric layer 132 are each preferably SiN x The thickness of the first passivation layer 7 and the second passivation layer 8 can each include 50nm-120nm; in the embodiment, the first capacitor dielectric layer 122 and the second capacitor dielectric layer 132 are each preferably SiN 2 (120μm×120μm), which is less than 0.1% of the total area of a conventional large-current p-GaN HEMT, and can effectively help to integrate the required pF-level capacitor into a bidirectional diode structure, which is one of the significant progress of the present application.

[0086] Based on the same inventive concept, the present application also provides a method for manufacturing a bidirectional diode structure, the method comprising the steps of forming a first gate structure 5, a second gate structure 6, an anode 9, a cathode 10, a first capacitor 12 and a second capacitor 13; the second gate structure 6 is located on one side of the first gate structure 5 and has a spacing with the first gate structure 5; the anode 9 is located on the side of the first gate structure 5 away from the second gate structure 6 and has a spacing with the first gate structure 5; the cathode 10 is located on the side of the second gate structure 6 away from the first gate structure 5 and has a spacing with the second gate structure 6; the first plate 121 of the first capacitor 12 is connected with the anode 9, and the second plate 123 of the first capacitor 12 is connected with the first gate structure 5; the first plate 131 of the second capacitor 13 is connected with the cathode 10, and the second plate 133 of the second capacitor 13 is connected with the second gate structure 6.

[0087] Specifically, the material of the anode 9 can include but is not limited to titanium-aluminum-nickel-gold; the material of the cathode 10 can include but is not limited to titanium-aluminum-nickel-gold; the material of the first plate 121 of the first capacitor 12 and the material of the second plate 123 of the first capacitor 12 can each include but is not limited to nickel-gold; the material of the first plate 131 of the second capacitor 13 and the material of the second plate 133 of the second capacitor 13 can each include but is not limited to nickel-gold.

[0088] In one embodiment, before forming the first gate structure 5, the second gate structure 6, the anode 9, the cathode 10, the first capacitor 12 and the second capacitor 13, the method further comprises:

[0089] providing a substrate 1;

[0090] forming an epitaxial layer 2 on the surface of the substrate 1;

[0091] forming a barrier layer 4 on the surface of the epitaxial layer 2 away from the substrate 1.

[0092] That is, Figure 3 and Figure 5 As shown, the method for fabricating the diode structure of the present invention may further include the following steps:

[0093] S301: Provides substrate 1;

[0094] S302: An epitaxial layer 2 is formed on the surface of substrate 1;

[0095] S303: A barrier layer 4 is formed on the surface of the epitaxial layer 2 away from the substrate 1;

[0096] S304: A first gate structure 5, a second gate structure 6, an anode 9, a cathode 10, a first capacitor 12, and a second capacitor 13 are formed; the second gate structure 6 is located on one side of the first gate structure 5 and has a gap with the first gate structure 5; the anode 9 is located on the side of the first gate structure 5 away from the second gate structure 6 and has a gap with the first gate structure 5; the cathode 10 is located on the side of the second gate structure 6 away from the first gate structure 5 and has a gap with the second gate structure 6; the first electrode 121 of the first capacitor 12 is connected to the anode 9, and the second electrode 123 of the first capacitor 12 is connected to the first gate structure 5; the first electrode 131 of the second capacitor 13 is connected to the cathode 10, and the second electrode 133 of the second capacitor 13 is connected to the second gate structure 6.

[0097] Specifically, both the epitaxial layer 2 and the barrier layer 4 may include group III nitride layers. For example, the epitaxial layer 2 may include, but is not limited to, AlN (aluminum nitride), GaN (gallium nitride), or InN (indium nitride); the barrier layer 4 may include, but is not limited to, AlGaN (aluminum gallium nitride) or InGaN (indium gallium nitride). In this embodiment, the epitaxial layer 2 is preferably a GaN layer; the barrier layer 4 is preferably an AlGaN layer.

[0098] In one embodiment, the first gate structure 5 includes a first gate 51, a first gate contact layer 52, and a first floating gate 53; the second gate structure 6 includes a second gate 61, a second gate contact layer 62, and a second floating gate 63; as shown Figure 4 As shown, the structure forming the first gate structure 5, the second gate structure 6, the anode 9, the cathode 10, the first capacitor 12, and the second capacitor 13 includes:

[0099] S401: A first gate 51 and a second gate 61 are formed on the surface of the barrier layer 4 away from the epitaxial layer 2, as follows: Figure 5 and Figure 6 As shown;

[0100] S402: A first passivation layer 7 is formed on the surface of the barrier layer 4 away from the epitaxial layer 2. The first passivation layer 7 is located around the first gate 51 and the second gate 61. Figure 8 As shown;

[0101] S403: forming an anode 9 and a cathode 10 on the surface of the barrier layer 4 away from the epitaxial layer 2; the anode 9 is located on one side of the first passivation layer 7, and the cathode 10 is located on one side of the first passivation layer 7, as shown in Figure 9 ;

[0102] S404: forming a first gate contact layer 52 on the surface of the barrier layer 4 away from the first gate 51; forming a second gate contact layer 62 on the surface of the barrier layer 4 away from the second gate 61; forming a first plate 121 of the first capacitor 12 and a first plate 131 of the second capacitor 13 on the surface of the barrier layer 4 away from the epitaxial layer 2; the first plate 121 of the first capacitor 12 is connected with the anode 9, and the first plate 131 of the second capacitor 13 is connected with the cathode 10, as shown in Figure 10 ;

[0103] S405: forming a dielectric material layer 152, which covers the first passivation layer 7, the anode 9, the cathode 10, the first gate contact layer 52, the second gate contact layer 62, the first plate 121 of the first capacitor 12, and the first plate 131 of the second capacitor 13, as shown in Figure 11 ;

[0104] S406: etching the dielectric material layer 152 to form a second passivation layer 8 on the surface of the first passivation layer 7 away from the barrier layer 4, and to form a first capacitor dielectric layer 122 on the surface of the first plate 121 of the first capacitor 12 away from the barrier layer 4, and to form a second capacitor dielectric layer 132 on the surface of the first plate 131 of the second capacitor 13 away from the barrier layer 4, as shown in Figure 12 ;

[0105] S407: forming a first floating gate 53 on the surface of the first gate contact layer 52 away from the first gate 51, forming a second floating gate 63 on the surface of the second gate contact layer 62 away from the second gate 61, forming a second plate 123 of the first capacitor 12 on the surface of the first capacitor dielectric layer 122 away from the first plate 121 of the first capacitor 12, and forming a second plate 133 of the second capacitor 13 on the surface of the second capacitor dielectric layer 132 away from the first plate 131 of the second capacitor 13; the second plate 123 of the first capacitor 12 is connected with the first floating gate 53, and the second plate 133 of the second capacitor 13 is connected with the second floating gate 63, as shown in Figure 13 ; finally, the bidirectional diode structure of the present application is formed, and the bidirectional diode structure still refers to Figure 1 .

[0106] Specifically, forming the first gate 51 and the second gate 61 on the surface of the barrier layer 4 away from the epitaxial layer 2 comprises:

[0107] A gate material layer 14 is formed on the barrier layer 4, the gate material layer 14 including a p-GaN layer, such as... Figure 5 As shown;

[0108] Etching the gate material layer 14 to form the first gate 51 and the second gate 61, as follows: Figure 6 As shown.

[0109] Specifically, S402 may include:

[0110] A dielectric material layer 151 is deposited on the barrier layer 4, such as Figure 7 As shown;

[0111] Etching the dielectric material layer 151 to form the first passivation layer 7, such as Figure 8 As shown.

[0112] In one embodiment, while forming an anode 9 and a cathode 10 on the surface of the barrier layer 4 away from the epitaxial layer 2, a first floating electrode layer 111 is also formed on the surface of the barrier layer 4 away from the epitaxial layer 2, such as... Figure 9 As shown, the first floating electrode layer 111 is located within the first passivation layer 7 and between the first gate 51 and the second gate 61, with a gap between it and both the first gate 51 and the second gate 61; Figure 13 As shown, while forming the first floating gate 53, the second floating gate 63, the second electrode plate 123 of the first capacitor 12 and the second electrode plate 133 of the second capacitor 13, a second floating electrode layer 112 is also formed on the surface of the first floating electrode layer 111 away from the barrier layer 4. The first floating electrode layer 111 and the second floating electrode layer 112 together constitute the floating electrode 11.

[0113] Specifically, the material of the first gate 51 may include p-GaN (p-type gallium nitride); the material of the first gate contact layer 52 may include, but is not limited to, nickel gold; the material of the first floating gate 53 may include, but is not limited to, nickel gold; the material of the second gate 61 may include p-GaN (p-type gallium nitride); the material of the second gate contact layer 62 may include, but is not limited to, nickel gold; and the material of the second floating gate 63 may include, but is not limited to, nickel gold.

[0114] Specifically, both dielectric material layer 152151 and dielectric material layer 152152 may include SiN. x Correspondingly, the first passivation layer 7, the second passivation layer 8, the first capacitor dielectric layer 122, and the second capacitor dielectric layer 132 can all include SiN. x The thickness of both the first passivation layer 7 and the second passivation layer 8 can range from 50 nm to 120 nm. In this embodiment, both the first capacitor dielectric layer 122 and the second capacitor dielectric layer 132 are preferably SiN. xThe layer is preferably 100 nm thick. In this case, to obtain a 10 pF first capacitor 12 and a second capacitor 13, the effective area required for the first electrode 121 of the first capacitor 12, the second electrode 123 of the first capacitor 12, the first electrode 131 of the second capacitor 13, and the second electrode 133 of the second capacitor 13 is 0.0144 mm². 2 (120μm×120μm), which is less than 0.1% of the total area of ​​a traditional high-current p-GaN HEMT, can effectively help integrate the required pF-level capacitor into the bidirectional diode structure during the fabrication process, thus making significant progress in the fabrication method of bidirectional diode structures.

[0115] The bidirectional diode structure of the present invention includes: a first gate structure 5; a second gate structure 6 located on one side of the first gate structure 5 and having a gap with the first gate structure 5; an anode 9 located on the side of the first gate structure 5 away from the second gate structure 6 and having a gap with the first gate structure 5; a cathode 10 located on the side of the second gate structure 6 away from the first gate structure 5 and having a gap with the second gate structure 6; a first capacitor 12, the first plate 121 of the first capacitor 12 being connected to the anode 9, and the second plate 123 of the first capacitor 12 being connected to the first gate structure 5; a second capacitor 13, the first plate 131 of the second capacitor 13 being connected to the cathode 10, and the second plate 133 of the second capacitor 13 being connected to the second gate structure 6. The anode 9 and the first gate structure 5 are connected through the first capacitor 12, and the cathode 10 and the second gate structure 6 are connected through the second capacitor 13. The structure can be adjusted... The capacitance value of the capacitor is reduced to below 10V for ESD. During a positive transient ESD event, the high dv / dt (voltage change rate) can induce capacitive coupling current. This capacitive coupling current carries a certain amount of positive transition charge to the first gate structure 5 and the second gate structure 6. This positive transition charge is stored in the first gate structure 5 and the second gate structure 6, which can pull down the energy bands in the first gate structure 5 and the second gate structure 6 and force electrons to accumulate under the first gate structure 5 and the second gate structure 6. When the gate potential generated by the positive transition charge reaches a certain value, a large current can pass through the first gate structure 5 and the second gate structure 6, effectively releasing the accumulated electrostatic charge caused by the ESD event. This can prevent the ESD event from damaging the first gate structure 5 and the second gate structure 6, thereby enhancing the ESD robustness of the first gate structure 5 and the second gate structure 6.

[0116] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0117] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A bidirectional diode structure, characterized by The bidirectional diode structure comprises: a first gate structure; a second gate structure located on one side of the first gate structure and having a spacing with the first gate structure; an anode located on one side of the first gate structure away from the second gate structure and having a spacing with the first gate structure; a cathode located on one side of the second gate structure away from the first gate structure and having a spacing with the second gate structure; a first capacitor, a first plate of the first capacitor being connected with the anode, and a second plate of the first capacitor being connected with the first gate structure; a second capacitor, a first plate of the second capacitor being connected with the cathode, and a second plate of the second capacitor being connected with the second gate structure; The bidirectional diode structure further comprises: a substrate; an epitaxial layer located on a surface of the substrate; a barrier layer located on a surface of the epitaxial layer away from the substrate; the first gate structure, the second gate structure, the anode, the cathode and the capacitors are all located on a surface of the barrier layer away from the epitaxial layer; The bidirectional diode structure further comprises: a floating electrode, the floating electrode being located on a surface of the barrier layer away from the epitaxial layer, and being located between the first gate structure and the second gate structure and having a spacing with both the first gate structure and the second gate structure.

2. The bidirectional diode structure of claim 1, wherein The first gate structure comprises: a first gate; a first gate contact layer located on a surface of the first gate; a first floating gate located on a surface of the first gate contact layer away from the first gate and connected with the second plate.

3. The bidirectional diode structure of claim 1, wherein, The second gate structure comprises: a second gate; a second gate contact layer located on a surface of the first gate; a second floating gate located on a surface of the second gate contact layer away from the second gate and connected with the second plate of the second capacitor.

4. The bidirectional diode structure of claim 1, wherein, The bidirectional diode structure further comprises: a first passivation layer located on a surface of the barrier layer away from the epitaxial layer, located between the anode and the cathode, and located in the periphery of the first gate structure, the periphery of the second gate structure and the periphery of the floating electrode; a second passivation layer located on a surface of the first passivation layer away from the barrier layer.

5. A method of fabricating a bidirectional diode structure, characterized by, The preparation method of the bidirectional diode structure comprises: forming a first gate structure, a second gate structure, an anode, a cathode, a first capacitor and a second capacitor; the second gate structure is located on one side of the first gate structure and has a spacing with the first gate structure; the anode is located on one side of the first gate structure away from the second gate structure and has a spacing with the first gate structure; the cathode is located on one side of the second gate structure away from the first gate structure and has a spacing with the second gate structure; a first plate of the first capacitor is connected with the anode, and a second plate of the first capacitor is connected with the first gate structure; a first plate of the second capacitor is connected with the cathode, and a second plate of the second capacitor is connected with the second gate structure; Before the forming of the first gate structure, the second gate structure, the anode, the cathode, the first capacitor and the second capacitor, the method further comprises: providing a substrate; forming an epitaxial layer on a surface of the substrate; forming a barrier layer on a surface of the epitaxial layer away from the substrate; the first gate structure comprises a first gate, a first gate contact layer and a first floating gate; the second gate structure comprises a second gate, a second gate contact layer and a second floating gate; the forming of the first gate structure, the second gate structure, the anode, the cathode, the first capacitor and the second capacitor comprises: forming the first gate and the second gate on a surface of the barrier layer away from the epitaxial layer; forming a first passivation layer on a surface of the barrier layer away from the epitaxial layer, the first passivation layer being located at the periphery of the first gate and the periphery of the second gate; forming the anode and the cathode on a surface of the barrier layer away from the epitaxial layer; the anode is located at one side of the first passivation layer, and the cathode is located at one side of the first passivation layer; forming the first gate contact layer on a surface of the first gate away from the barrier layer; forming the second gate contact layer on a surface of the second gate away from the barrier layer; forming a first plate of the first capacitor and a first plate of the second capacitor on a surface of the barrier layer away from the epitaxial layer, the first plate of the first capacitor being connected to the anode, and the first plate of the second capacitor being connected to the cathode; forming a dielectric material layer covering the first passivation layer, the anode, the cathode, the first gate contact layer, the second gate contact layer, the first plate of the first capacitor and the first plate of the second capacitor; etching the dielectric material layer to form a second passivation layer on a surface of the first passivation layer away from the barrier layer, and to form a first capacitor dielectric layer on a surface of the first plate of the first capacitor away from the barrier layer and a second capacitor dielectric layer on a surface of the first plate of the second capacitor away from the barrier layer; forming the first floating gate on a surface of the first gate contact layer away from the first gate, forming the second floating gate on a surface of the second gate contact layer away from the second gate, forming a second plate of the first capacitor on a surface of the first capacitor dielectric layer away from the first plate of the first capacitor, and forming a second plate of the second capacitor on a surface of the second capacitor dielectric layer away from the first plate of the second capacitor, the second plate of the first capacitor being connected to the first floating gate, and the second plate of the second capacitor being connected to the second floating gate.

6. The method of claim 5, wherein the method further comprises: the forming of the anode and the cathode on a surface of the barrier layer away from the epitaxial layer also forms a first floating electrode layer on a surface of the barrier layer away from the epitaxial layer, the first floating electrode layer being located in the first passivation layer and between the first gate and the second gate, and having a spacing with the first gate and the second gate; the forming of the first floating gate, the second floating gate, the second plate of the first capacitor and the second plate of the second capacitor also forms a second floating electrode layer on a surface of the first floating electrode layer away from the barrier layer, the first floating electrode layer and the second floating electrode layer together constituting a floating electrode.

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