A multi-environment batch chip testing method

Abstract

The present disclosure relates to a method for batch testing of chips in multiple environments. The method includes step 1 of performing a first test on a batch of chips based on a first test environment, and obtaining binning information of the batch of chips according to the results of the first test; step 2 of binning the batch of chips according to the binning information, and dividing the batch of chips into the first bin of chips to the Nth bin of chips; step 3 of selecting any one of the N bins of chips, performing a second test on the chips in this bin based on a second test environment, and obtaining the trimming target of the chips in this bin according to the results of the second test, until the trimming target of each chip in the batch of chips is obtained. Based on the method in the present disclosure, trimming targets of different bins can be provided for the chips, and mass production of high-precision chips can be achieved.

Description

Technical Field

[0001] The present invention relates to a chip testing method, and more particularly, to a batch chip testing method in multiple environments. Background Art

[0002] Currently, during the development process of integrated circuit chips, in order to ensure the yield of high-precision chip manufacturing, it is necessary to test the chips multiple times based on different environments before the chips are manufactured and shipped, and calculate the test results of the chips in different environments to obtain the final test results, so as to check whether the performance of the chips meets the requirements of high precision.

[0003] For example, during the production process of temperature sensor chips, it is necessary to detect that the chips output different voltages or currents corresponding to the ambient temperature at different ambient temperatures. In order to ensure that the measurement accuracy of the manufactured temperature sensor chips meets the requirements, it is necessary to achieve a linear relationship between the output voltage and the ambient temperature: V = kT + V0. Wherein, V is the output voltage of the chip, T is the ambient temperature, V0 is the output voltage of the chip when the test temperature is 0°C, and k is the slope of the linear relationship between the output voltage and the ambient temperature, usually a constant coefficient. When testing the chip, if the accuracy of k is to be achieved, it is necessary to test in two different temperature environments. At the first temperature T1, the test result is V1. Then the chip is tested in the second test temperature environment T2, and the test result is V2. Finally, the test value of k is k = (V2 - V1) / (T2 - T1).

[0004] However, using this testing method, it is necessary to first perform the first temperature test on each chip, then perform the second temperature test, and then repeat this process for each subsequent chip. Therefore, during testing, the testing machine needs to continuously heat up and cool down. This method not only places high requirements on the testing machine, but also requires a long time due to continuous heating and cooling. During mass production testing, this testing method has a long testing time, low efficiency, and large errors.

[0005] Therefore, there is an urgent need for a testing method that can perform multi-environment testing on batch chips during mass production testing. Summary of the Invention

[0006] In order to solve the deficiencies in the prior art, the purpose of the present invention is to provide a batch chip testing method in multiple environments, which can classify batch chips during a single test and provide different trimming references for the chips according to the classification information during the second test.

[0007] The present invention adopts the following technical solution. A method for batch chip testing in multiple environments, comprising: Step 1, performing a first test on a batch of chips based on a first test environment, and obtaining grading information of the batch of chips according to the results of the first test; Step 2, grading the batch of chips according to the grading information, and dividing the batch of chips into the first-grade chips to the N-grade chips; Step 3, selecting any one of the N-grade chips, performing a second test on the chips of this grade based on a second test environment, and obtaining trimming targets for the chips of this grade according to the results of the second test, until trimming targets for each chip in the batch of chips are obtained.

[0008] Preferably, Step 1 further includes: Step 1.1, pre-determining the grading range of the batch of chips according to one or more standard grading values; Step 1.2, comparing the results of the first test with one or more standard grading values; Step 1.3, determining the grading information of each chip in the batch of chips according to the comparison results.

[0009] Preferably, Step 1 further includes: The grading information of each chip is the average value of the maximum standard grading value and the minimum standard grading value of the grade where the chip is located.

[0010] Preferably, Step 3 further includes: Step 3.1, obtaining the trimming target for each chip according to the grading information and the expected attribute value of each chip in this grade of chips; Step 3.2, comparing the results of the second test and the trimming target to obtain the trimming value of each chip in this grade of chips.

[0011] Preferably, the first test environment is the first test temperature T1, the result of the first test is the output voltage V1 of the chip at the first test temperature T1; the grading information of the batch of chips is the average value of the maximum standard grading value and the minimum standard grading value of the grade where the chip is located obtained according to the output voltage V1 of the chip at the first test temperature T1; the second test environment is the second test temperature T2, and the result of the second test is the output voltage V2 of the chip at the second test temperature T2.

[0012] Preferably, the trimming target for each chip is k*(T2 - T1)+(a n +a n+1 ) / 2; where n is the grade where the chip is located, k is the expected attribute value corresponding to the grade where the chip is located, a n is the minimum standard grading value of the grade where the chip is located, and a n+1 is the maximum standard grading value of the grade where the chip is located.

[0013] Preferably, the output voltage range of qualified chips in the fourth gear is determined according to the standard gear values a1, a2, a3, a4, and a5; among them, the output voltage range of the first-gear chips is (a1, a2], the output voltage range of the second-gear chips is (a2, a3], the output voltage range of the third-gear chips is (a3, a4], and the output voltage range of the fourth-gear chips is (a4, a5]; among them, the grading information of the first-gear chips is (a1 +

[0014] (a2) / 2, the grading information of the second-gear chips is (a2 + a3) / 2, the grading information of the third-gear chips is (a3 + a4) / 2, and the grading information of the fourth-gear chips is (a4 + a5) / 2.

[0015] The beneficial effect of the present invention is that, compared with the prior art, in the present invention, a multi-environment batch chip testing method grades batch chips during a single test, and provides different trimming references for the chips according to the grading information during the second test. And the chips are trimmed according to the trimming target, so as to provide high-precision factory chips in batches.

[0016] 1. The present invention can grade batch chips according to the results of a single test, so that when generating a trimming target during the second test, the trimming target can vary according to the different gears, thereby improving the yield.

[0017] 2. The present invention can determine the trimming target generated during the second test based on the preliminary test performance of the chips during the test process, so it can ensure the effectiveness of two tests for the same chip, thereby realizing the testing and trimming of batch chips. Description of the Drawings

[0018] Figure 1 It is the method flow chart of a multi-environment batch chip testing method in the present invention;

[0019] Figure 2 It is the method flow chart of step 1 in a multi-environment batch chip testing method in the present invention;

[0020] Figure 3 It is the method flow chart of step 3 in a multi-environment batch chip testing method in the present invention. Detailed Embodiment

[0021] The following further describes the present application with reference to the drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention and cannot be used to limit the protection scope of the present application.

[0022] Figure 1 It is the method flow chart of a multi-environment batch chip testing method in the present invention. As Figure 1As shown, a multi - environment batch chip testing method includes Step 1 to Step 3.

[0023] Step 1: Conduct a first - time test on the batch of chips based on the first test environment, and obtain the grading information of the batch of chips according to the first - time test results.

[0024] On the same testing machine platform, multiple chips produced in batch can be tested simultaneously. The temperature of the testing machine platform can be adjusted to the first test temperature. When it is determined that the temperature is constant, the testing of the batch of chips can be started.

[0025] Preferably, Step 1 further includes Step 11 to Step 13. Figure 2 This is the flowchart of the method of Step 1 in a multi - environment batch chip testing method of the present invention. As Figure 2 shown, Step 11: Predetermine the grading range of the batch of chips according to one or more standard grading values. Step 12: Compare the first - time test results with one or more standard grading values. Step 13: Determine the grading information of each chip in the batch of chips according to the comparison results.

[0026] Preferably, the grading information of each chip is the average value of the maximum standard grading value and the minimum standard grading value of the grade where the chip is located.

[0027] In an embodiment of the present disclosure, the chips used for batch testing are temperature sensor chips. The first test environment and the second test environment are the first test temperature T1 and the second test temperature T2 respectively. And the first - time test result and the second - time test result are the output voltage V1 and the output voltage V2 of the chip at the first test temperature T1 and the second test temperature T2 respectively.

[0028] Preferably, the grading information of the batch of chips can be the average value of the maximum standard grading value and the minimum standard grading value of the grade where the chip is located obtained according to the output voltage V1 of the chip at the first test temperature T1.

[0029] In an embodiment, qualified chips with 4 grades can be set. When the chip is at the first environmental temperature T1, if its output voltage is less than a1 or greater than a5, it will be confirmed as unqualified. When the output voltage of the chip is between a1 and a5, it will be considered a qualified chip.

[0030] Preferably, the output voltage range of qualified chips in the fourth gear can be determined according to the standard gear values a1, a2, a3, a4, and a5. The specific grading of qualified chips is as follows: The output voltage range of the first-grade chips is (a1, a2], the output voltage range of the second-grade chips is (a2, a3], the output voltage range of the third-grade chips is (a3, a4], and the output voltage range of the fourth-grade chips is (a4, a5]. Among them, the grading information of the first-grade chips is (a1 + a2) / 2, the grading information of the second-grade chips is (a2 + a3) / 2, the grading information of the third-grade chips is (a3 + a4) / 2, and the grading information of the fourth-grade chips is (a4 + a5) / 2.

[0031] Step 2: Grade the batch of chips according to the grading information, and divide the batch of chips into first-grade chips to N-grade chips.

[0032] According to the grading information in Step 1, the operation of actually grading the chips can be carried out. For example, use the manipulator on the test bench to control the movement positions of chips in different grades and conduct a second test. Of course, other implementation methods in the prior art are feasible.

[0033] Step 3: Select any one of the N-grade chips, conduct a secondary test on the chips in this grade based on the second test environment, and obtain the trimming target of the chips in this grade according to the secondary test results until the trimming target of each chip in the batch of chips is obtained.

[0034] Preferably, Step 3 further includes Step 31 to Step 32. Figure 3 This is the method flow chart of Step 3 in a multi-environment batch chip testing method of the present invention. As Figure 3 shown, in Step 31, according to the grading information and expected attribute value of each chip in this grade, obtain the trimming target of each chip. Step 32: Compare the secondary test results with the trimming target and obtain the trimming value of each chip in this grade.

[0035] According to each grading information, it is possible to know the grade where the current chip is located. According to the grading information of the chip and the expected attribute value k, the trimming target of the chip can be calculated.

[0036] Preferably, the trimming target of each chip is k*(T2 - T1)+(a n +a n+1 ) / 2; where n is the grade where the chip is located, k is the expected attribute value corresponding to the grade where the chip is located, a n is the minimum standard gear value of the grade where the chip is located, and a n+1 is the maximum standard gear value of the grade where the chip is located. It can be seen that chips in the same grade have the same trimming target.

[0037] After determining the trimming target of the chip, the trimming value can be obtained based on the difference between the results of the second test and the trimming target, and then the chip can be trimmed. Generally, the chip used for trimming has a programming function in the integrated circuit. After the second test is completed, the corresponding module in the current chip can be programmed according to the trimming value, so as to achieve fine-tuning of the packaged chip.

[0038] In the present invention, a chip with a secondary programming function can also be selected, that is, the grading information of the chip obtained during the first test is also programmed in the trimming position of the chip in the form of a trimming value. Therefore, during the second test, the grading information recorded in the trimming position can be called to calculate the trimming target, so that batch trimming of the packaged chip can be achieved without tracking the chips outside the batch of chips.

[0039] The beneficial effect of the present invention is that, compared with the prior art, in the present invention, a method for batch testing of multi-environment chips grades the batch of chips during the first test, and provides different trimming references for the chips according to the grading information during the second test. And the chips are trimmed according to the trimming target, so as to batch provide high-precision chips for factory shipment.

[0040] 1. The present invention can grade a batch of chips according to the results of the first test, so that when generating the trimming target during the second test, the trimming target can vary according to the chip grades, thereby improving the yield.

[0041] 2. The present invention can determine the trimming target generated during the second test based on the preliminary test performance of the chip during the test process, so as to ensure the effectiveness of the two tests for the same chip, and thus achieve the testing and trimming of the batch of chips.

[0042] The applicant of the present invention has made a detailed description and illustration of the embodiments of the present invention in combination with the accompanying drawings of the specification. However, those skilled in the art should understand that the above embodiments are only the preferred implementation schemes of the present invention, and the detailed description is only to help readers better understand the spirit of the present invention, rather than a limitation on the protection scope of the present invention. On the contrary, any improvement or modification made based on the spirit of the present invention should fall within the protection scope of the present invention.

Claims

1. A batch chip testing method for multiple environments, characterized in that, It includes the following steps: Step 1: Conduct a first test on a batch of chips based on a first test environment, and obtain the grading information of the batch of chips according to the results of the first test; Step 2: Grade the batch of chips according to the grading information, and divide the batch of chips into the first-grade chips to the N-grade chips; Step 3: Select any one of the N-grade chips, conduct a second test on the chips of this grade based on a second test environment, and obtain the trimming target of the chips of this grade according to the results of the second test until the trimming target of each chip in the batch of chips is obtained; Step 3 further includes: Step 3.1: Obtain the trimming target of each chip according to the grading information and the expected attribute value of each chip in this grade of chips; Step 3.2: Compare the results of the second test with the trimming target to obtain the trimming value of each chip in this grade of chips; The first test environment is the first test temperature T1, and the result of the first test is the output voltage V1 of the chip at the first test temperature T1; The grading information of the batch of chips is the average value of the maximum standard grading value and the minimum standard grading value of the grading where the chip is located obtained according to the output voltage V1 of the chip at the first test temperature T1; The second test environment is the second test temperature T2, and the result of the second test is the output voltage V2 of the chip at the second test temperature T2; The trimming target of each chip is k*(T2 - T1)+(a n +a n+1 ) / 2; Among them, n is the gear where the chip is located, k is the expected attribute value corresponding to the gear where the chip is located, and a n is the minimum standard gear value of the gear where the chip is located, and a n+1 is the maximum standard gear value of the gear where the chip is located.

2. The method for batch chip testing in multiple environments according to claim 1, wherein Step 1 further includes: Step 1.1: Predetermine the grading range of the batch of chips according to one or more standard grading values; Step 1.2: Compare the result of the first test with the one or more standard grading values; Step 1.3: Determine the grading information of each chip in the batch of chips according to the comparison result.

3. The method for batch chip testing in multiple environments according to claim 2, wherein Step 1 further includes: The grading information of each chip is the average value of the maximum standard grading value and the minimum standard grading value of the grading where the chip is located.

4. A method for batch chip testing in multiple environments according to claim 1, characterized in that, Determine the output voltage range of the qualified chips in 4 grades according to the standard grading values a1, a2, a3, a4, a5; Among them, the range where the output voltage of the first-grade chips is located is (a1, a2], the range where the output voltage of the second-grade chips is located is (a2, a3], the range where the output voltage of the third-grade chips is located is (a3, a4], and the range where the output voltage of the fourth-grade chips is located is (a4, a5]; Among them, the grading information of the first-grade chips is (a1 + a2) / 2, the grading information of the second-grade chips is (a2 + a3) / 2, the grading information of the third-grade chips is (a3 + a4) / 2, and the grading information of the fourth-grade chips is (a4 + a5) / 2.

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