A new clamping structure for clamping Vgs of PMOS

Abstract

The present application discloses a novel clamping structure for clamping the Vgs of a PMOS, the clamping structure comprising a coupling module and a pull-up module; one end of the coupling module is connected to the power supply Vin, and the other end is connected to one end of the pull-up module, the other end of the pull-up module is connected to the G end of the PMOS to be clamped, the S end of the PMOS to be clamped is connected to the power supply Vin, and the D end generates Vreg; when the power supply Vin rises rapidly, the coupling module turns on the pull-up module, and pulls up the G end of the PMOS to be clamped, clamping its Vgs, thereby stabilizing the Vreg generated by the PMOS to be clamped, and reducing the impact on the next stage. The present invention uses a capacitor and a MOS tube as a clamping structure, and ensures the clamping function through the instantaneous conduction ability of the MOS tube. The larger the width-to-length ratio of the MOS tube, the stronger the instantaneous ability, so that the Vgs of the PMOS to be clamped is stable, stable and easy to implement.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuits or chips, and relates to a novel clamping structure for clamping a voltage Vgs of a PMOS gate relative to a source. Background Art

[0002] A voltage regulator Vreg is generated by PMOS inside the high-voltage chip, and Vreg can be used as the power supply for the low-voltage working module. When Vin rises rapidly, Vreg needs to be kept stable to ensure the working state of the subsequent circuits. Even in the case of ESD (electrostatic discharge), Vreg should not increase too much to avoid damage to the subsequent MOS tubes.

[0003] The solution generally adopted in the past is: add a diode to the MOS tube connected to Vin at the G end of the PMOS (field effect transistor) that generates Vreg, and clamp it with a parasitic diode. Generally, two parasitic diodes are connected in series to ensure that the Vgs of the PMOS will not change too much due to power supply fluctuations. In this way, the current generated by the PMOS can be stable and the output Vreg is also stable.

[0004] However, when using parasitic diodes for clamping, the size of the MOS tube needs to be considered. If the size of the MOS tube is too small, the clamping effect is poor and it does not play a significant role in the subsequent circuits; if the size of the MOS tube is too large, it is prone to leakage in some cases, which will cause mismatch in the circuit structure. Summary of the invention

[0005] In order to solve the deficiencies in the prior art, the present application provides a novel clamping structure for clamping the Vgs of a PMOS.

[0006] In order to achieve the above object, the present invention adopts the following technical solution:

[0007] A novel clamping structure for clamping the Vgs of a PMOS, the clamping structure comprising a coupling module and a pull-up module;

[0008] One end of the coupling module is connected to the power supply Vin, and the other end is connected to one end of the pull-up module. The other end of the pull-up module is connected to the G end of the PMOS to be clamped. The S end of the PMOS to be clamped is connected to the power supply Vin, and the D end generates Vreg;

[0009] When the power supply Vin rises rapidly, the coupling module turns on the pull-up module, pulls up the G end of the PMOS to be clamped, clamps its Vgs, and thus stabilizes the Vreg generated by the PMOS to be clamped, reducing the impact on the next stage.

[0010] The present invention further includes the following preferred embodiments:

[0011] Preferably, the coupling module and the pull-up module are capacitors and MOS tubes respectively;

[0012] One end of the capacitor is connected to the power supply Vin, and the other end of the capacitor is connected to the S end of the MOS tube;

[0013] The D terminal and the G terminal of the MOS tube are both connected to the G terminal of the PMOS to be clamped.

[0014] Preferably, the ratio of the width to the length of the conductive channel of the MOS tube is proportional to its on-state drain current ID;

[0015] When the power supply Vin suddenly becomes high, the faster the speed, the lower the capacitor impedance, the stronger the conduction effect, and the ratio of the width to the length of the MOS tube conductive channel is proportional to its on-state drain current ID, so that the G end of the PMOS to be clamped follows the change of Vin, clamps the Vgs of the PMOS to be clamped, stabilizes the current flowing through the PMOS to be clamped, and thus stabilizes the Vreg generated by the PMOS to be clamped.

[0016] Preferably, the clamping structure further comprises a closed-loop voltage stabilization module, which is used to stabilize Vreg generated by the PMOS to be clamped according to the reference voltage Vref.

[0017] Preferably, the closed-loop voltage stabilization module comprises an operational amplifier, a first resistor and a second resistor;

[0018] The output end of the operational amplifier is connected to the G end of the PMOS to be clamped, the non-inverting input end is connected to the reference voltage Vref, and the inverting input end is connected to one end of the first resistor and one end of the second resistor;

[0019] The other end of the first resistor is connected to the D end of the PMOS to be clamped;

[0020] The other end of the second resistor is grounded;

[0021] The first resistor and the second resistor determine the ratio of the feedback signal of the inverting input terminal of the input operational amplifier, and determine the current of the branch and the size of Vreg.

[0022] Preferably, in the closed-loop voltage stabilization module, a diode-connected MOS tube is used to replace the first resistor and the second resistor respectively to determine the ratio of the feedback signal of the inverting input terminal of the input operational amplifier and determine the current of the branch and the size of Vreg.

[0023] Preferably, in the closed-loop voltage stabilization module, diodes are used to replace the first resistor and the second resistor respectively to determine the ratio of the feedback signal of the inverting input terminal of the input operational amplifier, and to determine the current of the branch and the size of Vreg.

[0024] Beneficial effects achieved by this application:

[0025] 1. Use capacitors and MOS tubes as clamping structures. The instantaneous conduction capability of the MOS tube ensures the clamping function. The larger the width-to-length ratio of the MOS tube, the stronger the instantaneous capability, so that the Vgs of the PMOS to be clamped is stable. Under normal conditions, the capacitor is considered to be open circuit.

[0026] 2. The structure of the present invention has no effect on the circuit. When Vin has ripples, mutations or ESD, the faster the power supply changes, the lower the capacitor impedance, and the stronger the conduction effect. The ratio of the conductive channel width to the length of the MOS tube connected to the capacitor is proportional to its on-state drain current ID, and the instantaneous conduction capability is very strong, which can make the G end of the PMOS to be clamped follow the change of Vin, that is, clamp its Vgs and make Vreg stable. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a working principle diagram of a novel clamping structure for clamping Vgs of PMOS according to the present invention;

[0028] Figure 2 The present invention is a working timing diagram of a novel clamping structure for clamping Vgs of a PMOS. DETAILED DESCRIPTION

[0029] The present application is further described below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and cannot be used to limit the protection scope of the present application.

[0030] A novel clamping structure for clamping the Vgs of a PMOS according to the present invention comprises a coupling module and a pull-up module;

[0031] The coupling module and the pull-up module are connected in series, wherein one end of the coupling module is connected to the power supply Vin, and the other end is connected to one end of the pull-up module, the other end of the pull-up module is connected to the G end of the PMOS to be clamped, the S end of the PMOS to be clamped is connected to the power supply Vin, and the D end generates Vreg;

[0032] When the power supply Vin rises rapidly, the coupling module turns on the pull-up module, pulls up the G end of the PMOS to be clamped, clamps the Vgs of the PMOS to be clamped, and thus stabilizes the Vreg generated by the PMOS to be clamped, reducing the impact of the next stage.

[0033] In the embodiment, the coupling module and the pull-up module are capacitors and MOS tubes respectively;

[0034] One end of the capacitor is connected to the power supply Vin, and the other end of the capacitor is connected to the S end of the MOS tube;

[0035] The D terminal and the G terminal of the MOS tube are both connected to the G terminal of the PMOS to be clamped.

[0036] The capacitor is used for coupling the rapid rise of the power supply Vin;

[0037] The MOS tube is used to form a pull-up path with the capacitor when the power supply Vin rises rapidly;

[0038] When the power supply Vin rises rapidly, the S end of the clamping MOS tube becomes higher due to the capacitive coupling effect, the MOS tube is turned on, and the G end of the PMOS is pulled up to ensure that the Vgs of the PMOS does not change too much, thereby reducing the impact of the next stage.

[0039] like Figure 1 As shown, in the specific implementation, capacitor C and PMOS1 are used as the clamping structure, PMOS2 is the output stage that generates Vreg, and the clamping function is ensured by the instantaneous conduction capability of PMOS1. The larger the width-to-length ratio of the MOS tube, the stronger the instantaneous capability, so that the Vgs of PMOS2 is stable. In the normal state, the capacitor C is considered to be open circuit;

[0040] When Vin has ripples, mutations or ESD, that is, when the power supply Vin suddenly becomes high, the faster the speed, the lower the impedance of the capacitor C, the stronger the conduction effect, and the ratio of the width and length of the conductive channel of PMOS1 is proportional to its on-state drain current ID, so that the G end of PMOS2 follows the change of Vin, clamps the Vgs of PMOS2, stabilizes the current flowing through PMOS2, and thus stabilizes the Vreg generated by PMOS2.

[0041] The size of PMOS1 cannot be too small, otherwise the clamping effect will not be obvious. The size of PMOS1 cannot be too large. If it is too large, the parasitic capacitance of the S end of PMOS1 to the ground will be larger, resulting in the G point not following Vin too quickly, which has a counterproductive effect. This problem can be solved by increasing C or changing the ring potential of PMOS1.

[0042] The size of PMOS1 and the size of capacitor C are related to the actual circuit. The clamping structure can be strong or weak, depending on the actual effect. The ring potential is mainly affected by parasitics. When the size of PMOS1 is large, that is, the area is large, and the parasitic capacitance to the ground is large, the current of the clamping structure does not flow through PMOS1 but through the parasitic capacitance path to the ground. At this time, PMOS1 is large in size but does not play the role it should play. The smaller the size of PMOS1, the smaller the influence of the ring potential. These three parameters cannot be quantified and should be determined according to the actual project.

[0043] like Figure 1 As shown, the clamping structure can also be designed to add a closed-loop voltage stabilization module for clamping Vreg generated by the PMOS to be clamped according to the reference voltage Vref.

[0044] The closed-loop voltage stabilization module includes an operational amplifier, a first resistor R1 and a second resistor R2;

[0045] The output end of the operational amplifier is connected to the G end of the PMOS to be clamped, the non-inverting input end is connected to the reference voltage Vref, and the inverting input end is connected to one end of the first resistor R1 and one end of the second resistor R2;

[0046] The other end of the first resistor R1 is connected to the D end of the PMOS to be clamped;

[0047] The other end of the second resistor R2 is grounded;

[0048] The first resistor R1 and the second resistor R2 are used to determine the ratio of the feedback signal of the inverting input terminal of the input operational amplifier, and determine the current of the branch and the size of Vreg.

[0049] Thus, the overall circuit constitutes an LDO structure, that is, a closed-loop voltage stabilization structure, Vref is the reference voltage, the potential between R1 and R2 is the negative feedback end of the operational amplifier, PMOS2 is the second-stage single-stage amplifier, Vreg is the output of the LDO, Vreg = Vref * (R1 + R2) / R2, and supplies power to the low-voltage module behind. Because it is a closed-loop structure, it is hoped that the output Vreg can be stable or cannot suddenly rise too high to avoid damaging the MOS driven by Vreg behind. Therefore, the simple and effective clamping structure of the present invention is needed, and the capacitor C therein can also be reused with the compensation capacitor of the circuit to save area. The present invention is mainly aimed at the PMOS in the loop, Figure 1 For the preferred implementation of the circuit, the structure and embodiment of the large loop are as follows: Figure 1 It's OK to be different. Figure 1 R1 and R2 in the figure can be replaced by MOS tubes connected in diode form, that is, MOS tubes connected with drain (D) and gate (G), or by diodes, but it is not as good as Figure 1 The effect is good.

[0050] like Figure 2 As shown in FIG. 1 , it is a working timing diagram of the present invention. The amplitude of Vin change is 3V / 1u, which is relatively rare under normal circumstances. When Vin changes, the clamping structure takes effect. The voltage change of the G terminal of PMOS2 and the change of Vreg are shown in FIG. Figure 2 As shown, VG changes quickly to catch up with Vin, and the change of Vreg is relatively small, with an amplitude of only 10mV / 3us, which has little impact on the following.

[0051] If Vin suddenly changes to a higher level or even hits ESD, in order to prevent Vreg from being raised too high and causing damage to the low-voltage tube driven later, the clamping structure plays a big role in this case. The faster Vin changes, the lower the capacitor impedance and the stronger the conduction effect. The ratio of the conductive channel width to length of the capacitor-connected MOS is proportional to its on-state drain current ID, and the instantaneous conduction capability is very strong, which can make the G-terminal voltage VG of PMOS2 follow the changes of Vin and clamp the Vgs of PMOS2, so that the current flowing through PMOS2 will not change too much, and Vreg will not change too high. This method is simpler and more effective.

[0052] The applicant of the present invention has made a detailed explanation and description of the implementation examples of the present invention in conjunction with the drawings in the specification. However, those skilled in the art should understand that the above implementation examples are only preferred implementation schemes of the present invention, and the detailed description is only to help readers better understand the spirit of the present invention, but not to limit the scope of protection of the present invention. On the contrary, any improvements or modifications based on the inventive spirit of the present invention should fall within the scope of protection of the present invention.

Claims

1. A novel clamping structure for clamping the Vgs of a PMOS, characterized in that: The clamping structure includes a coupling module and a pull-up module; The coupling module and the pull-up module are respectively a capacitor and a MOS tube; One end of the capacitor is connected to the power supply Vin, the other end of the capacitor is connected to the S end of the MOS tube, the D end and the G end of the MOS tube are both connected to the G end of the PMOS to be clamped, the S end of the PMOS to be clamped is connected to the power supply Vin, and the D end generates Vreg; The ratio of the width to the length of the conductive channel of the MOS tube is proportional to its on-state drain current ID; When the power supply Vin suddenly becomes high, the faster the speed, the lower the impedance of the capacitor, the stronger the conduction effect, and the ratio of the width and length of the conductive channel of the MOS tube is proportional to its on-state drain current ID, so that the G end of the PMOS to be clamped follows the change of Vin, clamps the Vgs of the PMOS to be clamped, stabilizes the current flowing through the PMOS to be clamped, and thus stabilizes the Vreg generated by the PMOS to be clamped; When the power supply Vin rises rapidly, the coupling module turns on the pull-up module, pulls up the G end of the PMOS to be clamped, clamps its Vgs, and thus stabilizes the Vreg generated by the PMOS to be clamped, reducing the impact on the next stage; The clamping structure further includes a closed-loop voltage stabilization module, which is used to stabilize Vreg generated by the PMOS to be clamped according to a reference voltage Vref.

2. The novel clamping structure according to claim 1 is characterized in that: The closed-loop voltage stabilization module includes an operational amplifier, a first resistor and a second resistor; The output end of the operational amplifier is connected to the G end of the PMOS to be clamped, the non-inverting input end is connected to the reference voltage Vref, and the inverting input end is connected to one end of the first resistor and one end of the second resistor; The other end of the first resistor is connected to the D end of the PMOS to be clamped; The other end of the second resistor is grounded; The first resistor and the second resistor determine the ratio of the feedback signal of the inverting input terminal of the input operational amplifier, and determine the current of the branch and the size of Vreg.

3. The novel clamping structure according to claim 2 is characterized in that: In the closed-loop voltage stabilization module, a diode-connected MOS tube is used to replace the first resistor and the second resistor respectively to determine the ratio of the feedback signal of the inverting input terminal of the input operational amplifier and to determine the current of the branch and the size of Vreg.

4. The novel clamping structure according to claim 2 is characterized in that: In the closed-loop voltage stabilization module, diodes are used to replace the first resistor and the second resistor respectively to determine the ratio of the feedback signal of the inverting input terminal of the input operational amplifier, and to determine the current of the branch and the size of Vreg.

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