Memory module and method of operation thereof

Abstract

A memory module and an operating method thereof are disclosed. The memory module includes a plurality of dynamic random access memories (DRAMs), a controller configured to control operations of the DRAMs, and an active device configured to, in response to detecting an error occurring in at least one of the plurality of DRAMs, generate an interrupt and store error information corresponding to the error.

Description

Technical Field

[0001] The inventive concept generally relates to a memory module and a method of operating the same. More specifically, the inventive concept relates to a memory module including non-volatile memory and a method of operating the same. Background Technology

[0002] Different semiconductor memory devices use different semiconductor components to store data. Semiconductor memory devices can be broadly classified into non-volatile memory devices or volatile memory devices. Non-volatile memory devices retain stored data even without power. Exemplary non-volatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change random access RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM). In contrast, when power is interrupted, data stored in volatile memory loses its integrity. Exemplary volatile memory devices include static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM).

[0003] Volatile memory devices are particularly well-suited for applications that support high-speed, random data access (such as data access applications typically associated with the main memory in a computing system, such as a personal computer, server, or workstation). However, non-volatile memory devices are particularly well-suited for applications that support large (or, capacity) data storage (such as auxiliary storage devices in a computing system). Summary of the Invention

[0004] Embodiments of the inventive concept provide a memory module capable of storing error information associated with errors occurring in an electronic system related to the operation of a volatile memory device.

[0005] Embodiments of the inventive concept provide a method for operating a memory module capable of storing error information associated with errors occurring in an electronic system concerning the operation of a volatile memory device.

[0006] In one aspect, embodiments of the inventive concept provide a memory module comprising: a plurality of dynamic random access memories (DRAMs); a controller configured to control the operation of the DRAMs; and an active means configured to: generate an interrupt and store error information corresponding to the error in response to detecting an error occurring in at least one of the plurality of DRAMs.

[0007] In another aspect, embodiments of the inventive concept provide an electronic device comprising: a memory module including volatile memory and an active device; and a central processing unit (CPU) connected to the memory module via a system bus. The active device is configured to: generate an interrupt and store error information corresponding to the error in response to detecting an error occurring in the volatile memory.

[0008] In another aspect, embodiments of the inventive concept provide a method of operating a memory module, the memory module including a plurality of volatile memories, a controller, and an active device. The method includes: periodically reading an error log stored in a register using the active device; transmitting an interrupt to the register when an error concerning the operation of the memory module is detected; receiving the error log from the register in response to the interrupt, and storing at least a portion of the error log as error information; and storing the error information in non-volatile memory.

[0009] However, the inventive concept is not limited to the aspects set forth herein. The above and other aspects of the inventive concept will become clearer to those skilled in the art by referring to the specific embodiments of the inventive concept given below. Attached Figure Description

[0010] The above and other aspects and features of the inventive concept will become clearer when considered in conjunction with the following detailed embodiments, in which:

[0011] Figure 1 This is a block diagram illustrating an electronic device according to an embodiment of the inventive concept;

[0012] Figure 2 This further demonstrates Figure 1 Block diagram of memory module 100;

[0013] Figure 3 and Figure 4 As shown in various embodiments Figure 2 The corresponding block diagram of the active device 50;

[0014] Figure 5 and Figure 6 As shown in various embodiments Figure 3 and Figure 4 The corresponding block diagram of the active memory;

[0015] Figure 7 This is a list of exemplary error messages that can be used in some embodiments of the inventive concept;

[0016] Figure 8 and Figure 9 Operation is illustrated in various embodiments. Figure 2A flowchart of a method for using an active device; and

[0017] Figure 10 The operation is shown in one example. Figure 1 A flowchart of a method for making an electronic device. Detailed Implementation

[0018] In the following description, specific embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0019] Figure 1 is a block diagram illustrating an electronic device according to an embodiment of the inventive concept. Figure 2 It is shown as Figure 1 A block diagram of an example memory module 100 for a main memory device (or memory) 100.

[0020] Reference Figure 1 Electronic device 1 may be implemented in various ways, such as a personal computer (PC), a laptop computer, an ultra-mobile PC (UMPC), a workstation, a server, a netbook, a personal digital assistant (PDA), a portable computer, a network tablet computer, a wireless telephone, a mobile phone, a smartphone, a digital camera, a digital recorder, a digital audio player, a digital video recorder, a digital image player, a digital video recorder, a digital video player, a home network, or another device or system capable of “transmitting” (e.g., sending and / or receiving) information in a hardwired and / or wireless environment.

[0021] In some embodiments, electronic device 1 may include main memory device 100, central processing unit (CPU) 200, and system bus 300. Various components, such as input device 400, display device 500, network device 600, and storage device 700, may be connected to CPU 200 and / or main memory device 100 via system bus 300, either internally to electronic device 1 or externally to electronic device 1 in the case of attachable / removable components or communication with external components.

[0022] Main memory device 100 can be used to store data processed or transferred by CPU 200. In some embodiments, main memory device 100 can be used as working memory for CPU 200. Those skilled in the art will understand that main memory device 100 can be configured differently. For example, main memory device 100 may include one or more of DRAM, double data rate synchronous DRAM (or DDR SDRAM), low power DDR SDRAM (or LPDDR SDRAM), graphics DDR (or GDDR), Rambus DRAM (or RDRAM), and any other type of volatile memory device requiring refresh operations.

[0023] Here, the main memory device 100 may be manufactured wholly or partially as a semiconductor memory device. The processing speed of the main memory device 100 may be much faster than that of the storage device 700, which may include one or more non-volatile memory devices.

[0024] CPU 200 may include various arbitrary processors and may include means capable of encoding and / or decoding instructions associated with electronic device 1, means capable of performing arithmetic and / or logical operations, and means capable of processing data transmitted by electronic device 1 in different ways. For example, in some embodiments, CPU 200 may include a programming counter, an arithmetic logic unit (ALU) 210, a control unit 220, various registers 230, an instruction decoder, timing circuitry, and a bus interface 240, etc.

[0025] Here, ALU 210 can perform various arithmetic and / or logical operations in response to instructions associated with electronic device 1.

[0026] In some embodiments, register 230 may store a log for tracking the operational status of electronic device 1. That is, control unit 220 may write data recording the operational status of electronic device 1 into register 230 in real time during operation of electronic device 1. For example, register 230 may record various time information (such as the time when a specific operation is performed). Therefore, register 230 may be used as a polling register for the basic input / output system (BIOS), a register for recording system events related to the baseboard management controller (BMC), etc.

[0027] CPU 200 may include a single processing core or multiple processing cores. For example, CPU 200 may include multiple dual-core, quad-core, or hexa-core processors. CPU 200 may also include one or more cache memories (e.g., external cache memory and / or internal cache memory).

[0028] Input device 400 includes one or more devices capable of providing input data, addresses, and / or commands to electronic device 1. For example, input device 400 may include a keyboard, keypad, buttons, touch panel, touch screen, touchpad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, piezoelectric element, temperature sensor, biometric sensor, etc.

[0029] Display device 500 includes one or more means capable of providing output data to one or more circuits. For example, display device 500 may include a liquid crystal display (LCD), an organic light-emitting diode (OLED) display, an active-matrix OLED (AMOLED) display, an LED, a speaker, a motor, etc.

[0030] Network device 600 may include a communication device capable of transmitting information to a device external to electronic device 1. In this respect, network device 600 may be a hardwired communication device and / or a wireless communication device.

[0031] Storage device 700 may be located external to CPU 200 and main memory 100. In some embodiments, storage device 700 may serve as supplemental memory in relation to the limited storage capacity of main memory device 100. Storage device 700 may be non-volatile memory that preserves specific data when electronic device 1 is turned off. As shown above, the data processing speed of storage device 700 is much slower than that of main memory device 100; however, large amounts of data can be stored in storage device 700 in a semi-permanent state.

[0032] The storage device 700 may be implemented in various ways (e.g., as a hard disk drive (HDD)). However, in some embodiments, the storage device 700 may be a semiconductor memory device (such as a solid-state drive (SSD)).

[0033] Bus 300 may include, or be compatible with, various communication protocols and / or communication links. Therefore, in some embodiments, bus 300 may be a system management bus (SMBus), an internal integrated circuit (I2C) bus, an intelligent platform management interface (IPMI) compatible bus, Modbus, etc.

[0034] The main memory device 100 can be implemented as follows: Figure 2 The memory module is shown in the figure. When implemented as a memory module, the main memory device 100 can be easily attached to / removed from the electronic device 1 (or installed inside / removed from the electronic device 1). In this regard, one or more memory modules installed inside the electronic device 1 can be configured as the main memory device 100.

[0035] Figure 2The memory module (or main memory device, memory) 100 shown includes multiple volatile memories (e.g., DRAM 11, 12, 13, 14, 15, 16, 17, 18, hereinafter collectively referred to as "DRAM 11 to 18"), a controller 20, memory input / output (I / O) pins 30, and an active device 50. The memory module 100 can be used to write data, store data, retrieve (or read) data, and / or erase data under the control of the CPU 200. For example, in Figure 2 In the illustrated example, CPU 200 may use one or more communication protocols or technical standards established by JEDEC (see www.jedec.com) such as JESD79F for DDR SDRAM and JESD209 for LPDDR to control data exchange with memory module 100. In this regard, CPU 200 may appropriately transmit commands, addresses, control signals, and / or data to memory module 100 during various data access operations (e.g., read and write operations).

[0036] about Figure 2 The hypothetical (and in the written description below) DRAMs 11 to 18 may be one or more of DRAM, SRAM, and / or SDRAM. Each of the DRAMs 11 to 18 may transmit data (DQ) via a first channel CH1 under the control of the controller 20. In some embodiments, the memory module 100 may also include various buffers (not shown) typically used during the transmission of data (DQ) and / or various other signals. Here, the data (DQ) may be transmitted synchronously with a data strobe signal (DQS).

[0037] In some embodiments, the controller 20 may communicate with the DRAMs 11 to 18 using at least one communication protocol or technology standard typically associated with, for example, dual in-line memory modules (DIMMs), register-based DIMMs (RDIMMs), low-load DIMMs (LRDIMMs), and registerless DIMMs (UDIMMs). Therefore, the controller 20 of the memory module 100 may receive commands, addresses, control signals (including one or more clock signals), and data via the first channel CH1 during data access operations of the main memory device 100, and may provide (or distribute) one or more of these signals to the DRAMs 11 to 18.

[0038] Active device 50 can monitor the operating status of each of DRAMs 11 to 18 and can also store error information associated with detected errors occurring in at least one of DRAMs 11 to 18. Here, the detected "error" can be a data content error in data written to or read from at least one of DRAMs 11 to 18, a data transmission error in data transmitted to or from at least one of DRAMs 11 to 18, etc. In some embodiments, active device 50 can monitor the operating status of DRAMs 11 to 18 in real time. In other embodiments, active device 50 can monitor the operating status of DRAMs 11 to 18 periodically or upon receiving an external command. When an error is detected (regardless of how it is monitored), active device 50 can record the occurrence of the error by recording the corresponding time (or time period) in an "error log" stored in, for example, register 230. Therefore, active device 50 can report the occurrence of an error by reading the error log stored in register 230. In some of these embodiments, the error log in register 230 may include multiple logs associated with each of the individual DRAMs 11 to 18.

[0039] In some embodiments, upon detecting an error (e.g., by reading an error log), the active device 50 may send a corresponding control signal (e.g., an "interrupt" hereinafter) to the CPU 200. In response to the error interrupt, if the error was not recorded, the CPU 200 may cause the error to be recorded in the error log (e.g., update the error log in register 230). Thereafter, the active device 50 may receive an updated copy of the error log from the CPU 200 as an "error message".

[0040] In this regard, it should be noted that the active device 50 can detect abnormal operation of the memory module 100 and transmit an interrupt via the second channel CH2 to receive error information from the CPU 200.

[0041] In some embodiments, the second channel CH2 may be a separate channel from the first channel CH1. For example, the first channel CH1 connects the system bus 300 to the controller 20, and the second channel CH2 connects the system bus 300 to the active device 50. Therefore, if the electronic device 1 (or CPU 200) should be shut down due to an error and the first channel CH1 becomes unavailable, the active device 50 can still use the second channel CH2 to perform operations related to the error.

[0042] Figure 3 and Figure 4 Further examples are shown in different ways. Figure 2 The corresponding block diagram of the active device 50. Figure 5 and Figure 6 Further examples are shown in different ways. Figure 3 The corresponding block diagram of the active memory 52.

[0043] Reference Figure 3 The active device 50 may include an active controller 51 and an active memory 52. ​​Here, the active controller 51 may periodically monitor the operating status of DRAMs 11 to 18 and output an interrupt to the CPU 200 when an error occurs in at least one of DRAMs 11 to 18. In some embodiments, the active controller 51 may periodically read an error log stored in register 230 to monitor the operating status of DRAMs 11 to 18. Optionally, the active controller 51 may periodically check (or poll) each of DRAMs 11 to 18 to determine the operating status of DRAMs 11 to 18 and / or receive operating status information from controller 20.

[0044] As a result of monitoring, when an error is detected, the active controller 51 can output an interrupt to the CPU 200. In some embodiments, the interrupt can modify the BIOS in the CPU 200 to record system analysis data based on whether the detected error is a correctable error (CE) or an uncorrectable error (UE).

[0045] In this regard, the active controller 51 can receive error log entries associated with interrupts from the CPU 200 and store the error log entries in the active memory 52. ​​For example, in the case of correctable errors (CE), the active controller 51 can receive the corresponding error information from the machine detection model-specific register (MSR) (e.g., error-reporting bank register), error correction count register, and / or retry_rd_err_log register. In the case of uncorrectable errors (UE), the active controller 51 can receive the system event log as the corresponding error information. Therefore, the active memory 52 can store one or more types of error information. Optionally or additionally, the active memory 52 can store initial information, device information, module configuration (and / or, type) information, data storage capacity information, execution environment information, operation logs, etc., associated with the memory module 100. In this regard, the active memory 52 can be non-volatile memory.

[0046] In some embodiments, the active memory 52 can distinguish and store various error messages according to the error type. For example, such as Figure 5As shown, the active memory 52 can distinguish and separately store error information associated with a correctable first error 61 and an uncorrectable second error 62. In the case of a correctable first error 61 (i.e., when the first error 61 occurs), the operation of the memory module 100 and the electronic device 1 can continue if the first error 61 can be corrected. Therefore, correctable (or, first type) error information (e.g., CE LOG 1 to CE LOG N) can be cumulatively stored in the active memory 52. ​​However, in the case of an uncorrectable second error 62 (i.e., when the second error 62 occurs), once the corresponding second error information (UE LOG) is stored in the active memory 52, the CPU 200 and / or the electronic device 1 is immediately shut down.

[0047] In some embodiments, the active memory 52 may store error information in the order in which the error information is received from the CPU 200 (e.g., the order of receipt) or in the order in which the error is detected (e.g., the order in which it occurs). For example, such as Figure 6 As shown, the active memory 52 can store error information in chronological order. That is, since correctable first errors (e.g., CE LOG 1 to CE LOG N) 71 to 79 are continuously used to perform error correction associated with DRAMs 11 to 18, the correctable first errors can be recorded in chronological order. However, uncorrectable second errors (e.g., UE LOG) 80 can be stored as error information immediately before the system is shut down.

[0048] In some embodiments, the active device 50 may include a communication Internet Protocol (IP) 53. The communication IP 53 allows an external device (not shown) to access data stored in one or more of the DRAMs 11 to 18 using the functionality of the memory module 100. For example, the communication IP may assign Internet Protocol addresses to each of the DRAMs 11 to 18, and the active device 50 may then allow the external device to directly access the DRAMs 11 to 18 using these assigned addresses. The communication IP 53 may be implemented with... Figure 3 The active controller 51 and active memory 52 are separate chips. Optionally, the communication IP 53 can be used via... Figure 4 The functions provided by the active controller 51 and active memory 52 are implemented here. Here, the communication IP 53 can be connected to an external device via an input / output (I / O) bus, which can be used to transmit error information stored in the active memory 52 to the external device.

[0049] According to embodiments of the inventive concept, a memory module (or main memory device) 100 including an active device 50 is capable of checking for errors in real time and using error information stored in the active memory 52 to analyze the type and / or cause of errors, thereby improving the overall reliability, availability, and serviceability (RAS) of the electronic device 1.

[0050] Figure 7 This is a table listing exemplary error messages that can be used in relation to embodiments of the inventive concept.

[0051] Here, as mentioned earlier, a correctable first error (CE) is an error that can be corrected using the error correction capabilities associated with memory module 100. In this regard, a correctable first error (CE) can be detected by CPU 200. In some embodiments, a correctable first error (CE) may be an error that occurs in one of DRAMs 11 to 18.

[0052] In contrast, an uncorrectable second error (UE) is an error that cannot be corrected using the error correction capabilities associated with memory module 100. Again, an uncorrectable second error (UE) can be detected by CPU 200. For example, an uncorrectable second error (UE) may include errors occurring in two or more DQs, and similar critical errors that cause the system to stop or reset. In some embodiments, an uncorrectable second error (UE) may include errors exceeding the maximum CE threshold, or errors resulting when the RAS feature does not cover the system.

[0053] Refer to the illustration Figure 7 For example, in the case of a correctable first error (CE), address information associated with the correctable first error (CE) (e.g., a fault address), time information associated with the error, and error logs associated with DRAMs 11 to 18 (e.g., operation logs or system logs) can be read from register 230 and stored as first error information. Here, in some embodiments, whenever a correctable first error (CE) occurs, the active device 50 may use a BIOS-routed System Management Interrupt (SMI) service to store the first error information. Optionally, the active device 50 may access register 230 to read the error logs (e.g., one or more system event logs) (fully or partially) and then store the error logs in active memory 52.

[0054] In the case of an uncorrectable second error (UE), the corresponding error information may include at least one of the following: header information, cyclic redundancy check (CRC) information, address information associated with the uncorrectable second error (UE) (e.g., DRAM address), system information, system type and / or configuration, time information (e.g., timestamp associated with the UE).

[0055] Figure 8 and Figure 9 The operation is shown in one example. Figure 2 The corresponding flowchart of the method for the active device 50.

[0056] Reference Figure 1 , Figure 2 and Figure 8 The memory module (or main memory device) 100 performs memory operations in response to commands, addresses, control signals, and / or data provided by the CPU 200 (S10). When an error is detected (S20 = Yes), the active device can determine whether the detected error is correctable (S30). If the error is determined to be correctable (S30 = Yes), error correction can be performed, and error information can be stored according to the correctable error (CE) mode (S40). Otherwise, if the detected error is determined not to be correctable (S30 = No), error information can be stored according to the uncorrectable error (UE) mode (S50).

[0057] Reference Figure 1 , Figure 2 and Figure 9 In some embodiments of the inventive concept, the active device 50 can monitor the operating status of DRAMs 11 to 18 by periodically reading an error log stored in register 230 (S100). If an error is detected during this monitoring step (S110 = Yes), an interrupt can be sent to register 230 (S120). Here, the type of interrupt can vary depending on whether the error is determined to be correctable or uncorrectable. For example, in some embodiments, an interrupt can be sent only if the error is considered uncorrectable.

[0058] In response to an interrupt, register 230 may transmit error information to active device 50. For example, if the error log stored in register 230 stores multiple system (or component) logs, only the system log related to the interrupt may be transmitted to active device 50. Upon receiving the error log (in whole or in part) (S130), active device 50 may store the error log as error information (S140). If the error is an uncorrectable second error (UE), the CPU 200 or electronic device 1 associated with memory module 100 will be shut down (S150). However, if the error is a correctable first error (CE), error correction may be performed or a read retry may be performed on the data stored in one or more of DRAMs 11 to 18.

[0059] Figure 10 This is shown in one example. Figure 1 A flowchart of the method for operating the electronic device 1.

[0060] Reference Figure 1 and Figure 10 The CPU 200 operates in response to commands, addresses, control signals, and / or data received from components inside the electronic device 1 or from an external source (S300). In response to the operation of the CPU 200, the memory module 100 can perform memory operations (S400). In this regard, the CPU 200 can record (or update) the operating state of the memory module 100 in real time (S310), and furthermore, the active device 50 can access the CPU 200 to monitor for errors (S500).

[0061] If a correctable error occurs during memory operation (S320 and S410), the CPU 200 instructs the controller 20 to perform error correction operations, read retry operations, etc., and the controller 20 performs such operations (S420).

[0062] The active device 50 can transmit an interrupt to the CPU 200, and the CPU 200 can receive the interrupt (S330) and transmit an error log in response to the interrupt (S340). In some embodiments, the transmitted error log may be a recently updated set of system logs. The active device 50 receives the error log (S520) and stores the contents of the error log (in whole or in part) as error information (S530). Optionally, the active device may not output an interrupt to the CPU 200, but may instead store the error log corresponding to the occurrence of an error from a periodically read log as error information (S530).

[0063] If an uncorrectable error occurs during memory operation (S320 and S410), the system will shut down (S350). However, before the system shuts down, the active device 50 immediately transmits an interrupt (S510), and upon receiving the interrupt from the active device, the CPU 200 transmits an error log corresponding to the error occurrence (S340). The active device 50 receives the error log (S520) and stores the contents of the error log (in whole or in part) as error information (S530).

[0064] Furthermore, when the active device receives an access request to the active memory 52 from an external device (S600), the active device can send the stored error information to the external device (S540).

[0065] The formation and use of the inventive concept have been described with respect to specific embodiments. However, the scope of the inventive concept is not limited to the illustrated embodiments. Those skilled in the art will understand that many variations and modifications can be made to the illustrated and described embodiments without substantially departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A memory module, comprising: Multiple dynamic random access memories (DRAMs); Controller, wherein the controller controls the operation of the DRAM; and The active device circuit, in response to detecting an error associated with at least one of the plurality of DRAMs, generates an interrupt and stores error information corresponding to the error. Error messages include error logs in response to interrupted reception. Active device circuitry includes: An active controller, wherein the active controller transmits interrupts to the central processing unit, including registers; and The non-volatile memory is configured to receive the error log stored in the register and store the error log as error information.

2. The memory module according to claim 1, wherein, The active device circuitry is also configured to periodically monitor for the occurrence of errors during the operation of the plurality of DRAMs.

3. The memory module according to claim 1, wherein, The active device circuit is also configured to distinguish and store error information based on a first error that can be corrected and a second error that cannot be corrected.

4. The memory module according to claim 1, further comprising: The first channel is configured to connect the controller of the plurality of DRAMs to the system bus; as well as The second channel is configured to connect active device circuitry to the system bus.

5. The memory module according to claim 1, wherein, The active device circuitry includes: a communication Internet Protocol circuitry for transmitting an assigned address of at least one of the plurality of DRAMs.

6. The memory module according to claim 5, wherein, The communication internet protocol circuitry is configured separately from the active controller.

7. The memory module according to any one of claims 1-6, wherein, The non-volatile memory is also configured to sequentially store error information associated with multiple correctable errors.

8. The memory module according to any one of claims 1-6, wherein, The error is uncorrectable, and once the error information is stored in non-volatile memory, the operation of the central processing unit is shut down in response to an interrupt.

9. An electronic device comprising: The memory module includes volatile memory and active device circuitry; as well as The central processing unit is connected to the memory module via the system bus. In this circuit, the active device circuit, in response to detecting an error in the volatile memory, generates an interrupt and stores the error information corresponding to the error. Error messages include error logs in response to interrupted reception. The central processing unit includes: The processor is configured to access data stored in volatile memory; and The register is configured to store the error log of the memory module.

10. The electronic device according to claim 9, wherein, Active device circuitry includes: An active controller, wherein the active controller transmits interrupts to the central processing unit; and The non-volatile memory is configured to receive error logs and store the error logs as error information.

11. The electronic device according to claim 10, wherein, If the error is correctable, the active controller receives the address information in the volatile memory associated with the error and stores the address information in the non-volatile memory as the error information.

12. The electronic device according to claim 11, wherein, If the error is uncorrectable, the active controller sends an interrupt to the central processing unit (CPU), which responds to the interrupt by reading the operation log stored in the registers and shutting down the electronic device.

13. The electronic device according to claim 12, wherein, The operation log includes at least one of the following: header information, cyclic redundancy check information, address information in the error-associated volatile memory device, system information, system type information, system configuration information, and time information.

14. The electronic device according to claim 13, wherein, The memory module also includes: The first channel is configured to connect active device circuitry to the system bus and to transmit interrupts from the active controller to the central processing unit; and The second channel is configured to connect the controller of the volatile memory to the system bus.

15. A method of operating a memory module, the memory module comprising a plurality of volatile memories, a controller, and an active device, the method comprising: Use an active device to periodically read the error log stored in the register; When an error is detected in the operation of the memory module, an interrupt is sent to the register; In response to an interrupt, receive the error log from the register and store at least a portion of the error log as error information; as well as Error information is stored in non-volatile memory.

16. The operating method according to claim 15, further comprising: The error was determined to be correctable. Receive the address information of the error-associated volatile memory among the plurality of volatile memories, the operation log of the volatile memory, and the time information associated with the error; as well as Use address information, operation logs, and time information to perform error correction.

17. The operating method according to claim 16, wherein, The active device is configured to cumulatively and sequentially store error information associated with multiple errors that are respectively determined to be correctable errors.

18. The operating method according to claim 15, further comprising: The error is determined to be uncorrectable. as well as Shut down the system, including the memory module, after storing the error information.

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