Simulation End Mechanism Based on UVM Verification Platform
By writing simulation end control logic in the scoreboard component of UVM, obtaining the target phase and waiting for the DUT to complete the excitation sequence operation, the problem of inaccurate UVM simulation end control is solved, and simulation efficiency and management convenience are improved.
Patent Information
- Application Number
- CN202210085222.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-01-25
- Publication Date
- 2025-08-05
- Estimated Expiration
- 2042-01-25
AI Technical Summary
In the prior art, UVM simulation end control is inaccurate, resulting in too long or too short simulation time, making it difficult to determine the appropriate waiting time, affecting verification work efficiency and increasing debugging difficulty, especially in pre-compiled designs provided by IP providers, it is difficult to set appropriate additional waiting time.
Write the simulation end control logic in the scoreboard component of UVM, obtain the target phase through the callback method, and create a judgment program block in the simulation end control logic, wait for the DUT to complete the excitation sequence operation and call the simulation end method to achieve precise control.
It realizes the accuracy of simulation end control and improves verification work efficiency, reduces the difficulty of problem debugging, and facilitates the management of UVM simulation operation.
Smart Images
Figure CN114444421B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of chip verification, and particularly to a simulation end mechanism based on a UVM verification platform. Background Art
[0002] In the prior art, the UVM (Universal Verification Methodology) verification methodology is usually used to verify RTL (Register Transfer Level). When the simulation runs in the phase mechanism, the user usually controls the UVM simulation process by setting an additional waiting time. Specifically, as Figure 1 shown, first, the find_by_name method of the phase mechanism is called in the end_of_elaboration_phase of the test case base class to obtain the target phase, and then the set_drain_time method in the phase_done is called to set the additional simulation end waiting time of the target phase. However, the processing delay of the internal logic of the DUT (Device under test) component is in clock cycles, and the additional end waiting time of the specified target phase in the prior art is in the simulation time of the EDA (Electronic design automation) tool. Therefore, the prior art has the defect of inaccurate simulation end control. If the set additional waiting time is too long, then it increases the meaningless simulation time, undoubtedly reducing the efficiency of the verification work. If the set additional waiting time is too short, it may lead to the situation that some additional waiting times are sufficient while some are not for different DUTs, and it is difficult to determine a unified waiting time. At this time, if a problem occurs, it will increase the difficulty of problem debugging.
[0003] Moreover, setting the additional end waiting time of the target phase through the set_drain_time of the test case base class in the prior art will be determined during the project compilation phase. However, many IP suppliers provide designs in a pre-compiled form, and it is difficult to require the other party to set the just right additional end waiting time of the target phase for this project during the pre-compilation period. Therefore, in this application scenario, the prior solution becomes no longer feasible. Summary of the Invention
[0004] According to an embodiment of the present invention, a simulation end mechanism based on a UVM verification platform is provided, including the following steps:
[0005] Write simulation end control logic in the callback method of the scoreboard component in UVM;
[0006] Call the callback method to get the target phase;
[0007] Execute the simulation end control logic for the target phase to simulate the target phase.
[0008] Furthermore, the callback method calls the target acquisition method of the UVM phase mechanism to obtain the target phase;
[0009] Furthermore, the simulation end control logic is executed for the target phase, which includes the following sub-steps:
[0010] Call the simulation start method of UVM's phase mechanism to simulate the target phase;
[0011] Create a simulation judgment program block in the simulation end control logic, the simulation judgment program block obtains the target phase, and waits for the DUT device under test in the UVM verification platform to complete the operation of the stimulus sequence in the phase mechanism;
[0012] When the DUT device under test completes the calculation of the stimulus sequence of the phase mechanism, the simulation end method of the phase mechanism of UVM is called to end the simulation run of the target phase.
[0013] Furthermore, the simulation judgment program block judges whether the DUT device under test has completed the operation of the stimulus sequence of the phase mechanism through the status of the queue in the scoreboard component.
[0014] Furthermore, in the callback method, the end waiting time is set for the subdivision phase stage that consumes simulation time in the phase mechanism of UVM.
[0015] The simulation end mechanism based on the UVM verification platform according to the embodiment of the present invention solves the defect of inaccurate simulation end control in the prior art, has the characteristics of accurate simulation end control and high verification work efficiency, reduces the difficulty of problem debugging, and facilitates the control of UVM simulation operation.
[0016] It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the technology as claimed. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 A schematic diagram of a method for setting an additional waiting time in the prior art;
[0018] Figure 2 A flowchart of a simulation end mechanism based on the UVM verification platform according to an embodiment of the present invention;
[0019] Figure 3 It is a flowchart of sub - steps of step S3 according to an embodiment of the present invention;
[0020] Figure 4 It is a schematic diagram of the simulation end mechanism based on the UVM verification platform according to an embodiment of the present invention. Specific embodiments
[0021] The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, and the present invention will be further elaborated.
[0022] First, in combination with Figures 2 to 4 Describe the simulation end mechanism based on the UVM verification platform according to an embodiment of the present invention, which is used to verify mobile phone chips and has a wide range of application scenarios.
[0023] As Figure 2 , 4 shown, the simulation end mechanism based on the UVM verification platform according to an embodiment of the present invention includes the following steps:
[0024] In S1, as Figure 2 , 4 shown, write the simulation end control logic in the callback method (phase_ready_to_end) in the scoreboard component (scoreboard) of UVM, so as to achieve the effect of controlling the end of the simulation during the simulation running stage of the project rather than the compilation stage.
[0025] In S2, as Figure 2 , 4 shown, call the callback method (phase_ready_to_end) to obtain the target phase.
[0026] Furthermore, the callback method (phase_ready_to_end) calls the target acquisition method (get_name) of the phase mechanism of UVM to obtain the target phase.
[0027] Furthermore, in the callback method, set the end waiting time for the sub - phases of the phase mechanism of UVM that consume simulation time, solving the defect that it is difficult to set the additional waiting time for the end of the target phase in the prior art.
[0028] In S3, as Figure 2 , 4 shown, execute the simulation end control logic on the target phase to control the end of the simulation of the target phase.
[0029] Furthermore, executing the simulation end control logic on the target phase includes the following sub - steps:
[0030] In S31, as Figures 3 to 4 shown, call the simulation start method (raise_objection) of the UVM phase mechanism to simulate the target phase.
[0031] In S32, as Figures 3 to 4 shown, create a simulation judgment program block (objectphasewait logic) in the simulation end control logic. This simulation judgment program block (object phasewait logic) waits for the DUT (Device Under Test) in the UVM verification platform to complete the operation of the excitation sequence in the phase mechanism.
[0032] Furthermore, the simulation judgment program block (object phasewait logic) determines whether the DUT (Device Under Test) has completed the operation of the excitation sequence in the phase mechanism by the status of the queue in the scoreboard component. Because for the scoreboard component, it can obtain the operation output results from the DUT and the reference model through the TLM communication port. Generally, the scoreboard component will first obtain the operation output results from the reference model and write them into the queue of the scoreboard, and then obtain the operation output results from the DUT (Device Under Test). Therefore, it can be determined whether to continue waiting for the simulation to end by judging whether the queue is empty.
[0033] In S33, as Figures 3 to 4 shown, when the DUT (Device Under Test) completes the operation of the excitation sequence in the phase mechanism, call the simulation end method (drop_objection) of the UVM phase mechanism to end the simulation run of the target phase.
[0034] As Figure 4As shown, the working principle of this embodiment is as follows: First, after the phase start of the phase mechanism and before the phase end, the phase_ready_to_end method in the UVM component is called, and then we complete the control logic for the end of the simulation of the target phase therein. After the recognition object enters the phase_ready_to_end method, it is first determined whether the recognition object is the target phase. If the recognition object is not the target phase, no additional delay control for the end waiting time is added to the recognition object, and it directly jumps to the phase end to end the current target phase; if the recognition object is the target phase, the simulation start method (raise_objection) of the phase mechanism is called to start the simulation of the target phase. Then it enters the parallel simulation judgment program block (object phasewait logic). At this time, the DUT (device under test) is receiving the test sequence of the target phase and requires a certain amount of time to complete the operation. At the same time, the target phase waiting logic judges whether the DUT has completed the operation. This is usually judged by receiving the interface signals of the DUT monitored by the UVM monitor component through the TLM communication port in the scoreboard component. At this time, if the waiting is completed, the simulation end method (drop_objection) of the phase mechanism is called to end the simulation operation of the target phase, and then it jumps to the phase end to end the simulation operation of the current phase stage.
[0035] As described above, referring to Figures 2 to 4 The simulation end mechanism based on the UVM verification platform according to the embodiment of the present invention is described above, which solves the defect of inaccurate simulation end control in the prior art, has the characteristics of accurate simulation end control and high verification work efficiency, reduces the difficulty of problem debugging, and is convenient for controlling the simulation operation of UVM.
[0036] It should be noted that in this specification, the term "comprising", "including" or any other variant thereof is intended to cover a non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, the element defined by the statement "comprising..." does not exclude the existence of additional identical elements in the process, method, article or device including the said element.
[0037] Although the content of the present invention has been described in detail through the above preferred embodiments, it should be recognized that the above description should not be considered as a limitation of the present invention. After those skilled in the art have read the above content, various modifications and alternatives to the present invention will be obvious. Therefore, the protection scope of the present invention should be defined by the appended claims.
Claims
1. A simulation end mechanism based on UVM verification platform, characterized in that, The following steps are included: Write the simulation end control logic in the callback method of the UVM scoreboard component; Call the callback method to obtain the target phase; Executing the simulation end control logic on the target phase to control the simulation end of the target phase; Executing the simulation end control logic on the target phase includes the following sub-steps: Call the simulation start method of the phase mechanism of the UVM to simulate the target phase; Creating a simulation judgment program block in the simulation end control logic, the simulation judgment program block obtains the target phase, and waits for the DUT device under test in the UVM verification platform to complete the operation of the stimulus sequence in the phase mechanism; After the DUT device under test completes the calculation of the stimulus sequence under the phase stage, the simulation end method of the phase mechanism of the UVM is called to end the simulation operation of the target phase.
2. the simulation end mechanism based on UVM verification platform as claimed in claim 1, is characterized in that, The callback method calls the target acquisition method of the phase mechanism of the UVM to obtain the target phase.
3. the simulation end mechanism based on UVM verification platform as claimed in claim 1, is characterized in that, The simulation judgment program block judges whether the DUT device under test has completed the operation of the stimulus sequence of the phase mechanism through the status of the queue in the scoreboard component.
4. the simulation end mechanism based on UVM verification platform as claimed in claim 1, is characterized in that, In the callback method, the subdivision phase stage consuming simulation time in the phase mechanism of the UVM is set to end the setting of the waiting time.