Memory cell arrangement and method thereof

Abstract

A memory cell arrangement is provided, the memory cell arrangement may include: one or more memory cells, each of the one or more memory cells including: a field effect transistor structure; a plurality of first control nodes; a plurality of first capacitor structures; a second control node; and a second capacitor structure including a first electrode connected to the second control node and a second electrode connected to a gate region of the field effect transistor. Each of the plurality of first capacitor structures includes a first electrode connected to a corresponding first control node of the plurality of first control nodes, a second electrode connected to the gate region of the field effect transistor structure, and a spontaneous polarization region disposed between the first electrode and the second electrode of the first capacitor structure.

Description

Technical Field

[0001] Various aspects relate to memory cell arrangements and methods thereof, such as methods for operating memory cell arrangements. Background Art

[0002] In general, various computer memory technologies have been developed in the semiconductor industry. The basic building block of a computer memory may be referred to as a memory cell. A memory cell may be an electronic circuit configured to store at least one information (e.g., in a bitwise manner). As an example, a memory cell may have at least two memory states representing, for example, a logical "1" and a logical "0". Typically, information may be retained (stored) in a memory cell until, for example, the memory state of the memory cell is modified in a controlled manner. The information stored in the memory cell may be obtained by determining in which memory state the memory cell resides. Currently, various types of memory cells may be used to store data. Typically, a large number of memory cells may be implemented as a memory cell array, wherein each memory cell or a predefined group of memory cells may be individually addressed. In this case, information may be read out by addressing the memory cell accordingly. In addition, various driver circuits have been developed in the semiconductor industry to control the operation of one or more memory cells of a memory device. The memory cells may be implemented in such a way that each individual memory cell or at least individual groups of memory cells are unambiguously addressable, for example for writing (eg programming and / or erasing) and / or reading the respective memory cell or group of memory cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] In the drawings, like reference numerals generally refer to like parts in different views. The drawings are not necessarily drawn to scale, with emphasis generally being placed on illustrating the principles of the invention. In the following description, various aspects of the invention are described with reference to the following drawings, in which:

[0004] Figure 1A , Figure 1B , Figure 2A , Figure 3A , Figure 3C and Figure 3D each schematically illustrating a memory cell arrangement according to various aspects;

[0005] Figure 1C , Figure 2B and Figure 3B each showing a perspective view of a memory cell arrangement according to various aspects;

[0006] Figure 4A schematically illustrates a memory cell according to various aspects;

[0007] Figure 4Bschematically illustrates a memory cell arrangement according to various aspects;

[0008] FIG. 4C to FIG. 4H schematically illustrates memory cell arrangements of various architectures and addressing schemes according to various aspects;

[0009] FIG. 4I to FIG. 4L each schematically illustrates an example memory cell arrangement according to various aspects;

[0010] Figure 5A and Figure 5B each schematically illustrates an example memory cell arrangement including four memory cells according to various aspects;

[0011] Figure 5C shows an example configuration of a memory cell arrangement including four memory cells according to various aspects;

[0012] Figure 5D A perspective view showing an arrangement of memory cells driven by one or more control circuits according to various aspects;

[0013] Figure 5E shows an example configuration of a memory cell arrangement including four multi-bit memory cells according to various aspects;

[0014] Fig. 5F schematically illustrates a cross section of a memory cell arrangement having a NAND architecture according to various aspects;

[0015] Fig. 6A and Figure 6B each schematically illustrating a memory cell arrangement having a NOR architecture and including a multi-bit memory cell according to various aspects;

[0016] Figure 6C and Fig.6D each schematically illustrates a memory cell arrangement having a NAND architecture and including multi-bit memory cells according to various aspects;

[0017] Fig. 6E schematically illustrates a memory cell arrangement having an AND architecture and including multi-bit memory cells according to various aspects;

[0018] 7A to 7E each schematically illustrates an example memory cell arrangement including multi-bit memory cells according to various aspects;

[0019] Figure 8 A schematic flow chart showing a method for manufacturing a memory cell arrangement according to various aspects;

[0020] Fig. 9A schematic flow chart of a method for operating a memory cell arrangement according to various aspects is shown. DETAILED DESCRIPTION

[0021] The following detailed description refers to the accompanying drawings, which show the specific details and aspects of the present invention by way of illustration. These aspects are described in sufficient detail to enable those skilled in the art to practice the present invention. Without departing from the scope of the present invention, other aspects may be utilized and structural, logical and electrical changes may be made. Various aspects are not necessarily mutually exclusive, because some aspects may be combined with one or more other aspects to form new aspects. Various aspects are described in conjunction with methods, and various aspects are described in conjunction with devices (e.g., arrangements). However, it is understood that the aspects described in conjunction with methods may be similarly applied to devices, and vice versa.

[0022] The terms "at least one" and "one or more" may be understood to include any integer greater than or equal to one, i.e., one, two, three, four, ..., etc. The term "plurality" may be understood to include any integer greater than or equal to two, i.e., two, three, four, five, ..., etc.

[0023] The phrase "at least one" with respect to a group of elements may be used herein to indicate at least one element from the group consisting of these elements. For example, the phrase "at least one of" with respect to a group of elements may be used herein to indicate the following options: one of the listed elements, a plurality of the listed elements, a plurality of individual listed elements, or a plurality of multiple listed elements.

[0024] The phrase that an element or a group of elements “comprises” another element or another group of elements may be used herein to indicate that the additional element or another group of elements may be a part of the element or the group of elements or that the element or the group of elements may be configured or formed as the additional element or another group of elements (for example, the element may be another element).

[0025] The phrase "explicitly assigned" may be used herein to refer to a one-to-one assignment (e.g., dispatch, such as correspondence) or a bijective assignment. For example, a first element being explicitly assigned to a second element may include the second element being explicitly assigned to the first element. As another example, a first set of elements being explicitly assigned to a second set of elements may include each element of the first set of elements being explicitly assigned to a corresponding element of the second set of elements, and the corresponding element of the second set of elements being explicitly assigned to the element of the first set of elements.

[0026] The term "connection" may be used herein to refer to an electrical connection with respect to a node, an integrated circuit element, etc., which may include a direct connection or an indirect connection, wherein an indirect connection may only include additional structures in the current path that do not affect the basic function of the described circuit or device. The term "conductive connection" used herein to describe an electrical connection between one or more terminals, nodes, regions, contacts, etc. may be understood as a conductive connection having, for example, ohmic properties, such as provided by a metal or a degenerate semiconductor in the absence of a pn junction in the current path. The term "conductive connection" may also be referred to as an "electrical connection".

[0027] The term "voltage" may be used herein in relation to "one or more bit line voltages", "one or more word line voltages", "one or more lever line voltages", "one or more source line voltages", "one or more control line voltages", "one or more base voltages", etc. As an example, the term "base voltage" may be used herein to refer to a reference voltage and / or reference potential of a circuit. For a circuit, the base voltage may also be referred to as a ground voltage, a ground potential, a virtual ground voltage, or zero volts (0V). The base voltage of a circuit may be defined by a power supply used to operate the electronic circuit. As another example, the term "control line voltage" may be used herein to refer to a voltage provided to, for example, a control line of a memory cell arrangement (e.g., a "word line voltage" may be provided to a "word line", a "lever line voltage" may be provided to a "word line", a "bit line voltage" may be provided to a bit line, and a "source line voltage" may be provided to a source line). The sign of a voltage difference (e.g., a voltage drop) may be defined as the potential inside the memory cell (e.g., at a first electrode portion) minus the potential at a second electrode portion of the memory cell.

[0028] Illustratively, the voltage provided to a node or terminal may take any suitable value depending on the intended operation of the circuit including the node or terminal. For example, the bit line voltage (referred to as V BL Similarly, the word line voltage (referred to as V WL or VWL), the plate line voltage (called V PL or VPL) and / or the source line voltage (referred to as V SL The voltage supplied to a node or terminal may be determined by the base voltage (referred to as VSL) applied to that node or terminal relative to the circuit. B). In addition, the voltage drop associated with two different nodes or terminals of a circuit can be defined by the corresponding voltages / potentials applied at the two nodes or terminals. As an example, the bit line voltage drop associated with a memory cell (e.g., an electrode of the memory cell) of a memory cell arrangement can be defined by the corresponding voltage / potential applied at the corresponding memory cell (e.g., an electrode of the memory cell). For example, a memory cell based on an n-type or p-type field effect transistor (FET) can have a first threshold voltage and a second threshold voltage, the first threshold voltage also being referred to as a low threshold voltage (V L-th ), the second threshold voltage is also called the high threshold voltage (V H-th ). In the case of n-type field effect transistor (n-FET) based memory cells, the high threshold voltage V H-th Can be greater than the low threshold voltage V L-th , whether in terms of voltage values ​​or absolute voltage values ​​(e.g., V L-th can be 1V and V H-th It can be 3V, just as a numerical example), or a high threshold voltage V H-th Can be greater than the low threshold voltage V L-th , only about the voltage value (for example, V L-th can be -1V and V H-th Can be 1V, or V L-th can be -2V and V H-th Can be 0V, or V L-th can be -3V and V H-th It can be -1V, just as a numerical example). In the case of a memory cell based on a p-type field effect transistor (p-FET), the high threshold voltage V H-th may be lower than the low threshold voltage V L-th (Regarding voltage value) and is higher than the low threshold voltage V L-th (About absolute voltage value) (e.g., V L-th can be -1V and V H-th It can be -3V, just as a numerical example), or a high threshold voltage V H-th Can be lower than the low threshold voltage V L-th , only about the voltage value (for example, V L-th can be 1V and V H-th Can be -1V, or V L-th can be 2V and V H-th Can be 0V, or V L-th can be 3V and V H-th It can be 1V, just as a numerical example).

[0029] According to various aspects, the threshold voltage of a field effect transistor or a field effect transistor-based memory cell may be defined as a constant current threshold voltage (referred to as V th(ci) ). In this case, the constant current threshold voltage V th(ci) Can be determined by the gate-source voltage V GS , at which the drain current (called I D ) is equal to a predefined (constant) current. The predefined (constant) current can be a reference current (called I D0 ) multiplied by the ratio of gate width (W) to gate length (L). The reference current I D0 The magnitude of V is suitable for a given technology, for example, 0.1 μA. In some aspects, the constant current threshold voltage V th(ci) It can be determined based on the following equation:

[0030] V th(ci) =V GS (at I D =I D0 ·W / L).

[0031] The threshold voltage of a field effect transistor or a memory cell based on a field effect transistor may be defined by the characteristics of the field effect transistor or the memory cell based on a field effect transistor (e.g., material, doping, etc.), and therefore it may be a (e.g., intrinsic) characteristic of the field effect transistor or the memory cell based on a field effect transistor.

[0032] In some aspects, two voltages can be compared to each other using relative terms such as "greater," "higher," "lower," "less," or "equal." It should be understood that in some aspects, the comparison can include the sign of the voltage value (positive or negative), or in other aspects, the absolute voltage value (also referred to as magnitude or amplitude, such as the magnitude or amplitude of a voltage pulse) can be considered for comparison.

[0033] According to various aspects, the memory cell may be addressed via a corresponding access device. The access device may include or may be, for example, a field effect transistor (FET), such as an n-type or p-type field effect transistor, a transmission gate (e.g., an n-type or p-type transmission gate), etc. The access device may have a threshold voltage associated therewith. The threshold voltage of the access device (e.g., a field effect transistor) may be defined by characteristics of the access device (e.g., a field effect transistor), such as material, doping, etc., and thus it may be a (e.g., intrinsic) property of the access device.

[0034] According to various aspects, a memory cell may have at least two different states associated therewith, such as having two different conductivities, which may be determined to assess in which of the at least two different states the memory cell resides. The memory cell may typically include a phase change or phase change-based memory cell, a ferroelectric or ferroelectric-based memory cell, an antiferroelectric or antiferroelectric-based memory cell, a spontaneous polarization memory cell, such as a residual polarization memory cell, a capacitor or a capacitor-based memory cell, and / or a ferroelectric capacitor or a ferroelectric capacitor-based memory cell ("FeCAP"). The memory cell may include at least a first memory state and a second memory state. In some aspects, the memory state in which the memory cell resides may affect current characteristics and / or voltage characteristics during readout of the memory cell. For example, the first memory state may be associated with a logical "1", and the second memory state may be associated with a logical "0", for example. However, the definition of the memory state and / or the definition of a logical "0" and a logical "1" may be arbitrarily selected. A FET-based memory cell (e.g., a spontaneously polarized memory cell, such as a residual polarized memory cell) may include a first memory state, such as a low threshold voltage state (referred to as an LVT state), and a second memory state, such as a high threshold voltage state (referred to as an HVT state). In some aspects, the high threshold voltage state may be associated with a current that is lower than the low threshold voltage state during readout. The low threshold voltage state may be a conductive state (e.g., associated with a logical "1") and the high threshold voltage state may be a non-conductive state or at least a state that is less conductive than the low threshold voltage (e.g., associated with a logical "0"). However, the definition of the LVT state and the HVT state and / or the definition of a logical "0" and a logical "1" may be arbitrarily selected. Illustratively, the first memory state may be associated with a first threshold voltage of the FET-based memory cell, and the second memory state may be associated with a second threshold voltage of the FET-based memory cell.

[0035] For example, a phase change memory cell may include a phase change portion. The phase change portion may be used, for example, to implement a storage function in a memory cell. The phase change portion may include a first phase state and a second phase state. For example, a phase change memory cell may change from a first phase state to a second phase state or vice versa upon application of an electrical signal, and may remain in the corresponding phase state for at least a period of time (referred to as a retention time).

[0036] According to various aspects, a spontaneously polarized memory cell (e.g., a remanent polarized memory cell) may include a spontaneously polarized portion (also referred to as a spontaneously polarizable portion, e.g., a remanent polarized portion). The spontaneously polarized portion may be used, for example, to implement a storage function in a memory cell. Thus, according to various aspects, the memory cell may be implemented as a capacitor structure, for example, as a spontaneously polarized capacitor (e.g., a remanent polarized capacitor). Typically, spontaneous polarization may exist in a material portion (e.g., a material layer) when a material may have a non-zero electric polarization P after an electric field E is applied; therefore, a specific value of the material portion may be detected. For example, the spontaneous polarization may be a ferroelectric polarization or an antiferroelectric polarization. Typically, remanent polarization (also referred to as retention or remanence) may exist in a material portion (e.g., a material layer) when a material may retain polarization when an applied electric field E is reduced to zero; therefore, a specific value of the electric polarization (P) of the material portion may be detected. Illustratively, the polarization that remains in a material when the electric field is reduced to zero may be referred to as remanent polarization or residual polarization. Therefore, the remanence of a material can be a measure of the residual polarization in the material when the external electric field is removed. Spontaneously polarized materials can be or include spontaneously polarized materials that exhibit remanence, such as ferroelectric materials, and / or can include spontaneously polarized materials that do not exhibit remanence, such as antiferroelectric materials. In general, ferroelectricity can be a concept that describes the remanent polarization of a material, similar to the concept of ferromagnetism used to describe remanent magnetization in magnetic materials. In general, antiferroelectricity can be a concept that describes the non-remanent magnetization but spontaneous polarization of a material, similar to the antiferromagnetism used to describe non-remanent magnetization but spontaneous magnetization in magnetic materials. The spontaneously polarized portion (or spontaneously polarized region) can exhibit hysteresis in (voltage-dependent) polarization. The spontaneously polarized portion can exhibit antiferroelectric properties, for example, in the absence of a voltage drop across the spontaneously polarized portion, the spontaneously polarized portion may have no remanent polarization or no substantial remanent polarization remaining. In other aspects, the spontaneously polarized portion can exhibit ferroelectric properties, for example, the spontaneously polarized portion can have a remanent polarization or a substantially remanent polarization in the absence of a voltage drop across the spontaneously polarized portion.

[0037] In some aspects, as low as 0 μC / cm in various types of applications, such as in memory technology 2 To 3μC / cm 2 A remanent polarization of 1 μC / cm2 may be considered as having no basic remanent polarization. Such low remanent polarization values ​​may exist in a layer or material due to undesirable effects, for example due to non-ideal layer formation. In some aspects, in various types of applications, for example in memory technology, a remanent polarization value greater than 3 μC / cm2 may be considered as having no basic remanent polarization. 2 The remanent polarization of can be regarded as a basic remanent polarization. Such a basic remanent polarization can allow information to be stored based on the polarization state of the spontaneously polarized part or the spontaneously polarized material.

[0038] In addition, the remanent polarization material may include spontaneous polarization, for example, with reference to the polarization ability of the material beyond the dielectric polarization. The coercive force of a material can be a measure of the strength of the reverse polarization electric field that may be required to remove the remanent polarization. According to various aspects, the coercive electric field (also referred to as the coercive field) can be or represent the electric field required to depolarize the remanent polarization layer. The remanent polarization can be evaluated by analyzing one or more hysteresis measurements (e.g., hysteresis curves), for example in a graph of polarization P versus electric field E, where the material is polarized in opposite directions. The polarization ability (dielectric polarization, spontaneous polarization, and remanent polarization) of the material can be analyzed using capacitance spectroscopy, for example, by static (CV) and / or time-resolved measurements or by polarization voltage (PV) or positive up negative down (PUND) measurements.

[0039] The polarization state of the remnant polarization portion may be switched by the capacitor structure. The polarization state of the remnant polarization portion may be read out by the capacitor structure. The polarization state of the remnant polarization portion may define, for example, a memory state of the memory cell. As an example, the polarization state of the remnant polarization portion may affect one or more electrical properties of the capacitor structure, such as a charging current during charging of the capacitor structure.

[0040] In a typical capacitor structure, the amount of charge stored therein can be used to define a memory state. For example, a first amount of charge stored in the capacitor structure can define a first memory state, and a second amount of charge stored in the capacitor structure can define a second memory state.

[0041] According to various aspects, writing to a memory cell or performing a write operation on a memory cell may include an operation or process of modifying a memory state in which the memory cell resides from a (e.g., first) memory state to another (e.g., second) memory state. According to various aspects, writing to a memory cell may include programming the memory cell (e.g., performing a programming operation of the memory cell), wherein the memory state in which the memory cell resides after programming may be referred to as a "programmed state". For example, programming a remanent polarization memory cell may modify the polarization state of the remanent polarization memory cell from a first polarization state to a second polarization state (e.g., opposite to the first polarization state). According to various aspects, writing to a memory cell may include erasing the memory cell (e.g., performing an erase operation of the memory cell), wherein the memory state in which the memory cell resides after erasing may be referred to as an "erased state". For example, erasing a remanent polarization memory cell may modify the polarization state of the remanent polarization memory cell from the second polarization state to the first polarization state. For example, the programmed state may be associated with a logical "1" and the erased state may be associated with a logical "0". However, the definition of the programming state and the erased state may be selected arbitrarily. For example, programming an n-type FET-based memory cell may modify the state in which the memory cell resides from the HVT state to the LVT state, while programming a p-type FET-based memory cell may modify the state in which the memory cell resides from the LVT state to the HVT state. According to various aspects, writing to a memory cell may include erasing the memory cell (e.g., performing an erase operation of the memory cell), wherein the memory state in which the memory cell resides after erasing may be referred to as an "erased state". For example, erasing an n-type FET-based memory cell may modify the state in which the memory cell resides from the LVT state to the HVT state, while erasing a p-type FET-based memory cell may modify the state in which the memory cell resides from the HVT state to the LVT state. For example, the programming state may be a conductive state (e.g., associated with a logical "1") and the erased state may be a non-conductive state or at least a state that is less conductive than the programming state (e.g., associated with a logical "0"). However, the definition of the programming state and the erased state may be selected arbitrarily.

[0042] The term "switching" may be used herein to describe a modification of a memory state in which a memory cell resides. For example, where a memory cell resides in a first memory state, the memory state in which the memory cell resides may be switched such that, after switching, the memory cell may reside in a second memory state that is different from the first memory state. Thus, the term "switching" may be used herein to describe a modification of a memory state in which a memory cell resides from a first memory state to a second memory state. The term "switching" may also be used herein to describe a modification of a polarization, such as a modification of a remnant polarization portion. For example, the polarization of the remnant polarization portion may be switched such that the sign of the polarization changes from positive to negative or from negative to positive, while the absolute value of the polarization may remain substantially unchanged in some aspects.

[0043] According to various aspects, a ferroelectric capacitor based memory cell (also referred to as a ferroelectric capacitor "FeCAP") may include a capacitor structure that includes a ferroelectric material as a spontaneous polarization portion, for example, as a remanent polarization portion (e.g., a ferroelectric capacitor). The term "ferroelectric" may be used herein, for example, to describe a material that exhibits a hysteresis charge-voltage relationship (QV). The ferroelectric material may be or may include a ferroelectric HfO 2 and / or ferroelectric ZrO 2 . Ferroelectric HfO 2 Any form of hafnium oxide that can exhibit ferroelectric properties may be included. Ferroelectric materials may include, for example, HfO 2 、ZrO 2 , HfO 2 and ZrO 2 solid solution (such as but not limited to a 1:1 mixture) of HfO or HfO doped or substituted with one or more of the following elements (non-exhaustive list): 2 : silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, zirconium, any rare earth element or any other suitable dopant (also referred to as a dopant) that provides or maintains ferroelectricity in hafnium oxide. According to various aspects, the ferroelectric material can be an example of a material used in a spontaneous polarization portion (e.g., in a remanent polarization portion). According to various aspects, the ferroelectric portion can be an example of a spontaneous polarization portion (e.g., a remanent polarization portion).

[0044] In the semiconductor industry, the integration of non-volatile memory technology may be useful for system-on-chip (SoC) products such as microcontrollers (MCUs). According to various aspects, the non-volatile memory may be integrated next to the processor core of a processor. As another example, one or more non-volatile memories may be used as part of a large-capacity storage device. In some aspects, the non-volatile memory technology may be based on a memory cell arrangement as described below. The memory cell arrangement may include a FeCAP memory cell. Since the ferroelectric material included in the FeCAP memory cell may have at least two stable polarization states, a ferroelectric capacitor may be used as a non-volatile memory cell. Therefore, the FeCAP memory cell stores data by a ferroelectric material between at least the first electrode and the second electrode of the capacitor structure. According to various aspects, a memory structure or memory cell based on a non-volatile field effect transistor may store data for a period of time from a few hours (e.g., more than 5 hours) to several decades (e.g., 10 years, 20 years, etc.), while a volatile memory cell may store data for a period of time from nanoseconds to a few hours (e.g., less than 5 hours).

[0045] Compared to other emerging memory technologies, a remanent polarization memory cell, such as a FeCAP-based memory cell, can be integrated in front-end-of-line (FEoL) and / or back-end-of-line (BEoL) process flows because it can be implemented as a capacitor-type memory. Therefore, the integration of the FeCAP-based memory cell can comply with standard FEoL and / or BEoL complementary metal oxide semiconductor (CMOS) process flows. Therefore, various integration schemes can be used to integrate the FeCAP-based memory cell in different process technologies.

[0046] In some aspects, a memory cell arrangement (e.g., an array including a plurality of memory cells) may be operated based on one or more write operations (e.g., programming and / or erasing operations) and / or one or more read operations. For example, during a write operation, a predefined voltage may be provided to an electrical wire (also referred to as a control line or a driver line), wherein the electrical wire may be connected to a corresponding node (e.g., a corresponding electrode) of the memory cell to allow for the desired operation. The electrical wire may be referred to as, for example, a bit line, a word line, a plate line, and / or a source line. All memory cells that are not intended to be written may see a voltage that is at least less than the programming voltage. The programming voltage may be defined by the type and / or design of the memory cell. In some aspects, the programming voltage may be in the range of 1V to about 10V. The programming voltage may be determined by one or more electrical measurements. Various timings may be used to provide the corresponding voltage, for example, to provide a desired write voltage and / or a desired read voltage.

[0047] Typically, a memory cell arrangement may include a plurality of (e.g., volatile or non-volatile) memory cells that may be accessed individually or in groups by a corresponding addressing scheme. For example, a matrix architecture may be referred to as a "NOR" or "NAND" architecture, depending on the manner in which adjacent memory cells are connected to one another, i.e., depending on the manner in which the terminals of adjacent memory cells are shared, but is not limited to these two types (another type is, for example, an "AND" architecture). For example, in a NAND architecture, memory cells may be organized in sectors (also referred to as blocks) of memory cells, wherein the memory cells are connected in series in strings (e.g., source and drain regions are shared by adjacent transistors) and are connected in series to a first control line and a second control line. For example, groups of memory cells in a NAND architecture may be connected in series to one another. In a NOR architecture, memory cells may be connected in parallel to one another. A NAND architecture may therefore be more suitable for serial access to data stored in memory cells, while a NOR architecture may be more suitable for random access to data stored in memory cells.

[0048] Various aspects relate to a memory cell arrangement including one or more memory cells. The one or more memory cells may be, for example, one or more FeCAP memory cells. In some aspects, a control circuit may be configured to perform and / or instruct one or more write operations associated with writing to one or more memory cells of the memory cell arrangement. In some aspects, a control circuit may be used to control writing to a single memory cell (illustratively, a memory cell intended to be written to) of the memory cell arrangement. According to various aspects, writing to a memory cell may include causing the memory cell to enter another of the at least two memory states of the memory cell from one of at least two memory states.

[0049] According to various aspects, a memory cell arrangement may include: one or more memory cells, each of the one or more memory cells including: an electrode column having a bottom surface and a top surface; a memory material portion surrounding a side portion of the electrode column; an electrode layer surrounding the memory material portion and the side portion of the electrode column, wherein the electrode column, the memory material portion and the electrode layer form a capacitor memory structure; and a field effect transistor structure including a gate structure, wherein the bottom surface of the electrode column faces the gate structure and is conductively connected to the gate structure, and wherein the top surface of the electrode column faces away from the gate structure.

[0050] According to various aspects, a memory cell arrangement may include: one or more memory cells, each of the one or more memory cells including: an electrode column extending from the bottom surface of the electrode column to the top surface of the electrode column; one or more memory material portions, each of the one or more memory material portions surrounds a corresponding first side portion of the electrode column; one or more first electrode layers, each of the one or more first electrode layers surrounds a corresponding memory material portion in the one or more memory material portions and a first side portion of the electrode column associated with the corresponding memory material portion; wherein the first electrode layer, the corresponding memory material portion and the electrode column form a corresponding capacitor memory structure; and a dielectric material portion, surrounding a second side portion of the electrode column that is different from each of the first side portions; a second electrode layer, surrounding the dielectric material portion and the second side portion of the electrode column, wherein the electrode column, the dielectric material portion and the second electrode layer form a capacitor lever structure; and a field effect transistor structure, including a gate structure, wherein the gate structure faces the bottom surface of the electrode column and is conductively connected to the electrode column.

[0051] According to various aspects, a memory cell arrangement may include: one or more memory cells, each of the one or more memory cells including: a field effect transistor structure; multiple control nodes; multiple capacitor structures, each of the multiple capacitor structures including a first electrode connected to a corresponding control node among the multiple control nodes, a second electrode connected to a gate region of the field effect transistor structure, and a polarizable region arranged between the first electrode and the second electrode of the capacitor structure.

[0052] According to various aspects, a memory cell arrangement may include: one or more memory cells, each of the one or more memory cells including: a field effect transistor structure; a plurality of first control nodes; a plurality of first capacitor structures, each of the plurality of first capacitor structures including a first electrode connected to a corresponding first control node among the plurality of first control nodes, a second electrode connected to a gate region of the field effect transistor structure, and a spontaneous polarization region disposed between the first electrode and the second electrode of the first capacitor structure; a second control node; and a second capacitor structure including a first electrode connected to the second control node and a second electrode connected to the gate region of the field effect transistor.

[0053] Figure 1AA cross section of an example memory cell 1 according to various aspects is schematically shown. The memory cell arrangement 10 may include one or more memory cells, such as memory cell 1. The memory cell 1 may include an electrode column 12. The electrode column 12 may have a bottom surface 14 and a top surface 16. The bottom surface 14 may be substantially parallel to the xy plane. The top surface 16 may be substantially parallel to the xy plane. The xy plane may be defined by a lateral plane (referred to as a lateral dimension in some aspects) of a substrate on which, above, and / or in which the memory cell arrangement 10 may be disposed. The xy plane may be defined by a lateral plane of a chip on which, above, and / or in which the memory cell arrangement 10 may be disposed. For example, the xy plane may be defined by an in-plane direction of the substrate and / or chip. The electrode column 12 may be substantially perpendicular to the xy plane, for example, extending in the z direction. The z direction may correspond to an out-of-plane direction (referred to as a vertical dimension in some aspects) of the substrate and / or chip. For example, the height of the substrate and / or chip may be given by a z coordinate. The bottom surface 14 may have one of the following geometric shapes: a circle, a square, a triangle, a parallelogram, a trapezoid, an ellipse, a polygon, an n-gon, etc. The top surface 16 may have a bottom surface geometry of one of the following geometric shapes: a circle, a square, a triangle, a parallelogram, a trapezoid, an ellipse, a polygon, an n-gon, etc. The bottom surface 14 and the top surface 16 may define any geometric body or a frustum of a geometric body having a bottom surface and a top surface as an electrode column. For example, the bottom surface 14 and the top surface 16 may both be circular and the electrode column 12 may be a frustum of a cylinder or a cone (referred to as a circular frustum in some aspects). For example, the bottom surface 14 and the top surface 16 may both be square, and the electrode column 12 may be a cube, a cuboid, a rectangular prism, a pyramid (referred to as a square frustum in some aspects), etc. According to various aspects, the electrode column 12 may have a cylindrical shape, such as a circular cylindrical shape or a prismatic shape. A cylinder may generally have a bottom surface and a top surface of the same shape and size. The shape and size are not limited. A cylinder with a circular bottom and top surface may be referred to as a circular cylinder, and is sometimes often referred to as a cylinder. A cylinder with a bottom and top surface in the shape of an n-gon (e.g., a polygon, e.g., n is greater than 2) may be referred to as a prism. The cylinder may include a truncated cylinder. According to various aspects, the electrode column 12 may have a frustum shape. The frustum may be a frustum of a pyramid or a cone. The frustum may include a truncated frustum.

[0054] According to various aspects, the bottom surface 14 and the top surface 16 may be substantially parallel to each other. The electrode column 12 may have a height defined by the distance between the bottom surface 14 and the top surface 16. For example, the height of the electrode column 12 may be the distance in the z direction. The electrode column 12 may have a side 18. The side 18 may be defined by the geometry of the electrode column 12. The side may include all sides (e.g., sides) of the electrode column except the bottom surface 14 and the top surface 16. For example, in the case where the electrode column 12 is a body of rotation (such as a cylinder), the side 18 may include one side. For example, in the case where the bottom surface 14 and the top surface 16 are formed as n-gons, the side 18 may include "n" sides. Illustratively, the body defined by the bottom surface 14, the top surface 16, and the side 18 may have a short side defined by the bottom surface and / or the top surface and a long side (e.g., the height of the side) defined by the side. The width of the electrode column 12 may be defined by the shape of the bottom surface 14 and / or the top surface 16. For example, in the case of a circular shape, the width of the electrode column 12 may be defined by the diameter of the circle. For example, in the case of an n-gon, the width of the electrode column 12 may be defined by the distance between two opposite sides or two substantially opposite sides of the n-gon. The width of the electrode column 12 may be the maximum extension of the electrode column 12 in the x-direction and / or the y-direction. The width of the electrode column 12 may be the maximum extension of the electrode column 12 perpendicular to the height direction (e.g., the z-direction). The electrode column 12 may include or may be made of Cu, Au, Ag, W, Al, Ru, Ti, TiN, Ta, TaN, Co, CoN, Nb, NbN, Pd, Pt, Ir, IrO. 2 、RuO 2 , Poly-Si, etc.

[0055] The memory cell 1 may include a memory material portion 22 (e.g., a spontaneous polarization portion, e.g., a residual polarization portion). The memory material may include a phase change material, a spontaneous polarization material, a residual polarization material, etc. In the following, in various aspects, the memory material is described as a residual polarization material by way of example. However, it should be noted that this is used as an example and any other material having at least two different states associated therewith may be used as a memory material, such as any kind of spontaneous polarization material (e.g., a ferroelectric memory material, e.g., an antiferroelectric material, etc.). The memory material portion 22 may surround a portion 20 of the side 18 (referred to as a side portion 20 in some aspects). The side portion 20 may include a corresponding portion of one or more sides of the electrode column 12. According to various aspects, the memory material portion 22 may circumferentially surround (e.g., completely circumferentially surround) the side portion 20 of the electrode column 12. For example, the electrode column 12 may have a cylindrical shape and the side portion 20 may be defined by an arc of a circle (e.g., a complete circumference of a circle) provided by the cylindrical shape in the xy plane and the height of the side portion 20 may be defined by a z coordinate. In this case, the side portion 20 may be a curved surface. For example, the bottom surface 14 and / or the top surface 16 of the electrode column 12 may have an n-gonal shape and the side portion 20 may be defined by one or more sides of the electrode column 12 in the xy plane (e.g., by all sides when the side portion 20 completely surrounds the electrode column 12), and the height of the side portion 20 may be defined by the z coordinate (e.g., in the z direction). According to various aspects, the surface of the memory material portion 22 may face the side portion 20. The surface of the memory material portion 22 facing the side portion 20 may be substantially parallel to the side portion 20. The surface of the memory material portion 22 facing the side portion 20 may be substantially coaxial with the side portion 20. For example, in the case where the electrode column 12 has a cylindrical shape, the surface of the memory material portion 22 facing the side portion 20 may be shaped as an arc, and the arc may be substantially coaxial with the arc defined by the side portion 20. For example, in the case where the electrode column 12 has a polygonal shape, the surface of the memory material portion 22 facing the side portion 20 may include one or more surface portions, and each surface portion may be substantially coaxial with the side of the polygonal side portion 20. According to various aspects, the memory material portion 22 may directly contact the electrode column 12. For example, the surface of the memory material portion 22 may directly contact the side portion 20 of the electrode column 12.

[0056] The memory cell 1 may include an electrode layer 24. The electrode layer 24 may surround the memory material portion 22. The electrode layer 24 may surround the side portion 20. For example, the electrode layer 24 may circumferentially surround (e.g., completely circumferentially surround) the memory material portion 22. According to various aspects, a surface of the electrode layer 24 may face the side portion 20. The surface of the electrode layer 24 facing the side portion 20 may be substantially parallel to the side portion 20. The surface of the electrode layer 24 facing the side portion 20 may be substantially coaxial with the side portion 20. For example, in the case where the electrode column 12 has a cylindrical shape, the surface of the electrode layer 24 facing the side portion 20 may be shaped as an arc, and the arc shape may be substantially coaxial with the arc defined by the side portion 20. For example, in the case where the electrode column 12 has a polygonal shape, the surface of the electrode layer 24 facing the side portion 20 may include one or more surface portions, and each surface portion may be substantially coaxial with the side of the polygonal side portion 20. The memory material portion 22 may be disposed between the surface of the electrode layer facing the side portion 20 and the side portion 20. According to various aspects, the electrode layer 24 may directly contact the memory material portion 22. For example, the surface of the electrode layer 24 may directly contact the memory material portion 22. The electrode layer 24 may have a width defined in the x-direction and / or the y-direction, which is greater than the height defined in the z-direction. The electrode layer 24 may have a flat shape. The electrode layer 24 may be arranged at a certain angle to the electrode column 12. The angle between the electrode layer 24 and the electrode column 12 may be between about 45° and about 90°. The electrode layer 24 may be arranged at a certain angle relative to the z-direction. Illustratively, the electrode column 12 may extend in or along a first direction (e.g., the z-direction), and the electrode layer 24 may extend in a second direction (e.g., the x-direction and / or the y-direction) different from the first direction. According to various aspects, the electrode layer 24 may be perpendicular to the xy plane. For example, the electrode layer 24 may be parallel to the lateral direction (e.g., the in-plane direction) of the substrate and / or the chip. For example, the electrode layer 24 may extend in the lateral direction of the substrate. According to various aspects, the memory cell arrangement 10 may include one or more metallization layers arranged on or above the substrate. The electrode layer 24 may be substantially parallel to the one or more metallization layers.

[0057] Illustratively, the electrode layer 24 may include a hole (e.g., a groove). The hole may extend from a first surface of the electrode layer 24 to a second surface of the electrode layer 24 opposite to the first surface of the electrode layer 24. The electrode column 12 may be disposed in the hole of the electrode layer 24. The memory material portion 22 may be disposed at least in the hole of the electrode layer 24, in the gap between the electrode layer 24 and the side portion 20. It should be noted that the term "hole in the layer" may be understood as: the hole is defined by a specific (e.g., patterned) structure of the layer, and the hole may or may not be filled with one or more materials. In various aspects, a hole may be provided in the electrode layer, wherein the hole is at least partially filled with a material different from the material of the electrode layer. One or more material portions filling the hole may be part of a memory cell and may be combined with the electrode layer to form a capacitor structure (e.g., a capacitive memory structure).

[0058] According to various aspects, the electrode pillars 12, the memory material portions 20, and the electrode layers 24 can form a capacitive memory structure 2 (also referred to in some aspects as a memory capacitor or a memory capacitor structure). The capacitive memory structure 2 can be configured to have at least a first memory state and a second memory state (e.g., an LVT state and an HVT state) as described herein (e.g., to store bits).

[0059] The memory cell 1 may include a transistor structure, for example, a field effect transistor structure 30. The field effect transistor structure 30 may be a metal oxide semiconductor (MOS) field effect transistor structure (for example, referred to as a MOSFET). However, any other suitable transistor structure may be used in the same or similar manner. The field effect transistor structure 30 may include a gate structure. The bottom surface 14 of the electrode column 12 may face the gate structure. The electrode column 12 (for example, the bottom surface 14 of the electrode column 12) may be conductively connected to the gate structure. The top surface 16 of the electrode column 12 may face away from the gate structure. The distance between the bottom surface 14 of the electrode column 12 and the gate structure may be less than the distance between the top surface 16 of the electrode column 12 and the gate structure. Illustratively, the bottom surface 14 may be closer to the gate structure than the top surface 16. The vertical distance between the electrode layer 24 and the gate structure may be substantially consistent. The vertical distance may be a distance perpendicular to the bottom surface 14 and / or the top surface 16. The electrode layer 24 may include or may be made of Cu, Au, Ag, W, Al, Ru, Ti, TiN, Ta, TaN, Co, CoN, Nb, NbN, Pd, Pt, Ir, IrO 2 、RuO 2 , Poly-Si, etc.

[0060] Figure 1BA memory cell arrangement 10 is schematically shown including a field effect transistor structure 30 having a planar gate structure 32 according to various aspects. According to various aspects, the field effect transistor structure 30 may include a first terminal 34 (e.g., a source terminal) and a second terminal 36 (e.g., a drain terminal). According to various aspects, the electrode layer 24 may be substantially parallel to the gate structure. For example, the electrode layer 24 may have a first surface and a second surface opposite the first surface, and the first surface and / or the second surface may be substantially parallel to the gate structure (e.g., a surface of the gate structure). However, it should be noted that the gate structure may have any kind of shape. For example, the field effect transistor structure 30 may be or may include a fin FET structure and the gate structure may be U-shaped or similar to a U-shape.

[0061] Figure 1C A perspective view of a memory cell arrangement 10 according to various aspects is shown by way of example. The memory cell arrangement 10 may include a memory cell 1. The bottom surface 14 and the top surface 16 of the electrode column 12 may each have a circular shape and the electrode column 12 may have a cylindrical shape. The memory material portion 22 may completely surround the side portion 20. In this example, the memory material layer may completely surround the side 18 of the electrode column 12. The memory material layer may form the memory material portion 22. The memory material portion 22 may directly contact the electrode column 12. The electrode layer 24 may have a flat shape. The electrode layer 24 may completely surround the electrode column 12 and the memory material portion 22. The electrode layer 24 may directly contact the memory material portion 22.

[0062] Figure 2A A memory cell arrangement 10 including a first memory cell 1A and a second memory cell 1B according to various aspects is schematically shown. Figure 2B A perspective view of a memory cell arrangement 10 including a first memory cell 1A and a second memory cell 1B according to various aspects is shown by way of example. Each of the first memory cell 1A and the second memory cell 1B may be configured according to the memory cell 1. According to various aspects, the memory cell arrangement 10 may include a common electrode layer 24. The common electrode layer 24 may provide an electrode layer 24 of each of the first memory cell 1A and the second memory cell 1B. According to various aspects, the electrode column 12A of the first memory cell 1A and the electrode column 12B of the second memory cell 1B may be spaced apart from each other.

[0063] Figure 3A A memory cell arrangement 10 comprising two electrode layers according to various aspects is schematically shown. Figure 3BA perspective view of a memory cell arrangement 10 including two electrode layers according to various aspects is shown by way of example. The electrode layer 24 may be a first electrode layer 24. The memory cell 1 may further include a second electrode layer 44. The memory cell 1 may include a dielectric material portion 42. The dielectric material portion 42 may surround (e.g., circumferentially surround, e.g., completely circumferentially surround) a second side portion 40 of the electrode column 12. The second side portion 40 may be different from the side portion 20 (hereinafter also referred to as the first side portion 20). The second electrode layer 44 may surround the dielectric material portion 42 and the second side portion 40 of the electrode column 12. According to various aspects, the geometry of the dielectric material portion 42 may be configured to be similar to the memory material portion 22, such as shape, alignment, geometric constraints, etc. According to various aspects, the second electrode layer 44 may be configured similarly to the first electrode layer 24 with respect to geometric properties, material properties, etc. According to various aspects, the first electrode layer 24 may extend in a first plane (e.g., parallel to the xy plane) along a first direction (e.g., y direction), and the second electrode layer 44 may extend in a second plane (e.g., parallel to the xy plane, e.g., different from the first plane) along a second direction (e.g., x direction) different from the first direction. For example, the first electrode layer 24 and the second electrode layer 44 may extend at an angle of about 45° or more relative to each other. The first electrode layer 24 and the second electrode layer 44 may be spaced apart from each other. According to various aspects, the memory cell arrangement 10 may include at least one intermediate layer (e.g., an isolation intermediate layer, e.g., a dielectric intermediate layer) disposed between the first electrode layer 24 and the second electrode layer 44. According to various aspects, the height h(24) of the first electrode layer 24 (e.g., defined in the z direction) may be different from the height h(44) of the second electrode layer 44 (e.g., defined in the z direction). For example, the height h(44) of the second electrode layer 44 may be greater than the height h(24) of the first electrode layer 24, or vice versa. The first electrode layer 24 may directly contact the memory material portion 22, and the second electrode layer 44 may directly contact the dielectric material portion 42. The contact area between the dielectric material portion 42 and the second electrode layer 44 may be greater than the contact area between the memory material portion 22 and the first electrode layer 24, and vice versa. The memory material portion 22 may directly contact the first side portion 20, and the dielectric material portion 42 may directly contact the second side portion 40. The contact area between the dielectric material portion 42 and the second side portion 40 may be greater than the contact area between the memory material portion 22 and the first side portion 20, and vice versa.

[0064] According to various aspects, the capacitance of the capacitor storage structure can be controlled by the height h(24) of the first electrode layer 24. According to various aspects, the electrode column 12, the dielectric material portion 42 and the second electrode layer 44 can form a capacitor structure. If not otherwise explicitly stated, the dielectric material portion as described herein may include a non-spontaneously polarized dielectric material. According to various aspects, the non-spontaneously polarized dielectric material portion 42, the electrode column 12 and the second electrode layer 44 can form a capacitor structure, also referred to as a capacitor lever structure in some aspects. If not otherwise explicitly stated, the capacitor lever structure (also referred to as a lever capacitor or a lever capacitor structure in some aspects) may include a non-spontaneously polarized dielectric material portion 42. According to various aspects, the capacitance of the capacitor structure can be controlled by the height h(44) of the second electrode layer 44. According to various aspects, the capacitor storage structure 2 can have a first capacitance and the capacitive structure can have a second capacitance different from the first capacitance. According to various aspects, the ratio of the first capacitance to the second capacitance can be controlled by the height h(24) of the first electrode layer 24 and / or the height h(44) of the second electrode layer 44. Illustratively, the first capacitance, the second capacitance and / or their ratio are adjustable. Therefore, the first capacitance, the second capacitance and / or their ratio can be controlled by controlling the thickness of the corresponding electrode layer. In some cases, compared with other techniques that can control the capacitance by controlling the width, the layer can be prepared (e.g., by deposition, e.g., by etching, etc.) more accurately, for example, the width can be controlled by photolithography. For example, photolithography can have an accuracy of about 5nm, while the layer can be prepared accurately to the atomic layer.

[0065] Illustratively, the second electrode layer 44 may include a hole (e.g., a groove). The hole may extend from the first surface of the second electrode layer 44 to the second surface of the second electrode layer 44 opposite to the first surface of the second electrode layer 44. The electrode column 12 may be disposed in the hole of the second electrode layer 44. The dielectric material portion 42 may be disposed at least in the hole of the second electrode layer 44, in the gap between the second electrode layer 44 and the second side portion 40.

[0066] According to various aspects, dielectric material portion 42 may include or may consist of a memory material. For example, memory material portion 22 may be a first memory material portion, and dielectric material portion 42 may be a second memory material portion. In this case, dielectric material portion 42 may include or may consist of a spontaneously polarized material, and the capacitor structure including dielectric material portion 42 may be a capacitive memory structure.

[0067] Figure 3CSchematically illustrates a memory cell arrangement 10 according to various aspects. The memory cell arrangement 10 may include an additional second electrode layer 44B. The memory cell 1 may include an additional dielectric material portion 42B. The additional dielectric material portion 42B may surround (e.g., circumferentially surround, e.g., completely circumferentially surround) an additional second side portion 40B of the electrode column 12. The additional second side portion 40B may be different from the second side portion 40 (hereinafter also referred to as the second side portion 40A) and different from the first side portion 20.

[0068] According to various aspects, the additional dielectric material portion 42B can be configured similar to the dielectric portion 42 herein. According to various aspects, the additional electrode layer 44B can be configured similar to the electrode layer 44 herein. According to various aspects, the height h(44A) of the second electrode layer 44A can be greater than the height h(44B) of the additional second electrode layer 44B, and vice versa. According to various aspects, the electrode column 12, the additional dielectric material portion 42B, and the additional second electrode layer 44B can form an additional capacitor structure.

[0069] about Figure 3D , the memory cell 1 may include a dielectric material layer 50. The dielectric material layer 50 may substantially continuously surround (e.g., circumferentially surround, e.g., completely circumferentially surround) at least a portion of the side 18 of the electrode column 12. The dielectric material layer 50 may provide a dielectric material portion 42A associated with the second electrode layer 44A and an additional dielectric material portion 42B associated with the additional second electrode layer 44B. According to various aspects, the dielectric material portion 42 may include or may consist of a memory material (e.g., a spontaneously polarized material). According to various aspects, the dielectric material layer 50 may provide a dielectric material portion 42A, an additional dielectric material portion 42B, and a memory material portion 24. In this case, the sum of the height h(44A) of the second electrode layer 44A and the height h(44B) of the additional second electrode layer 44B may be greater than the height h(24) of the first electrode layer 24. According to various aspects, the height h( 44A) of the second electrode layer 44A and the height h( 44B) of the additional second electrode layer 44B may each be greater than the height h( 24 ) of the first electrode layer 24 .

[0070] Figure 4ASchematically, a memory cell 100 according to various aspects is shown. The memory cell 100 may include a transistor structure, such as a field effect transistor structure 102. The field effect transistor structure 102 may be a metal oxide semiconductor (MOS) field effect transistor structure 102 (e.g., referred to as a MOSFET). However, any other suitable transistor structure may be used in the same or similar manner. According to various aspects, the memory cell 100 may include two capacitor structures, such as a first capacitor structure 104 and a second capacitor structure 106. Illustratively, the memory cell 100 may be configured as a 1T2C cell (i.e., a memory cell including one transistor 1T and two capacitors 2C). According to various aspects, the first capacitor structure 104 may be a first capacitor memory structure. According to various aspects, the second capacitor structure 106 may be a capacitor lever structure. Therefore, even in the case where the second capacitor structure 106 includes one or more residual polarization portions and / or one or more residual polarization layers, these one or more residual polarization portions and / or one or more residual polarization layers may not be switched as a lever capacitor during operation. Illustratively, the second capacitor structure 106 may effectively be used as a dielectric (non-spontaneous polarization) capacitor structure.

[0071] The memory cell 100 may include a first control node 104c (eg, a node to be connected to a word line, to which a write voltage V FE =V PP node, applying a read voltage V FE =V G , as an example) and a second control node 106c (eg, a node to be connected to a lever line, a node to be applied with a lever voltage V LE , as an example). The first capacitor structure 104 may include a first electrode 104e-1, for example, connected to a first control node 104c of the memory cell 100. The first capacitor structure 104 may also include a second electrode 104e-2 connected to the field effect transistor structure 102, for example, connected to a gate structure or gate node of the field effect transistor structure 102. In some aspects, the field effect transistor structure 102 may include a gate structure 102g to control the field effect transistor structure 102, for example, to control a current flowing through the field effect transistor structure 102 or to control the conductivity of a channel of the field effect transistor structure 102. According to some aspects, the field effect transistor structure 102 may include or may be a long channel MOSFET. The long channel MOSFET may include a channel length greater than about 50nm. The memory cell 100 may include a gate node 102f at which a gate voltage V FGto control the field effect transistor structure 102. The gate structure 102g of the field effect transistor structure 102 can be configured to be electrically floating. According to various aspects, the second electrode 104e-2 of the first capacitor structure 104 can be connected to the gate node 102f.

[0072] According to various aspects, the first capacitor structure 104 may include a remanent polarization layer or region 104r disposed between a first electrode 104e-1 and a second electrode 104e-2. According to various aspects, the first capacitor structure 104 may have a layered design including one or more remanent polarization layers sandwiched between two electrode layers. One or more remanent polarization layers may be provided between the electrodes 104e-1, 104e-2 of the first capacitor structure 104. According to various aspects, the first capacitor structure may be a ferroelectric capacitor (also referred to as a FeCAP). The FeCAP may be a memory element of the memory cell 100 for storing information bit by bit.

[0073] According to various aspects, the second capacitor structure 106 can include a first electrode 106e-1 connected to the second control node 106c and a second electrode 106e-2 connected to the field effect transistor structure 102 (e.g., a gate of the field effect transistor). According to various aspects, the second electrode 106e-2 of the second capacitor structure 106 can be connected to the gate node 102f.

[0074] According to various aspects, the second capacitor structure 106 may include an electrically isolated region 106i disposed between a first electrode 106e-1 and a second electrode 106e-2 of the second capacitor structure 106. According to various aspects, one or more dielectric layers (in other words, one or more electrically insulating layers) may be provided between the electrodes 106e-1, 106e-2 of the second capacitor structure 106. In another aspect, one or more residual polarization layers may be provided between the electrodes 106e-1, 106e-2 of the second capacitor structure 106. According to various aspects, the second capacitor structure may be a dielectric capacitor or a ferroelectric capacitor (also referred to as FeCAP). According to various aspects, the second capacitor structure 106 may include a layered design having one or more residual polarization layers and / or one or more dielectric layers sandwiched between two electrode layers. However, if integration allows, a gap between the electrodes 106e-1, 106e-2 of the second capacitor structure 106 may be provided that does not contain any solid material. In this case, no dielectric material may be provided between the electrodes 106e-1, 106e-2 of the second capacitor structure 106.

[0075] According to various aspects, the first capacitor structure 104 and the second capacitor structure 106 may include the same material but may have different respective capacitances from each other. In some aspects, the first capacitor structure 104 has a first capacitance C FEThe second capacitor structure 106 has a second capacitance C LE , where the first capacitor C FE Different from the second capacitor C LE For example, the capacitance C of the second capacitor structure 106 is LE The capacitance C of the first capacitor structure 104 may be at least 10% (eg, 10%, eg, greater than 15%, eg, greater than 20%, eg, greater than 30%, eg, greater than 40%, etc.) different from the capacitance C of the first capacitor structure 104. FE For example, the capacitance C of the second capacitor structure 106 is LE The capacitance C of the first capacitor structure 104 may be greater than FE For example, the capacitance C of the second capacitor structure 106 is LE may be greater than the capacitance C of the first capacitor structure 104. FE The lever voltage V having a first voltage value may be at least 10% greater (e.g., 10%, e.g., greater than 15%, e.g., greater than 20%, e.g., greater than 30%, e.g., greater than 40%, etc.). This may allow, for example, efficient reading of the memory cell 100 and, for example, simultaneously allow efficient writing of the memory cell 100. For example, during the reading process, a lever voltage V having a first voltage value may be applied at the second control node 106c. LE , and a lever voltage V having a second voltage value may be applied at the second control node 106c during the write process LE , wherein the first voltage value may be different from the second voltage value.

[0076] There may be a variety of options for modifying the capacitance of the capacitor structure, for example, the distance between the capacitor electrodes may be reduced to increase the capacitance of the capacitor structure, and vice versa. Another possibility may include increasing the effective area of ​​the capacitor electrodes to increase the capacitance of the capacitor structure. Another possibility may include using a dielectric material disposed between the capacitor electrodes, the higher the relative dielectric constant of the dielectric material, the higher the capacitance of the capacitor structure. According to various aspects, the effective area of ​​the capacitor structure may be determined by the geometric vertical projection of one electrode of the capacitor structure to another electrode of the capacitor structure. Increasing the effective area of ​​the capacitor structure (e.g., while maintaining a relatively low footprint) may be configuring the capacitor structure as a three-dimensional capacitor structure including at least one curved or angled portion.

[0077] According to various aspects, the memory cell 100 may include a third control node (e.g., a first source / drain node) 102c-1 coupled to a first region (e.g., a first source / drain region) 102d of the field effect transistor structure 102 and a fourth control node (e.g., a second source / drain node) 102c-2 coupled to a second region (e.g., a second source / drain region) 102s of the field effect transistor structure 102.

[0078] According to various aspects, the field effect transistor structure 102 can have a third capacitor C associated therewith. MOS In some aspects, the capacitance C of the field effect transistor structure 102 is MOS It may be at least partially caused by its gating design. It may be noted that the first capacitor structure 104 and the second capacitor structure 106 are shown (e.g., in Figure 4A ) is a single capacitor. However, the first capacitor structure 104 may include more than one capacitor, for example, a capacitor arrangement including at least two capacitors (e.g., at least two FeCAPs) coupled in parallel between the first control node 104c and the gate node 102f. In addition, the second capacitor structure 106 may include more than one capacitor, for example, a capacitor arrangement including at least two capacitors (e.g., at least two dielectric capacitors, for example, at least two ferroelectric capacitors) coupled in parallel between the second control node 106c and the gate node 102f.

[0079] According to various aspects, the second capacitor structure 106 may be a non-ferroelectric capacitor structure, i.e., another material other than a ferroelectric material may be disposed between the two electrodes 106e-1, 106e-2 of the second capacitor structure 106. According to various aspects, the second capacitor structure 106 may be or may include a linear capacitor (such as a dielectric capacitor). A linear capacitor may be configured to exhibit a linear characteristic in a current-voltage characteristic, i.e., a linear IV curve.

[0080] One or more issues associated with if the second capacitor structure 106 is not included in the memory cell 100, ie, one or more issues associated with a standard 1T1C memory cell that does not include a levered capacitor structure therein, are described below.

[0081] A 1T1C ferroelectric field effect transistor (FeFET) may include a ferroelectric field effect transistor (FeFET) connected to a single field effect transistor structure (eg, having a capacitor C MOS ) of the gate of a single ferroelectric capacitor (e.g., having a capacitance C FE ). The charge generated by the ferroelectric capacitor modifies the effective gate voltage to control the field effect transistor. According to various aspects, the capacitance C of the two elements can be adjusted MOS and C FE , therefore, the voltage drop across the ferroelectric capacitor can be adjusted to have an efficient write operation or an efficient read operation, ie, either reduce the gate voltage or reduce (eg, minimize) read disturbance, as explained in more detail below.

[0082] In the first case, the capacitor C MOS Can be substantially larger than the capacitance C FE This allows lower write voltage V PPThe advantage is that the write voltage can be reduced, since most of the voltage is likely to be across the ferroelectric capacitor (C FE ) drops. However, a disadvantage may be that during the read operation, the read voltage V G The ferroelectric capacitor (C FE ) decreases, which reduces the effect on the field effect transistor structure (C MOS ) control. MOS With C FE When the capacitance ratio is very high, the field effect transistor may not be effectively controlled in some cases because most of the voltage may be across the ferroelectric capacitor (C FE ) decreases, which may cause read disturbance due to rewriting the memory state during the read process. In addition, the capacitance of a field effect transistor (e.g., a MOSFET) can be nonlinear, which may make it difficult to set a specific capacitance ratio C MOS / C FE .

[0083] In the second case, C FE Can be significantly greater than C MOS This can allow read disturb to be reduced. The advantage is that read disturb can be avoided, since most of the voltage may be across the field effect transistor (C MOS ) drops. However, a disadvantage may be that all voltages may drop across the field effect transistor during a write operation, which increases the voltage required to write to the memory cell. In addition, the cross-C MOS and C FE The voltage drop may vary with C MOS / C FE ratio decreases, which may cause the ferroelectric capacitor (C FE ) depolarization.

[0084] Compared to common approaches, the memory cell 100 described herein may include a lever capacitor structure in addition to a ferroelectric capacitor. In this case, the ferroelectric capacitor may be used to store actual information in the memory cell, while the lever capacitor may be used to modify the voltage state in the memory cell 100 to improve operation. The lever capacitor (e.g., embodied by the second capacitor structure 106) may be used to modify the voltage distribution between elements of the memory cell 100 so that reading and writing may be performed efficiently, as explained in more detail below.

[0085] According to various aspects, a lever capacitor (C LE ) of a memory cell 100, for example, wherein a lever capacitor (C LE) can be used to change the voltage dropped across the ferroelectric capacitor during writing and reading. For example, using a lever capacitor can allow for lower write voltages and avoid destructive reads or any other read disturbances. The lever capacitor can be a ferroelectric capacitor, a dielectric capacitor, or any suitable capacitor structure. The ferroelectric capacitor storing the actual information (e.g., embodied by the first capacitor structure 104) and the lever capacitor can have different capacitances. The equation for calculating the floating gate potential can be given by:

[0086] V FG ≈(V FE C FE +V LE C LE +V MOS C MOS +Q FE ) / (C FE +C LE +C MOS ),

[0087] Among them, V FE can be the voltage applied to the ferroelectric capacitor, V LE can be the voltage applied to the level capacitor, V MOS can be the voltage applied to the field effect transistor (e.g., the source / body and drain of the field effect transistor), Q FE Can be a ferroelectric charge, C LE can be the capacitance of the lever capacitor, and C FE Can be the capacitance of a ferroelectric capacitor (see Figure 4A ).

[0088] As an example, during a write operation, the voltage / potential V PP can be applied to the ferroelectric capacitor node so that V FE Can be basically equal to V PP , while the lever capacitor and the field effect transistor (eg, embodied by field effect transistor structure 102) may be grounded, such that V SS (base voltage) can be basically equal to V LE And make V LE Can be basically equal to V MOS According to the lever capacitance C LE and the FET capacitor C MOS , the voltage drop across the ferroelectric capacitor can be tuned to C MOS +C LE , which is basically greater than C FE , and most of the voltage V PP can drop across the ferroelectric capacitor. This can significantly reduce the write voltage and produce ferroelectric polarization charge Q FE .

[0089] In C MOS +C LE Basically greater than C FE Under the assumption of , the equation for calculating the floating gate potential gives the following result:

[0090] V FG ≈V FE C FE / (C LE +C MOS )≈V SS .

[0091] It can be noted that when choosing C large enough MOS In the case of , this goal can be achieved by a classic FeFET structure with only one capacitor connected to the gate. However, this may lead to read disturb problems as above. However, as explained in more detail below, read disturb can be prevented by using the configuration described herein with respect to memory cell 100.

[0092] During a read of a memory cell (e.g., to detect the ferroelectric charge Q FE ), the read voltage V G applied to the ferroelectric capacitor node (so that V FE Can be basically equal to V G ) and the lever capacitor node (making V LE Can be basically equal to V G ). However, a voltage lower than the read voltage V G The voltage, for example, between V G / 2 to V G As an example, the read voltage may be applied to both the first control node 104c and the second control node 106c of the memory cell 100. Thus, the capacitive voltage divider provided by the two capacitors 104, 106 of the memory cell 100 and the field effect transistor structure 102 may be varied by the applied voltage and provide C MOS Can be significantly smaller than C LE +C FE condition, and as a result, most of the voltage may be dropped across the field effect transistor structure 102, which allows non-destructive reading.

[0093] According to various aspects, due to the additional terminal connected to the lever capacitor (e.g. due to the second control terminal 106c), it is possible to change the effective capacitive voltage divider of the memory cell 100 during writing and / or reading. This allows, for example, avoiding the disadvantages described above with reference to a standard 1T1C memory cell. If C LE Can be basically greater than C MOS And if C LE Can be basically greater than C FE, then the lever capacitor C LE In the case of linear capacitors, the nonlinearity of MOS capacitors can be significantly reduced.

[0094] In C MOS Basically smaller than C LE +C FE Under the assumption of , the equation for calculating the floating gate potential gives the following result:

[0095] V FG ≈V G +Q FE / C LE .

[0096] According to various aspects, the drain voltage applied to the third control node 102 c - 1 may be used to transfer charge across the inversion layer of the field effect transistor structure 102 and read out the ferroelectric state of the first capacitor structure 104 .

[0097] During the retention period, all terminals of the memory cell 100 (in other words, all control nodes 102c-1, 102c-2, 104c, 106c) may be grounded, and the floating gate potential (V FG ) can be mainly determined by the lever capacitance (C LE ), assuming C LE Probably larger than C MOS And C LE Probably larger than C FE , which can be used to reduce the depolarization field of the ferroelectric, as can be seen from the following equation:

[0098] V FG ≈Q FE / C LE .

[0099] According to various aspects, the lever capacitance value may be selected accordingly to obtain a sufficiently high change in the gate voltage of the field effect transistor during a read operation and to obtain a low floating gate potential during a holding phase.

[0100] Figure 4BSchematically illustrates an example configuration of a memory cell arrangement 200 according to various aspects. In some aspects, the memory cell arrangement 200 may include a plurality of memory cells 100, as described herein. However, other suitable memory cells may be used in the same or similar manner. As an example, each memory cell 202 of the memory cell arrangement 200 may include a field effect transistor structure (referred to as a field effect transistor, FET), a ferroelectric capacitor structure (referred to as a ferroelectric capacitor, FeCAP), and an additional capacitor structure (referred to as a lever capacitor, LeCAP). The additional capacitor structure may include or may be a ferroelectric capacitor, a dielectric capacitor, or any other suitable capacitor. In some aspects, the memory cells 202 of the memory cell arrangement 200 may be as described in reference Figure 4A 1. The memory cell 100 shown in FIG. 1 is configured as described. In another aspect, each memory cell 202 of the memory cell arrangement 200 can be configured such that the ferroelectric capacitor structure and the additional capacitor structure have the same capacitance. In some aspects, each memory cell 202 of the memory cell arrangement 200 can include two ferroelectric capacitors, wherein one of the two ferroelectric capacitors can be configured to store a charge representing actual information of the memory cell 202 (e.g., representing a logical "0" or a logical "1"), and wherein the other of the two ferroelectric capacitors can be configured as a lever capacitor.

[0101] According to various aspects, each memory cell 202 of the memory cell arrangement 200 may include four nodes, or in other words, four terminals. The nodes / terminals may be used to address the memory cells 202 of the memory cell arrangement 200 to read and / or write to the corresponding memory cells 202. Figure 4B As shown, each memory cell 202 may include a first control node 202-1, a second control node 202-2, a third control node 202-3, and a fourth control node 202-4. The first control node 202-1 may be connected to a ferroelectric capacitor of the memory cell 202. The second control node 202-2 may be connected to a lever capacitor of the memory cell 202. The third control node 202-3 may be connected to a field effect transistor of the memory cell 202 (e.g., connected to a first source / drain region of the field effect transistor, referred to as a drain). The fourth control node 202-4 may be connected to a field effect transistor of the memory cell 202 (e.g., connected to a second source / drain region of the field effect transistor, referred to as a source).

[0102] As an example, by applying corresponding voltages at the control nodes, the electrical characteristics of the third control node 202-3 and the fourth control node 202-4 of the corresponding memory cell 202 can be controlled. For example, the current between the third control node 202-3 and the fourth control node 202-4 can be controlled by applying corresponding voltages to the first control node 202-1 and the second control node 202-2. As another example, the voltage output at the third control node 202-3 can be controlled by applying corresponding voltages to the first control node 202-1 and the second control node 202-2.

[0103] According to various aspects, each of the plurality of memory cells 202 of the memory cell arrangement 200 may be a field effect transistor (FET) based memory cell and may include two source / drain regions and a gate region (also referred to as a gate structure) to control the current between the two source / drain regions. In various aspects, each of the one or more memory cells 202 may include a field effect transistor structure. As an example, each memory cell 202 may include a gate node, a source node, and a drain node. The gate node may be coupled to the gate region of the memory cell 202 via the first capacitor structure 104 (e.g., via a ferroelectric capacitor). The source node may be coupled to the source region of the memory cell. The drain node may be coupled to the drain region of the memory cell 202.

[0104] The memory cells 202 of the memory cell arrangement 200 may be arranged, for example, in a matrix architecture. The memory cells 202 may be arranged in n columns and m rows, where m and n are integers greater than 1. For example only, Figure 4B Two columns (e.g., a first column and a second column) and two rows (a first row and a second row) of a memory cell arrangement 200 are shown, each including two memory cells 202. The memory cell arrangement 200 may include any suitable number of memory cells 202 arranged in any suitable number n of columns and any suitable number m of rows. The memory cells 202 in each row may be from a respective first subset of memory cells, and the memory cells 202 in each column may be from a respective second subset of memory cells.

[0105] According to various aspects, the memory cell arrangement 200 may include a plurality of control lines 204, 206, 208 (e.g., one or more word lines WL, one or more bit lines BL, and one or more lever lines LL) coupled to the memory cells 202. The control lines 204, 206, 208 may be used to provide voltages / potentials to control nodes of the memory cells 202. The plurality of control lines 204, 206, 208 may be arranged in any suitable manner, such as defined by a desired matrix architecture of the memory cell arrangement 200.

[0106] According to various aspects, the first control node 202-1 of each memory cell 202 can be connected to a corresponding first control line 204(1), 204(2) (e.g., a corresponding word line WL). The second control node 202-2 of each memory cell 202 can be connected to a corresponding second control line 206(1), 206(2) (e.g., a corresponding lever line LL). According to various aspects, the third control node 202-3 of each memory cell 202 can be connected to a corresponding third control line 208(1), 208(2) (e.g., a corresponding bit line BL). According to various aspects, the fourth control node 202-4 of each memory cell 202 can be connected to a common control node (e.g., a common source node or a common source region). However, if desired, the fourth control node 202-4 can be addressed via one or more corresponding fourth control lines (not shown) (e.g., via one or more corresponding source lines (not shown)). Illustratively, each memory cell 202 of the memory cell arrangement 200 can be explicitly assigned to one word line WL, one lever line LL, and one bit line BL. According to various aspects, the memory cell arrangement 202 may include a set of word lines (e.g., a first word line WL(1) and a second word line WL(2), as an example), a set of bit lines (e.g., a first bit line BL(1) and a second bit line BL(2), as an example), and a set of lever lines (e.g., a first lever line LL(1) and a second lever line LL(2), as an example). The memory cell arrangement 200 may include any suitable number of control lines. According to various aspects, each word line WL may be coupled to each memory cell 202 in the same row of the memory cells 202. Each bit line BL may be coupled to each memory cell 202 in the same row of the memory cells 202. Each lever line LL may be coupled to each memory cell 202 in the same column of the memory cells 102. According to various aspects, the word lines and the lever lines may be connected to different subsets of the memory cells 202 of the memory cell arrangement 200. According to various aspects, the bit lines and the lever lines may be connected to different subsets of the memory cells 202 of the memory cell arrangement 200. According to various aspects, the bit lines and word lines can be connected to the same subset of the memory cells 202 of the memory cell arrangement 200 .

[0107] According to various aspects, each memory cell 202 of the memory cell arrangement 200 may include a remanent polarization layer (e.g., each of the one or more memory cells 102 may include FeCAP). Therefore, the memory state in which the memory cell 202 resides may be associated with one of the at least two polarization states of the corresponding remanent polarization layer. The first threshold voltage V of the field effect transistor of the memory cell 202 L-thmay be associated with (eg, may be a function of) the first (eg, positive) remnant polarization of the remnant polarization layer, and the second threshold voltage V H-th may be associated with (eg, it may be a function of) a second (eg, negative) remnant polarization of the remnant polarization layer.

[0108] According to various aspects, the memory cell arrangement 200 may include a control circuit 210. The control circuit 210 may be configured to perform and / or instruct one or more read operations and / or one or more write operations associated with reading and / or writing of the memory cell 202 of the memory cell arrangement 200. The control circuit 210 may be configured to provide one or more control signals (e.g., one or more read signals, one or more write signals, etc.) to the memory cell 202. Illustratively, one or more read signals and one or more write signals may be provided to the corresponding memory cell intended to be read and / or written. The control signal may be understood as any (e.g., constant or time-varying) potential or voltage provided at the corresponding node of the memory cell and / or provided to the control line of the memory cell arrangement 200. According to various aspects, the control circuit 210 may include or may control one or more voltage supply circuits. One or more voltage supply circuits may be used to supply a control voltage (e.g., a read voltage V G , write voltage V PP , base voltage V SS , as an example), for example, for providing a voltage to the corresponding control nodes 201-1, 201-2, 201-3, 201-4 of one or more memory cells 202. According to various aspects, the control circuit 210 can define a base voltage associated with the memory cell arrangement 200, such as V SS , such as ground voltage (eg, 0V).

[0109] According to various aspects, during the readout of a memory cell, a drain current I may be generated at a bit line corresponding to the memory cell to be read out. D (e.g., by applying a read voltage and a lever voltage accordingly), wherein the drain current may vary as a function of the gate-source voltage drop and thus as a function of the memory state (e.g., LVT state or HVT state) in which the memory cell resides. For example, when the gate-source voltage falls below a first threshold voltage V L-th With the second threshold voltage V H-th In the event of a lag, the current flowing through the memory cell may reflect the memory state in which the memory cell resides.

[0110] In the following, one or more problems that may be associated with a conventional AND architecture for implementing a memory cell arrangement based on a standard 1T1C-FeFET memory cell that does not include a levered capacitor structure are described.

[0111] Generally speaking, ferroelectric transistors (FeFETs) can be organized in an AND architecture, which can allow, for example, single bit programming but only word-based erasure. For example, if the memory cells of the memory cell arrangement include long channel MOS transistors, only an entire row of memory cells can be erased at a time. Bit erasure may be feasible for short channel MOS transistors in which the depletion regions are merged by applying voltages to the source and drain regions. However, high voltages must be used at the source and drain regions during inhibition or bit erasure, which can result in a large amount of reverse junction leakage, thereby increasing the power consumption of the memory cell arrangement during operation.

[0112] Compared to commonly used approaches, the memory cells described herein may include at least two capacitors; and in some aspects, the memory cells may be embedded in an array to prevent the disadvantages mentioned above, such as to prevent large amounts of reverse junction leakage during bit erase, such as to avoid large amounts of read and write disturb.

[0113] According to various aspects, a memory cell arrangement (eg, as referred to herein) Figure 4A The 1T2C memory cells of the memory cell arrangement 200 described above may be organized as an array based on a NOR architecture, such as Figure 4C and Figure 4D shown.

[0114] Figure 4C The writing of a memory cell (1) of a memory cell arrangement 300 according to various aspects is shown by way of example. The memory cell arrangement 300 may be configured in the same or similar manner as described herein with reference to the memory cell arrangement 200, see Figure 4A . Each memory cell 302 of the memory cell arrangement 300 may include a lever capacitor LE, a ferroelectric capacitor FE, and a field effect transistor FT. The lever capacitor LE of the corresponding memory cell 302 may be connected to the corresponding lever line LL(1), LL(2) and the floating gate of the field effect transistor FT of the corresponding memory cell 302. The ferroelectric capacitor FE of the corresponding memory cell 302 may be connected to the corresponding word line WL(1), WL(2) and the floating gate of the field effect transistor FT of the corresponding memory cell 302. The field effect transistor FT may be connected with its source S to a common source potential and with its drain D to the corresponding bit line BL(1), BL(2).

[0115] In this example, it can be assumed that only the memory cell (1) of the memory cell arrangement 300 is intended to be written (selected to be written, for example, referred to as a selected memory cell). To program or erase the memory cell (1), a write voltage V PP is applied to the active word line connected to the ferroelectric capacitor FE of the selected memory cell (1). In this case, the voltage (V FE，ACT ) can be the write voltage V PP (Also called programming voltage V PP ). In addition, in order to program or erase the memory cell (1), the base voltage (e.g., V SS ) or a voltage close to the base voltage is applied to the active lever line connected to the lever capacitor LE of the selected memory cell (1). In this case, the voltage (V LE，ACT ) may be, for example, a base voltage (e.g., 0 V) ​​or a voltage close to the base voltage (e.g., a voltage in the range of about -0.25 V to about 0.25 V). However, a voltage greater than the base voltage (e.g., in the range of about V SS To about V PP / 2) is applied to the active lever line connected to the lever capacitor LE of the selected memory cell (1). In addition, in order to program or erase the memory cell (1), the base voltage (e.g., V SS ) or a voltage close to the base voltage is applied to the active bit line of the field effect transistor FT connected to the selected memory cell (1). In this case, the voltage (V BL，ACT ) may be, for example, a base voltage (eg, 0 V) ​​or a voltage close to the base voltage (eg, a voltage in a range of approximately -0.25 V to approximately 0.25 V).

[0116] According to various aspects, the field effect transistor structure can be in a non-conductive state during writing to the selected memory cell. Illustratively, the field effect transistor structure can be closed during writing to the selected memory cell. This can, for example, increase the speed of writing to the selected memory cell (e.g., with a writing time of less than 15ns, such as with a writing time of less than 10ns). According to various aspects, the write voltage V PP It may be in the range of, for example, about 1V to about 10V, for example, about 1.5V to about 6V.

[0117] According to various aspects, the write voltage V PP The voltage value and the voltage applied to the corresponding lever line (V LE，ACTThe voltage value of the write voltage (V PP ) may have a positive voltage value, and the first (active) lever voltage (V LE，ACT ) may have a negative voltage value, and vice versa. According to an example, the write voltage V PP may have a voltage value of +1.0V, and the first lever voltage V LE，ACT May have a voltage value of -1.0V.

[0118] According to various aspects, disturbance of other memory cells 302 of the memory cell arrangement 300 can be prevented during writing to the selected memory cell (1).

[0119] For example, to avoid disturbing memory cell (2) of memory cell arrangement 300 during writing to memory cell (1), a voltage different from V SS A voltage of V is applied to the passive lever line connected to the lever capacitor LE of the non-selected memory cell (2). Different from V SS A voltage of V may be applied to all passive lever lines connected to the lever capacitors LE of non-selected memory cells of the memory cell arrangement 300 that share the same word line (WL(1)) as the selected memory cell (1). According to various aspects, a voltage (V LE，PAS ) may be, for example, between about 1 / 2*|V PP | to about |V PP | within the range.

[0120] According to various aspects, the first lever voltage (V LE，ACT ) and the voltage (V LE，PAS The voltage value of the first (active) lever voltage (V LE，ACT ) may have a negative voltage value, and the second (passive) lever voltage (V LE，PAS ) may have a positive voltage value, and vice versa. According to an example, the first lever voltage V LE，ACT may have a voltage value of -1.0V, and the second lever voltage V LE，PAS Can have a voltage value of +0.4V.

[0121] According to various aspects, applying a first lever voltage (V LE，ACT ) and / or with the write voltage (V PP ) compared to the second (passive) lever voltage of opposite sign (V LE，PAS) ensures that the memory state of unselected memory cells is not changed (eg, neither written nor erased).

[0122] For example, in order to avoid disturbing the memory cells (3) and (4) of the memory cell arrangement 300 during writing to the memory cell (1), different voltages from V PP A voltage of V is applied to the passive word line connected to the ferroelectric capacitor FE of the non-selected memory cells (3) and (4). PP A voltage of V may be applied to all passive word lines connected to ferroelectric capacitors FE of non-selected memory cells of the memory cell arrangement 300 that do not share the same word line (WL(1)) as the selected memory cell (1). According to various aspects, a voltage (V FE，PAS ) may be, for example, between about 0 V (or V SS ) to about 1 / 2*|V PP | within the range.

[0123] According to various aspects, the write voltage (V PP ) and the voltage (V FE，PAS The voltage value of the write voltage (V PP ) can have positive voltage values ​​and the inhibit voltage (V FE，PAS ) may have a negative voltage value, and vice versa. According to an example, the write voltage V PP can have a voltage value of +1.0V and prohibits the voltage V FE，PAS Can have a voltage value of -0.2V.

[0124] Furthermore, in order to avoid disturbing the memory cells (3), (4) of the memory cell arrangement 300 during writing to the memory cell (1), the base voltage (e.g., V SS ) or a voltage close to the base voltage may be applied to the inactive bit lines of the field effect transistors FT connected to the non-selected memory cells (3), (4). In this case, the voltage (V BL，PAS ) may be, for example, a voltage of 0 V or close to 0 V (eg, a voltage in a range of approximately -0.25 V to approximately 0.25 V).

[0125] As exemplarily described above, individual cells of the memory cell arrangement 300 may be erasable. It should be noted that some or all of the described voltages are merely examples and that deviations from the described voltages are possible.

[0126] As described exemplarily further above, the terminal of the memory cell 302 connected to the bit line (eg, connected to the source / drain region of the field effect transistor of the memory cell 302) may be held at V SS (or at least close to V SS ), thereby eliminating the power consumption from reverse junction leakage from the body to the source and drain during the inhibit period.

[0127] Figure 4D The reading of the memory cell (1) of the memory cell arrangement 300 according to various aspects is shown by way of example. In this example, it can be assumed that only the memory cell (1) of the memory cell arrangement 300 is intended to be read (selected to be written, referred to as the selected memory cell). In order to read the memory cell (1), the read voltage V G is applied to the active word line connected to the ferroelectric capacitor FE of the selected memory cell (1). In this case, the voltage (V FE，ACT ) can be the read voltage V G .

[0128] Furthermore, in order to read the memory cell (1), the voltage (V LE，ACT ) is applied to the active lever line connected to the lever capacitor LE of the selected memory cell (1). In this case, the voltage (V LE，ACT ) can be substantially equal to the read voltage V G .

[0129] In addition, in order to read the memory cell (1), a voltage greater than V SS The potential / voltage is applied to the active bit line of the field effect transistor FT connected to the selected memory cell (1). In this case, the voltage (V BL，ACT ) may be, for example, greater than 0 V. In an example, the voltage (V BL，ACT ) can be 1V.

[0130] The body and source terminals of the field effect transistor of the memory cell can be maintained at or near V SS A voltage (e.g., 0 V or a voltage in a range between about -0.25 V to about 0.25 V).

[0131] According to various aspects, the voltage V G The voltage value and the voltage applied to the corresponding lever line (V LE，ACT The voltage value of the read voltage (V G ) may have a positive voltage value, and the first (active) lever voltage (VLE，ACT ) can have negative voltage values ​​and vice versa.

[0132] According to various aspects, disturbance of other memory cells 302 of the memory cell arrangement 300 can be prevented during reading of the selected memory cell (1).

[0133] For example, to avoid disturbing memory cell (2) of memory cell arrangement 300 during reading of memory cell (1), a voltage different from V G A voltage of V is applied to the passive lever line connected to the lever capacitor LE of the non-selected memory cell (2). Different from V G A voltage of V may be applied to all passive lever lines connected to the lever capacitors LE of non-selected memory cells of the memory cell arrangement 300 that share the same word line (WL(1)) as the selected memory cell (1). According to various aspects, a voltage (V LE，PAS ) may be, for example, between about V SS (e.g., 0V) to about 1 / 2*|V G | within the range.

[0134] According to various aspects, the first lever voltage (V LE，ACT ) and the voltage (V LE，PAS The voltage value of the first (active) lever voltage (V LE，ACT ) may have a positive voltage value, and the second (passive) lever voltage (V LE，PAS ) may have a negative voltage value, and vice versa. According to an example, the first lever voltage V LE，ACT may have a voltage value of +0.6V, and the second lever voltage V LE，PAS Can have a voltage value of -0.1V.

[0135] According to various aspects, applying a first lever voltage (V LE，ACT ) and / or with the read voltage (V G ) compared to the second (passive) lever voltage of opposite sign (V LE，PAS ) ensures that the memory state of unselected memory cells is not changed (eg, neither written nor erased).

[0136] For example, to avoid disturbing memory cells (3) and (4) of the memory cell arrangement 300 during reading of the memory cell (1), different V G A voltage of is applied to the ferroelectric capacitor FE passive word line connected to the non-selected memory cells (3) and (4). Different from VG A voltage of V may be applied to all passive word lines connected to ferroelectric capacitors FE of non-selected memory cells of the memory cell arrangement 300 that do not share the same word line (WL(1)) as the selected memory cell (1). According to various aspects, a voltage (V FE，PAS ) may be, for example, between about V SS (e.g., 0V) to about 1 / 2*|V G | within the range.

[0137] According to various aspects, the read voltage (V G ) and the voltage (V FE，PAS The voltage value of the read voltage (V G ) can have positive voltage values ​​and the inhibit voltage (V FE，PAS ) can have negative voltage values ​​and vice versa.

[0138] Furthermore, in order to avoid disturbing the memory cells (3), (4) of the memory cell arrangement 300 during the reading of the memory cell (1), the base voltage (e.g., V SS ) or a voltage close to the base voltage may be applied to the inactive bit lines of the field effect transistors FT connected to the non-selected memory cells (3), (4). A voltage equal to or close to the base voltage may be applied to all inactive bit lines of the field effect transistors connected to the non-selected memory cells of the memory cell arrangement 300 that do not share the same bit line (BL(1)) as the selected memory cell (1). In this case, the voltage (V BL，PAS ) may be, for example, a voltage of 0 V or close to 0 V (eg, a voltage in a range of approximately -0.25 V to approximately 0.25 V).

[0139] As exemplarily described above, individual cells of the memory cell arrangement 300 may be read. It should be noted that some or all of the described voltages are merely examples and that deviations from the described voltages are possible.

[0140] According to various aspects, the body and source terminals of the transistors of memory cell 302 (including semiconductor material) may be held at V SS , but the active bit line potential can be charged to a level greater than V SS to detect the charge generated by the ferroelectric capacitor FE.

[0141] According to various aspects, the memory cell described herein comprises or consists of a transistor and two capacitors, one of which is a ferroelectric capacitor. By increasing the capacitance of a capacitor that does not exhibit a ferroelectric charge (e.g., a lever capacitor), a programming voltage can be obtained that is close to the programming voltage of an independent ferroelectric capacitor. During reading, the voltage distribution can be changed (compared to writing), so that disturbance of the ferroelectric material in the ferroelectric capacitor can be avoided, and good control of the transistor (e.g., a MOS transistor) can be obtained. During a hold condition, the voltage across the ferroelectric material can be reduced to avoid depolarization of the ferroelectric portion.

[0142] According to various aspects, a NOR architecture is described herein to organize 1T2C memory cells into an array structure to construct a memory array. By coordinating the voltages applied to the two capacitors, interference during the read and write processes can be effectively reduced. For write inhibition, junction leakage can be avoided because all semiconductor terminals can be kept grounded. This structure allows bit variability of long channel transistors. According to various aspects, if necessary, another memory element can be used instead of a ferroelectric capacitor. According to various aspects, if necessary, another transistor can be used instead of a field effect transistor. According to various aspects, the lever capacitor (or the second capacitor structure) can be configured so that it has a capacitance in the range of about 0.01fF to about 100fF, 0.1fF to about 10fF. However, the capacitance of the lever capacitor can be adapted to other elements of the memory cell as needed.

[0143] Fig. 4I An example configuration of a memory cell arrangement 310 including six memory cells 302 having a NOR configuration is shown. The memory cells 302 of the memory cell arrangement 310 may be as described with reference to Figure 4C The memory cell 302 of the memory cell arrangement 310 may be written as described with reference to Figure 4D In an example, to read a selected memory cell, a read voltage having a voltage value of about 0.6 V may be applied to a word line (WL) corresponding to the selected memory cell, and a first (active) lever voltage having a voltage value of about 0.9 V may be applied to a lever line (LL) corresponding to the selected memory cell. For example, a second (passive) lever voltage having a voltage value of about 0.3 V may be applied to an inactive lever line corresponding to a non-selected memory cell.

[0144] According to various aspects, a memory cell arrangement (eg, as referred to herein) Figure 4A The 1T2C memory cells of the memory cell arrangement 200 described above may be organized as an array based on a NAND architecture (eg, the memory cells in the plurality of memory cells may be in a NAND configuration), such as Figure 4E and Figure 4F shown.

[0145] In a NAND configuration, field effect transistor structures associated with memory cells sharing a corresponding word line (e.g., WL(1), e.g., WL(2)) may be connected in series. For example, a first region and a second region of the field effect transistor structure may be connected in series. For example, two corresponding adjacent memory cells are connected from a first region to a second region. For example, two corresponding adjacent memory cells may have a shared first / second region, which includes a first region of a field effect transistor structure and a second region of another field effect transistor structure. Illustratively, the first region and the second region of the series connection of the field effect transistor structure may form a bit line. The memory cell arrangement may include one or more third control nodes. Each of the one or more third control nodes may be connected to a first region of each field effect transistor structure of the series connected field effect transistor structure. The memory cell arrangement may include one or more fourth control nodes. Each of the one or more fourth control nodes may be connected to a second region of each field effect transistor structure of the series connected field effect transistor structure.

[0146] Figure 4E The writing of a memory cell (1) of a memory cell arrangement 400 according to various aspects is shown by way of example. The memory cell arrangement 400 may be configured in the same or similar manner as described herein with reference to the memory cell arrangement 200, see Figure 4A. Each memory cell 402 of the memory cell arrangement 400 may include a lever capacitor LE, a ferroelectric capacitor FE, and a field effect transistor FT. The lever capacitor LE of the corresponding memory cell 402 may be connected to the corresponding lever line LL(1), LL(2) and the floating gate of the field effect transistor FT of the corresponding memory cell 402. The ferroelectric capacitor FE of the corresponding memory cell 402 may be connected to the corresponding word line WL(1), WL(2) and the floating gate of the field effect transistor FT of the corresponding memory cell 402. The field effect transistor structures associated with the memory cells sharing the corresponding word line WL(1), WL(2)) may be connected in series. Illustratively, the series connection of the memory cells may form a corresponding control line. For example, the voltage applied to the control line may be applied to the common drain D connection of the memory cell corresponding to the control line. For example, the voltage applied to the control line may be applied to the common source S connection of the memory cell corresponding to the control line. According to various aspects, a bit line voltage may be applied to a common drain D connection of the memory cells corresponding to a control line (e.g., third terminals BL(1), BL(2) of the memory cell arrangement 400), and a source line voltage may be applied to a common source S connection of the memory cells corresponding to a control line (e.g., fourth terminals SL(1), SL(2) of the memory cell arrangement 400). According to various aspects, each third terminal may be connected to a corresponding bit line (e.g., BL(1), BL(2)). According to various aspects, each fourth terminal may be connected to a corresponding source line (e.g., SL(1), SL(2)).

[0147] In this example, it can be assumed that only the memory cell (1) of the memory cell arrangement 400 is intended to be written (selected to be written, for example, referred to as a selected memory cell). To program or erase the memory cell (1), a write voltage V PP is applied to the active word line connected to the ferroelectric capacitor FE of the selected memory cell (1). In this case, the voltage (V FE，ACT ) can be the write voltage V PP (Also called programming voltage V PP ). In addition, in order to program or erase the memory cell (1), the base voltage (e.g., V SS ) or a voltage close to the base voltage is applied to the active lever line connected to the lever capacitor LE of the selected memory cell (1). In this case, the voltage (V LE，ACT ) may be, for example, a base voltage (e.g., 0 V) ​​or a voltage close to the base voltage (e.g., a voltage in the range of about -0.25 V to about 0.25 V). However, a voltage greater than the base voltage (e.g., in the range of about V SS To about VPP / 2) is applied to the active lever line connected to the lever capacitor LE of the selected memory cell (1). In addition, in order to program or erase the memory cell (1), the base voltage (e.g., V SS ) or a voltage close to the base voltage is applied to the active bit line of the field effect transistor FT connected to the selected memory cell (1). In this case, the voltage (V BL，ACT ) may be, for example, a base voltage (e.g., 0 V) ​​or a voltage close to the base voltage (e.g., a voltage in a range of about -0.25 V to about 0.25 V). For example, the voltage (V BL，ACT ) can be applied to the third terminal. In addition, in order to program or erase the memory cell (1), the base voltage (e.g., V SS ) or a voltage close to the base voltage is applied to the active source line of the field effect transistor FT connected to the selected memory cell (1). In this case, the voltage applied to the corresponding source line (SL(1)) may be, for example, the base voltage (e.g., 0 V) ​​or a voltage close to the base voltage (e.g., a voltage in the range of about -0.25 V to about 0.25 V). For example, the voltage applied to the corresponding source line (SL(1)) may be applied to the fourth terminal.

[0148] According to various aspects, the field effect transistor structure can be in a non-conductive state during writing to a selected memory cell. Illustratively, the field effect transistor structure can be closed during writing to a selected memory cell. This can, for example, increase the speed of writing to the selected memory cell (e.g., to a write time of less than 15 ns, such as a write time of less than 10 ns).

[0149] According to various aspects, the write voltage V PP It may be in the range of, for example, about 1V to about 10V, such as about 1.5V to about 6V.

[0150] According to various aspects, the write voltage V PP The voltage value and the voltage applied to the corresponding lever line (V LE，ACT The voltage value of the write voltage (V PP ) may have a positive voltage value, and the first (active) lever voltage (V LE，ACT ) may have a negative voltage value, and vice versa. According to an example, the write voltage V PP may have a voltage value of +1.0V, and the first lever voltage V LE，ACT May have a voltage value of -1.0V.

[0151] According to various aspects, disturbance of other memory cells 402 of the memory cell arrangement 400 can be prevented during writing to the selected memory cell (1).

[0152] For example, to avoid disturbing memory cell (2) of memory cell arrangement 400 during writing to memory cell (1), a voltage different from V SS A voltage of V is applied to the passive lever line connected to the lever capacitor LE of the non-selected memory cell (2). Different from V SS A voltage of V may be applied to all passive lever lines connected to the lever capacitors LE of non-selected memory cells of the memory cell arrangement 400 that share the same word line (WL(1)) as the selected memory cell (1). According to various aspects, a voltage (V LE，PAS ) may be, for example, between about 1 / 2*|V PP | to about |V PP | within the range.

[0153] According to various aspects, the first lever voltage (V LE，ACT ) and the voltage (V LE，PAS The voltage value of the first (active) lever voltage (V LE，ACT ) may have a negative voltage value, and the second (passive) lever voltage (V LE，PAS ) may have a positive voltage value, and vice versa. According to an example, the first lever voltage V LE，ACT may have a voltage value of -1.0V, and the second lever voltage V LE，PAS The second lever voltage V LE，PAS The arrangement 400 may be selected so that the field effect transistor structures of the non-selected memory cells are in an inverted state.

[0154] According to various aspects, applying a first lever voltage (V LE，ACT ) and / or with the write voltage (V PP ) compared to the second (passive) lever voltage of opposite sign (V LE，PAS ) ensures that the memory state of unselected memory cells is not changed (eg, neither written nor erased).

[0155] According to various aspects, in a NAND configuration of multiple memory cells, each field effect transistor structure of the multiple memory cells can be configured such that (e.g., via implantation of a channel of the corresponding field effect transistor structure) the LVT state of the corresponding memory cell corresponds to a normally-on state of the field effect transistor structure.

[0156] For example, in order to avoid disturbing memory cells (3) and (4) of the memory cell arrangement 400 during writing to the memory cell (1), different voltages from V PP A voltage of is applied to the ferroelectric capacitor FE passive word line connected to the non-selected memory cells (3) and (4). Different from V PP A voltage of V may be applied to all passive word lines connected to the ferroelectric capacitors FE of non-selected memory cells of the memory cell arrangement 400 that do not share the same word line (WL(1)) as the selected memory cell (1). According to various aspects, a voltage (V FE，PAS ) may be, for example, between about 0 V (or V SS ) to about 1 / 2*|V PP | within the range.

[0157] According to various aspects, the write voltage (V PP ) and the voltage (V FE，PAS The voltage value of the write voltage (V PP ) can have positive voltage values ​​and the inhibit voltage (V FE，PAS ) may have a negative voltage value, and vice versa. According to an example, the write voltage V PP can have a voltage value of +1.0V and prohibits the voltage V FE，PAS Can have a voltage value of -0.2V.

[0158] Furthermore, in order to avoid disturbing the memory cells (3), (4) of the memory cell arrangement 400 during writing to the memory cell (1), the base voltage (e.g., V SS ) or a voltage close to the base voltage may be applied to the inactive bit lines of the field effect transistors FT connected to the non-selected memory cells (3), (4). In this case, the voltage (V BL，PAS ) may be, for example, 0 V or a voltage close to 0 V (eg, a voltage in a range of about -0.25 V to about 0.25 V). For example, the voltage (V BL，ACT ) may be applied to a third terminal corresponding to the bit line (BL(2)).

[0159] Furthermore, in order to avoid disturbing the memory cells (3), (4) of the memory cell arrangement 400 during writing to the memory cell (1), the base voltage (e.g., V SS ) or a voltage close to the base voltage may be applied to the inactive source line of the field effect transistor FT connected to the non-selected memory cells (3), (4). In this case, the voltage applied to the corresponding source line (SL(2)) may be, for example, 0 V or a voltage close to 0 V (for example, a voltage in the range of about -0.25 V to about 0.25 V). For example, the voltage applied to the corresponding source line (SL(2)) may be applied to the fourth terminal corresponding to the source line (SL(2)).

[0160] As exemplarily described above, individual cells of the erasable memory cell arrangement 400 may be erasable. It should be noted that some or all of the described voltages are merely examples and that deviations from the described voltages are possible.

[0161] As further described above by way of example, the terminal of the memory cell 402 connected to the bit line (eg, connected to the source / drain region of the field effect transistor of the memory cell 402) may be held at V SS (or at least close to V SS ), thereby eliminating the power consumption from reverse junction leakage from the body to the source and drain during the inhibit period.

[0162] According to various aspects, memory cells of the memory cell arrangement 400 may be read. To increase the reading speed, more than one memory cell of the memory cell arrangement 400 may be read substantially simultaneously. In the following example, reading two memory cells (1), (4) of the memory cell arrangement 400 is described. Note that reading a single memory cell of the memory cell arrangement 400 may be performed in a similar manner.

[0163] Figure 4F The reading of memory cells (1) and (4) of the memory cell arrangement 400 according to various aspects is shown by way of example. In this example, it can be assumed that two corresponding memory cells (1) and (4) of the memory cell arrangement 400 in a NAND configuration are intended to be read (selected to be read, referred to as selected memory cells). In order to read the memory cells (1) and (4), a read voltage V G is applied to the active word line of the ferroelectric capacitor FE connected to the selected memory cell (1), (4). In this case, the voltage (V FE，ACT ) can be the read voltage V G .

[0164] In addition, in order to read the memory cells (1) and (4), the voltage (V LE，ACT ) is applied to the active lever line of the lever capacitor LE connected to the selected memory cell (1), (4). In this case, the voltage (V LE，ACT ) can be substantially equal to the read voltage V G .

[0165] Furthermore, in order to read the memory cells (1) and (4), a voltage greater than V may be applied to the active bit line of the field effect transistor FT connected to the selected memory cell (1) and (4). SS In this case, the voltage (V BL，ACT ) may be, for example, greater than 0 V. In an example, the voltage (V BL，ACT ) may be 1 V. For example, the voltage (V BLACT ) may be applied to the third terminal corresponding to the corresponding bit line (BL(1), BL(2)).

[0166] In addition, in order to read the memory cells (1) and (4), a voltage greater than V SS A potential / voltage is applied to the active source line of the field effect transistor FT connected to the selected memory cell (1), (4). In this case, the voltage applied to the corresponding source line (SL(1), SL(2)) may be, for example, substantially equal to 0V. In an example, the voltage applied to the corresponding source line (SL(1), SL(2)) may be 0V. For example, the voltage applied to the corresponding source line (SL(1), SL(2)) may be applied to a fourth terminal corresponding to the corresponding source line (SL(1), SL(2)). Reading the selected memory cell (1), (4) may include providing a voltage to a third terminal and a fourth terminal so that each field effect transistor structure associated with other memory cells in the corresponding first subset of memory cells including the selected memory cell is in a conductive state. For example, a voltage may be applied to the third terminal and the fourth terminal so that each field effect transistor structure connected in series with the selected memory cell (1), (4) is in a conductive state. The body terminal and the source terminal of the field effect transistor of the memory cell may be maintained at or near V SS A voltage (e.g., 0 V or a voltage in a range between about -0.25 V to about 0.25 V).

[0167] According to the example, the voltage V is read G may have a voltage value of 0.7V, and the voltage (V LE，ACT) can have a voltage value of 0.5V.

[0168] According to various aspects, the voltage V G The voltage value and the voltage applied to the corresponding lever line (V LE，ACT The voltage value of the read voltage (V G ) may have a positive voltage value, and the first (active) lever voltage (V LE，ACT ) can have negative voltage values ​​and vice versa.

[0169] According to various aspects, disturbance of other memory cells 402 of the memory cell arrangement 400 can be prevented during reading of the selected memory cell (1), (4).

[0170] For example, to avoid disturbing the memory cell (2) of the memory cell arrangement 400 during the reading of the memory cells (1) and (4), a voltage different from V G A voltage of V is applied to the passive lever line connected to the lever capacitor LE of the non-selected memory cell (2). Different from V G A voltage of V may be applied to all passive lever lines connected to the lever capacitors LE of non-selected memory cells of the memory cell arrangement 400 that share the same word line (WL(1), WL(2)) as the selected memory cells (1), (4). According to various aspects, the voltage (V LE，PAS ) may be, for example, between about V SS (e.g., 0V) to about 1 / 2*|V G | is within the range of. According to an example, the first lever voltage V LE，ACT can be +0.5V, and the second lever voltage V LE，PAS It can be 1.0V.

[0171] According to various aspects, the first lever voltage (V LE，ACT ) and the voltage (V LE，PAS The voltage value of the first (active) lever voltage (V LE，ACT ) may have a positive voltage value, and the second (passive) lever voltage (V LE，PAS ) may have a negative voltage value, and vice versa. According to various aspects, applying the first lever voltage (V LE，ACT ) and / or with the read voltage (V G ) compared to the second (passive) lever voltage of opposite sign (V LE，PAS) ensures that the memory state of unselected memory cells is not changed (eg, neither written nor erased).

[0172] As an example, the memory cell arrangement 400 may include additional memory cells, and in order to avoid disturbing one or more additional memory cells of the memory cell arrangement 400 during reading of the memory cells (1), (4), different from V G A voltage of V may be applied to the passive word line connected to the ferroelectric capacitor FE of the non-selected memory cell. G A voltage of V may be applied to all passive word lines connected to the ferroelectric capacitors FE of the non-selected memory cells of the memory cell arrangement 400 that do not share the same word line (WL(1), WL(2)) as the selected memory cells (1), (4). According to various aspects, the voltage (V FE，PAS ) may be, for example, between about V SS (e.g., 0V) to about 1 / 2*|V G | within the range.

[0173] According to various aspects, the read voltage (V G ) and the voltage (V FE，PAS The voltage value of the read voltage (V G ) can have positive voltage values ​​and the inhibit voltage (V FE，PAS ) can have negative voltage values ​​and vice versa.

[0174] Furthermore, in order to prevent one or more additional memory cells of the memory cell arrangement 400 from being disturbed during the reading of the memory cells (1) and (4), the base voltage (e.g., V SS ) or a voltage close to the base voltage may be applied to the inactive bit lines of the field effect transistors FT connected to the non-selected memory cells. A voltage equal to or close to the base voltage may be applied to all inactive bit lines and source lines of the field effect transistors connected to the non-selected memory cells of the memory cell arrangement 400 that do not share the same word line (WL(1), WL(2)) as the selected memory cells (1), (4). In this case, the voltage (V BL，PAS ) may be, for example, a voltage of 0 V or close to 0 V (eg, a voltage in a range of -0.25 V to about 0.25 V).

[0175] As described above by way of example, individual NAND cell pairs of the memory cell arrangement 400 may be read. It should be noted that some or all of the voltages described are merely examples, and deviations from the described voltages are possible. According to various aspects, the body terminal and source terminal of the transistor of the memory cell 402 (including semiconductor material) may be maintained at V SS , but the effective bit line potential can be charged to a level greater than V SS The potential of the ferroelectric capacitor FE is used to detect the charge generated by the ferroelectric capacitor FE. According to various aspects, the memory cell described herein includes or consists of a transistor and two capacitors, one of which is a ferroelectric capacitor. By increasing the capacitance of a capacitor that does not exhibit a ferroelectric charge (e.g., a lever capacitor), a programming voltage close to the programming voltage of an independent ferroelectric capacitor can be obtained. During reading, the voltage distribution can be changed (compared to writing), so that interference with the ferroelectric material in the ferroelectric capacitor can be avoided, and good control of the transistor (e.g., a MOS transistor) can be obtained. During the hold condition, the voltage across the ferroelectric material can be reduced to avoid depolarization of the ferroelectric portion.

[0176] According to various aspects, a NAND architecture is described herein to organize 1T2C memory cells into an array structure to construct a memory array. By coordinating the voltages applied to the two capacitors, interference during the read and write processes can be effectively reduced. For write inhibition, junction leakage can be avoided because all semiconductor terminals can be kept grounded. This structure allows bit variability of long channel transistors. According to various aspects, if necessary, another memory element can be used instead of a ferroelectric capacitor. According to various aspects, if necessary, another transistor can be used instead of a field effect transistor. According to various aspects, the lever capacitor (or the second capacitor structure) can be configured so that it has a capacitance in the range of about 0.01fF to about 100fF, 0.1fF to about 10fF. However, the capacitance of the lever capacitor can be adapted to other elements of the memory cell as needed.

[0177] Figure 4J An example configuration of a memory cell arrangement 410 including six memory cells 402 having a NAND configuration is shown. The memory cells 402 of the memory cell arrangement 410 may be as described with reference to Figure 4E The memory cell 402 of the memory cell arrangement 410 may be written as described with reference to Figure 4FIn an example, to read a selected memory cell, a read voltage having a voltage value of about 1.7 V may be applied to a word line (WL) corresponding to the selected memory cell, and a first (active) lever voltage having a voltage value of about 1.3 V may be applied to a lever line (LL) corresponding to the selected memory cell. For example, a second (passive) lever voltage having a voltage value of about 2.0 V may be applied to an inactive lever line corresponding to a non-selected memory cell.

[0178] According to various aspects, both capacitors of the 1T2C memory cell may be memory capacitors (also referred to as memory capacitor structures in some aspects). Both memory capacitor structures may include a spontaneously polarized material as a dielectric material. In the following, the memory capacitor structure is described as a ferroelectric capacitor (e.g., including a ferroelectric material as a spontaneously polarized material). The two ferroelectric capacitors may be configured to store a charge representing actual information of the memory cell (e.g., representing a logical "0" or a logical "1"). Therefore, each memory cell may be configured to store two bits. In the following, a memory cell configured to store more than one bit may also be referred to as a multi-bit memory cell.

[0179] According to various aspects, multi-bit memory cells may be organized into an array based on a NOR architecture, such as Figure 4G As shown, or organized as an array based on NAND architecture, such as Figure 4H shown.

[0180] Figure 4G A memory cell arrangement 500 having a NOR architecture and including a multi-bit memory cell 502 according to various aspects is schematically shown. Each memory cell 502 of the memory cell arrangement 500 may include a first ferroelectric capacitor FE(A), a second ferroelectric capacitor FE(B), and a field effect transistor FT. The first ferroelectric capacitor FE(A) of the respective memory cell 502 may be connected to the corresponding word line WL(1A), WL(2A) and the floating gate of the field effect transistor FT of the respective memory cell 502. The second ferroelectric capacitor FE(B) of the respective memory cell 502 may be connected to the corresponding word line WL(1B), WL(2B) and the floating gate of the field effect transistor FT of the respective memory cell 502. The field effect transistor FT may be connected with its source S to a common source potential and with its drain D to the corresponding bit line BL(1), BL(2).

[0181] According to various aspects, a ferroelectric capacitor (e.g., a first ferroelectric capacitor FE(A), for example, a second ferroelectric capacitor FE(B)) can be written. In this example, it can be assumed that only one ferroelectric capacitor (e.g., a first ferroelectric capacitor FE(A) or a second ferroelectric capacitor FE(B)) of a memory cell (1) of the memory cell arrangement 500 is intended to be written (selected to be written, for example, referred to as a selected ferroelectric capacitor of a selected memory cell, also referred to as a selected ferroelectric capacitor in some aspects). In order to program or erase the first ferroelectric capacitor FE(A) of the memory cell (1), a write voltage V PP is applied to the active word line connected to the selected ferroelectric capacitor FE(A) of the selected memory cell (1). In this case, the voltage (V FE，ACT ) can be the write voltage V PP (Also called programming voltage V PP To program or erase a selected ferroelectric capacitor FE(A), the base voltage (e.g., V SS ) or a voltage close to the base voltage is applied to the active bit line of the field effect transistor FT connected to the selected ferroelectric capacitor FE(A) of the memory cell (1). In this case, the voltage (V BL，ACT ) may be, for example, a base voltage (eg, 0 V) ​​or a voltage close to the base voltage (eg, a voltage in a range of approximately -0.25 V to approximately 0.25 V).

[0182] According to various aspects, the field effect transistor structure can be in a non-conductive state during writing of the selected ferroelectric capacitor FE(A) of the selected memory cell. Illustratively, the field effect transistor structure can be closed during writing of the selected ferroelectric capacitor FE(A) of the selected memory cell. This can, for example, increase the speed of writing to the selected ferroelectric capacitor FE(A) of the selected memory cell (e.g., with a writing time of less than 15 ns, such as with a writing time of less than 10 ns). According to various aspects, the write voltage V PP It may be in the range of, for example, about 1V to about 10V, such as about 1.5V to about 6V.

[0183] According to various aspects, interference with other ferroelectric capacitors FE(B) of a selected memory cell (1) can be prevented during writing of a selected ferroelectric capacitor FE(A) of a selected memory cell (1). For example, in order to avoid interference with a second ferroelectric capacitor FE(B) during writing of a selected first ferroelectric capacitor FE(A) of a selected memory cell (1), a voltage different from V PPA voltage (V ) is applied to an inactive word line connected to a selected memory cell (1). According to various aspects, a voltage (V ) applied to a corresponding word line (WL(1B)) FE(B)，PAS ) may be, for example, between about 0 V (or V SS ) to about 1 / 2*|V PP | within the range.

[0184] According to various aspects, the write voltage (V PP ) and the voltage (V FE(B)，PAS The voltage value of the write voltage (V PP ) may have a positive voltage value, and the first prohibition voltage (V FE(B)，PAS ) can have negative voltage values ​​and vice versa.

[0185] According to various aspects, disturbances to other memory cells 502 of the memory cell arrangement 500 may be prevented during writing to a selected ferroelectric capacitor FE(A) of a selected memory cell (1).

[0186] For example, in order to avoid disturbing the memory cells (3), (4) (hereinafter also referred to as the selected ferroelectric capacitor FE (A, 1)) of the memory cell arrangement 500 during writing of the selected ferroelectric capacitor FE (A) of the selected memory cell (1), the ferroelectric capacitors different from V PP A voltage of V is applied to the passive word line connected to the ferroelectric capacitor FE of the non-selected memory cells (3) and (4). PP A voltage of V may be applied to all passive word lines connected to ferroelectric capacitors FE of non-selected memory cells of the memory cell arrangement 500 that do not share the same word line (WL(1A), WL(1B)) as the selected memory cell (1). According to various aspects, a voltage (V FE，PAS ) may be, for example, between about 0 V (or V SS ) to about 1 / 2*|V PP | within the range.

[0187] According to various aspects, the write voltage (V PP ) and the voltage (V FE，PAS The voltage value of the write voltage (V PP ) may have a positive voltage value, and the second prohibition voltage (V FE，PAS) may have a negative voltage value, and vice versa. According to an example, the write voltage V PP may have a voltage value of +1.0V, and the second prohibition voltage V FE，PAS Can have a voltage value of -0.2V.

[0188] Furthermore, in order to avoid disturbing the memory cells (3), (4) of the memory cell arrangement 500 during writing to the selected ferroelectric capacitor FE(A,1), the base voltage (e.g., V SS ) or a voltage close to the base voltage is applied to the inactive bit line of the field effect transistor FT connected to the non-selected memory cells (3) and (4). In this case, the voltage (V BL，PAS ) may be, for example, a voltage of 0 V or close to 0 V (eg, a voltage in a range of approximately -0.25 V to approximately 0.25 V).

[0189] As exemplarily described above, individual cells of the memory cell arrangement 500 may be erased. It should be noted that some or all of the described voltages are merely examples and deviations from the described voltages are possible.

[0190] As further exemplarily described above, the terminal of the memory cell 502 connected to the bit line (eg, connected to the source / drain region of the field effect transistor of the memory cell 502) may be held at V SS (or at least close to V SS ), thereby eliminating the power consumption from reverse junction leakage from the body to the source and drain during the inhibit period.

[0191] According to various aspects, a ferroelectric capacitor (e.g., a first ferroelectric capacitor FE(A), for example, a second ferroelectric capacitor FE(B)) can be read. In this example, it can be assumed that only one ferroelectric capacitor (e.g., the first ferroelectric capacitor FE(A) or the second ferroelectric capacitor FE(B)) of a selected memory cell (1) of the memory cell arrangement 500 is intended to be read (selected to be read, referred to as a selected ferroelectric capacitor of the selected memory cell, also referred to as a selected ferroelectric capacitor in some aspects). In order to read the selected ferroelectric capacitor FE(A) of the memory cell (1), a read voltage V G is applied to the active word line of the selected ferroelectric capacitor FE(A) (hereinafter also referred to as the selected ferroelectric capacitor FE(A, 1)) connected to the selected memory cell (1). In this case, the voltage (V FE，ACT ) can be the read voltage V G .

[0192] In addition, in order to read the selected ferroelectric capacitor FE(A,1), a voltage greater than VSS The potential / voltage is applied to the active bit line of the field effect transistor FT connected to the selected memory cell (1). In this case, the voltage (V BL，ACT ) may be, for example, greater than 0 V. In an example, the voltage (V BL，ACT ) can be 1V.

[0193] The body and source terminals of the field effect transistor of the memory cell can be maintained at or near V SS A voltage (e.g., 0 V or a voltage in a range between about -0.25 V to about 0.25 V).

[0194] According to various aspects, interference with other ferroelectric capacitors FE(B) of a selected memory cell (1) can be prevented during reading of a selected ferroelectric capacitor FE(A) of a selected memory cell (1). For example, in order to avoid interference with a second ferroelectric capacitor FE(B) during reading of a selected first ferroelectric capacitor FE(A) of a selected memory cell (1), a capacitor different from V G A voltage (V ) is applied to an inactive word line connected to a selected memory cell (1). According to various aspects, a voltage (V ) applied to a corresponding word line (WL(1B)) FE(B)，PAS ) may be, for example, between about 0 V (or V SS ) to about 1 / 2*|V PP | within the range.

[0195] According to various aspects, the read voltage (V G ) and the voltage (V FE(B)，PAS The voltage value of the read voltage (V G ) may have a positive voltage value, and the first prohibition voltage (V FE(B)，PAS ) can have negative voltage values ​​and vice versa.

[0196] According to various aspects, disturbance of other memory cells 502 of the memory cell arrangement 500 can be prevented during reading of a selected ferroelectric capacitor FE(A) of a selected memory cell (1).

[0197] For example, in order to avoid disturbing the memory cells (3), (4) of the memory cell arrangement 500 during reading of the selected ferroelectric capacitor FE(A, 1), different ferroelectric capacitors may be used. G A voltage of V is applied to the passive word line connected to the ferroelectric capacitor FE of the non-selected memory cells (3) and (4). GA voltage of V may be applied to all passive word lines connected to ferroelectric capacitors FE of non-selected memory cells of the memory cell arrangement 500 that do not share the same word line (WL(1A), WL(1B)) as the selected memory cell (1). According to various aspects, a voltage (V FE，PAS ) may be, for example, between about V SS (e.g., 0V) to about 1 / 2*|V G | within the range.

[0198] According to various aspects, the read voltage (V G ) and the voltage (V FE，PAS The voltage value of the read voltage (V G ) may have a positive voltage value, and the second prohibition voltage (V FE，PAS ) can have negative voltage values ​​and vice versa.

[0199] Furthermore, in order to avoid disturbing the memory cells (3), (4) of the memory cell arrangement 500 during reading of the selected ferroelectric capacitor FE(A, 1), the base voltage (e.g., V SS ) or a voltage close to the base voltage is applied to the inactive bit lines of the field effect transistors FT connected to the non-selected memory cells (3), (4). A voltage equal to or close to the base voltage may be applied to all inactive bit lines of the field effect transistors connected to the non-selected memory cells of the memory cell arrangement 500 that do not share the same bit line (BL(1)) as the selected memory cell (1). In this case, the voltage (V BL，PAS ) may be, for example, a voltage of 0 V or close to 0 V (eg, a voltage in a range of approximately -0.25 V to approximately 0.25 V).

[0200] As described above, individual cells of the memory cell arrangement 500 may be read. It should be noted that some or all of the described voltages are merely examples, and deviations from the described voltages are possible.

[0201] According to various aspects, the body and source terminals of the transistors of memory cell 502 (including semiconductor material) can be held at V SS , but the effective bit line potential can be charged to a level greater than V SS to detect the charge generated by the ferroelectric capacitor FE.

[0202] According to various aspects, a NOR architecture is described herein to organize 1T2C memory cells into an array structure to construct a memory array. By coordinating the voltages applied to the two capacitors, interference during read and write processes can be effectively reduced. For write inhibition, junction leakage can be avoided because all semiconductor terminals can be kept grounded. The structure allows bit variability of long channel transistors. According to various aspects, if necessary, another memory element can be used instead of a ferroelectric capacitor. According to various aspects, if necessary, another transistor can be used instead of a field effect transistor.

[0203] Figure 4H A memory cell arrangement 600 having a NAND architecture and including a multi-bit memory cell 602 according to various aspects is schematically shown. Each memory cell 602 of the memory cell arrangement 600 may include a first ferroelectric capacitor FE(A), a second ferroelectric capacitor FE(B), and a field effect transistor FT. The first ferroelectric capacitor FE(A) of the corresponding memory cell 602 may be connected to a corresponding word line WL(1A), WL(2A) and a floating gate of the field effect transistor FT of the corresponding memory cell 602. The second ferroelectric capacitor FE(B) of the corresponding memory cell 602 may be connected to a corresponding word line WL(1B), WL(2B) and a floating gate of the field effect transistor FT of the corresponding memory cell 602.

[0204] According to various aspects, a ferroelectric capacitor (e.g., a first ferroelectric capacitor FE(A), for example, a second ferroelectric capacitor FE(B)) can be written. In this example, it can be assumed that only one ferroelectric capacitor (e.g., the first ferroelectric capacitor FE(A) or the second ferroelectric capacitor FE(B)) of a memory cell (1) of the memory cell arrangement 600 is intended to be written (selected to be written, for example, referred to as a selected ferroelectric capacitor of a selected memory cell, also referred to as a selected ferroelectric capacitor in some aspects). In order to program or erase the first ferroelectric capacitor FE(A) of the memory cell (1), a write voltage V PP is applied to the active word line connected to the selected ferroelectric capacitor FE(A) of the selected memory cell (1). In this case, the voltage (V FE，ACT ) can be the write voltage V PP (Also called programming voltage V PP To program or erase a selected ferroelectric capacitor FE(A), the base voltage (e.g., V SS ) or a voltage close to the base voltage is applied to the active bit line of the field effect transistor FT connected to the selected ferroelectric capacitor FE(A) of the memory cell (1). In this case, the voltage (V BL，ACT) may be, for example, a base voltage (e.g., 0 V) ​​or a voltage close to the base voltage (e.g., a voltage in a range of about -0.25 V to about 0.25 V). For example, the voltage (V BL，ACT ) can be applied to the third terminal corresponding to the bit line (BL(1)). To program or erase the selected ferroelectric capacitor FE(A), the base voltage (e.g., V SS ) or a voltage close to the base voltage is applied to the active source line of the field effect transistor FT connected to the selected ferroelectric capacitor FE(A) of the memory cell (1). In this case, the voltage applied to the corresponding source line (SL(1)) may be, for example, the base voltage (e.g., 0 V) ​​or a voltage close to the base voltage (e.g., a voltage in the range of about -0.25 V to about 0.25 V). For example, the voltage applied to the corresponding source line (SL(1)) may be applied to the fourth terminal corresponding to the source line (SL(1)).

[0205] According to various aspects, the field effect transistor structure can be in a non-conductive state during writing to a selected memory cell. Illustratively, the field effect transistor structure can be closed during writing to a selected memory cell. This can, for example, increase the speed of writing to the selected memory cell (e.g., to a write time of less than 15 ns, such as a write time of less than 10 ns).

[0206] According to various aspects, the write voltage V PP It may be in the range of, for example, about 1V to about 10V, such as about 1.5V to about 6V.

[0207] According to various aspects, interference with other ferroelectric capacitors FE(B) of a selected memory cell (1) can be prevented during writing of a selected ferroelectric capacitor FE(A) of a selected memory cell (1). For example, in order to avoid interference with a second ferroelectric capacitor FE(B) during writing of a selected first ferroelectric capacitor FE(A) of a selected memory cell (1), a ferroelectric capacitor different from V PP A voltage (V ) is applied to an inactive word line connected to a selected memory cell (1). According to various aspects, a voltage (V ) applied to a corresponding word line (WL(1B)) FE(B)，PAS ) may be, for example, between about 0 V (or V SS ) to about 1 / 2*|V PP | within the range.

[0208] According to various aspects, the write voltage (V PP ) and the voltage (V FE(B)，PASThe voltage value of the write voltage (V PP ) may have a positive voltage value, and the first prohibition voltage (V FE(B)，PAS ) can have negative voltage values ​​and vice versa.

[0209] According to various aspects, disturbance of other memory cells 602 of the memory cell arrangement 600 can be prevented during writing to the selected memory cell (1).

[0210] For example, in order to avoid disturbing the memory cells (3), (4) (hereinafter also referred to as the selected ferroelectric capacitor FE (A, 1)) of the memory cell arrangement 600 during writing of the selected ferroelectric capacitor FE (A) of the selected memory cell (1), the ferroelectric capacitors different from V PP A voltage of V is applied to the passive word line connected to the ferroelectric capacitor FE of the non-selected memory cells (3) and (4). PP A voltage of V may be applied to all passive word lines connected to ferroelectric capacitors FE of non-selected memory cells of the memory cell arrangement 600 that do not share the same word line (WL(1A), WL(1B)) as the selected memory cell (1). According to various aspects, a voltage (V FE，PAS ) may be, for example, between about 0 V (or V SS ) to about 1 / 2*|V PP | within the range.

[0211] According to various aspects, the write voltage (V PP ) and the voltage (V FE，PAS The voltage value of the write voltage (V PP ) may have a positive voltage value, and the second prohibition voltage (V FE，PAS ) may have a negative voltage value, and vice versa. According to an example, the write voltage V PP can have a voltage value of +1.0V and prohibits the voltage V FE，PAS Can have a voltage value of -0.2V.

[0212] Furthermore, in order to avoid disturbing the memory cells (3), (4) of the memory cell arrangement 600 during writing to the selected ferroelectric capacitor FE(A,1), the base voltage (e.g., V SS) or a voltage close to the base voltage is applied to the inactive bit line of the field effect transistor FT connected to the non-selected memory cells (3) and (4). In this case, the voltage (V BL，PAS ) may be, for example, 0 V or a voltage close to 0 V (eg, a voltage in a range of about -0.25 V to about 0.25 V). For example, the voltage (V BL，ACT ) may be applied to the third terminal corresponding to the bit line (BL(1)). In addition, in order to avoid disturbing the memory cells (3), (4) of the memory cell arrangement 600 during writing to the selected ferroelectric capacitor FE(A,1), the base voltage (e.g., V SS ) or a voltage close to the base voltage is applied to the inactive source line of the field effect transistor FT connected to the non-selected memory cells (3), (4). In this case, the voltage applied to the corresponding source line (SL(2)) may be, for example, 0 V or a voltage close to 0 V (for example, a voltage in the range of about -0.25 V to about 0.25 V). For example, the voltage applied to the corresponding source line (SL(1)) may be applied to the fourth terminal corresponding to the source line (SL(1)).

[0213] As exemplarily described above, individual cells of the memory cell arrangement 600 may be erased. It should be noted that some or all of the described voltages are merely examples and deviations from the described voltages are possible.

[0214] As described exemplarily further above, the terminal of the memory cell 602 connected to the bit line (eg, connected to the source / drain region of the field effect transistor of the memory cell 602) may be held at V SS (or at least close to V SS ), thereby eliminating the power consumption from reverse junction leakage from the body to the source and drain during the inhibit period.

[0215] According to various aspects, a selected ferroelectric capacitor FE(A) of a selected memory cell (1) of the memory cell arrangement 600 can be read out.

[0216] To increase the reading speed, more than one memory cell of the memory cell arrangement 600 may be read substantially simultaneously. In the following example, reading two memory cells (1), (4) of the memory cell arrangement 600 is described. It should be noted that reading a single memory cell of the memory cell arrangement 600 may be performed in a similar manner.

[0217] In this example, it can be assumed that two selected ferroelectric capacitors FE(A) of corresponding memory cells (1) and (4) of the memory cell arrangement 600 of the NAND configuration are intended to be read (selected to be read, referred to as selected ferroelectric capacitors as selected memory cells). In order to read the memory cells (1), (4), the read voltage V G is applied to the active word line connected to the selected ferroelectric capacitor FE(A) of the selected memory cell (1), (4). In this case, the voltage (V FE，ACT ) can be the read voltage V G .

[0218] Furthermore, in order to read the memory cells (1) and (4), a voltage greater than V may be applied to the active bit line of the field effect transistor FT connected to the selected memory cell (1) and (4). SS In this case, the voltage (V BL，ACT ) may be, for example, greater than 0 V. In an example, the voltage (V BL，ACT )) may be 1V. In addition, in order to read the memory cells (1), (4), a potential / voltage may be applied to the active source line of the field effect transistor FT connected to the selected memory cell (1), (4). In this case, the voltage applied to the corresponding source line (SL(1), SL(2)) may be, for example, equal to 0V. Reading the selected memory cell (1), (4) may include providing a voltage to the third terminal and the fourth terminal so that each field effect transistor structure associated with other memory cells in the corresponding first subset of memory cells including the selected memory cell is in a conductive state. For example, a voltage may be applied to the third terminal and the fourth terminal so that each field effect transistor structure connected in series with the selected memory cell (1), (4) is in a conductive state. The body terminal and the source terminal of the field effect transistor of the memory cell may be maintained at or close to V SS A voltage (e.g., 0 V or a voltage in a range between about -0.25 V to about 0.25 V).

[0219] According to various aspects, during writing of a selected ferroelectric capacitor FE(A) of a selected memory cell (1), (4), interference with other ferroelectric capacitors FE(B) of the selected memory cell (1), (4) can be prevented. For example, in order to avoid interference with a second ferroelectric capacitor FE(B) of the selected memory cell (1), (4) during writing of a selected first ferroelectric capacitor FE(A) of the selected memory cell (1), (4), a capacitor different from V PPA voltage of V is applied to the passive word lines connected to the selected memory cells (1) and (4). According to various aspects, a voltage (V FE (B), PAS) may be, for example, between about 0V (or V SS ) to about 1 / 2*|V PP | in the range. According to various aspects, the write voltage (V PP ) and the voltage (V FE(B)，PAS The voltage value of the write voltage (V PP ) may have a positive voltage value, and the first prohibition voltage (V FE(B)，PAS ) can have negative voltage values ​​and vice versa.

[0220] According to various aspects, disturbance of other memory cells 602 of the memory cell arrangement 600 can be prevented during reading of the selected memory cells (1), (4).

[0221] As an example, the memory cell arrangement 600 may include additional memory cells, and in order to avoid disturbing one or more additional memory cells of the memory cell arrangement 600 during reading of the selected ferroelectric capacitor FE(A) of the selected memory cells (1), (4) (hereinafter also referred to as the selected ferroelectric capacitor FE(A-1, A-4)), different from V G A voltage of V is applied to the passive word line connected to the ferroelectric capacitor FE of the non-selected memory cell. G A voltage of V may be applied to all passive word lines connected to the ferroelectric capacitors FE of the non-selected memory cells of the memory cell arrangement 600 that do not share the same word line (WL(1), WL(2)) as the selected memory cells (1), (4). According to various aspects, the voltage (V FE，PAS ) may be, for example, between about V SS (e.g., 0V) to about 1 / 2*|V G | within the range.

[0222] According to various aspects, the read voltage (V G ) and the voltage (V FE，PAS The voltage value of the read voltage (V G ) may have a positive voltage value, and the second prohibition voltage (VFE，PAS ) can have negative voltage values ​​and vice versa.

[0223] Furthermore, in order to avoid disturbing one or more additional memory cells of the memory cell arrangement 600 during reading of the selected ferroelectric capacitor FE (A-1, A-4), the base voltage (e.g., V SS ) or a voltage close to the base voltage is applied to the inactive bit lines of the field effect transistors FT connected to the non-selected memory cells. A voltage equal to or close to the base voltage may be applied to all inactive bit lines and / or all inactive source lines of the field effect transistors connected to the non-selected memory cells of the memory cell arrangement 600 that do not share the same word line (WL(1), WL(2)) with the selected memory cells (1), (4). In this case, the voltage applied to the corresponding bit lines and / or source lines of the non-selected memory cells may be, for example, 0 V or a voltage close to 0 V (e.g., a voltage in the range of about -0.25 V to about 0.25 V).

[0224] As described above, individual NAND cell pairs of the memory cell arrangement 600 may be read. It should be noted that some or all of the described voltages are merely examples, and deviations from the described voltages are possible.

[0225] According to various aspects, the body and source terminals of the transistors of memory cell 602 (including semiconductor material) can be held at V SS , but the effective bit line potential can be charged to a level greater than V SS to detect the charge generated by the ferroelectric capacitor FE.

[0226] According to various aspects, a NAND architecture is described herein to organize 1T2C memory cells into an array structure to construct a memory array. By coordinating the voltage applied to the two capacitors, interference during read and write processes can be effectively reduced. For write inhibition, junction leakage can be avoided because all semiconductor terminals can be kept grounded. This structure allows bit variability of long channel transistors. According to various aspects, if necessary, another memory element can be used instead of a ferroelectric capacitor. According to various aspects, if necessary, another transistor can be used instead of a field effect transistor.

[0227] According to various aspects, multiple 1T2C memory cells can be organized into an AND architecture. Figure 4KAn example configuration of a memory cell arrangement 700 including six memory cells 702 having an AND configuration is shown. The memory cells 702 of the memory cell arrangement 700 may be written or read in a manner similar to that described with reference to the NOR configuration, wherein an additional voltage may be applied at the corresponding source line SL. In an example, to read a selected memory cell, a read voltage having a voltage value of approximately 0.6V may be applied to a word line (WL) corresponding to the selected memory cell, and a first (active) lever voltage having a voltage value of approximately 0.9V may be applied to a lever line (LL) corresponding to the selected memory cell. For example, a second (passive) lever voltage having a voltage value of approximately 0.3V may be applied to an inactive lever line corresponding to a non-selected memory cell.

[0228] According to various aspects, a plurality of multi-bit memory cells can be organized into an AND architecture. Figure 4L An exemplary configuration of a memory cell arrangement 710 including six multi-bit memory cells 704 having an AND configuration is shown. In this example, each multi-bit memory cell 704 may have three memory capacitor structures. The memory cells 704 of the memory cell arrangement 710 may be written or read in a manner similar to that described with reference to the NOR configuration, wherein an additional voltage may be applied at the corresponding source line SL.

[0229] Figure 5A An example memory cell arrangement 10 is schematically shown according to various aspects, the memory cell arrangement including a first memory cell 1(1), a second memory cell 1(2), a third memory cell 1(3), and a fourth memory cell 1(4). According to various aspects, each of the first memory cell 1(1), the second memory cell 1(2), the third memory cell 1(3), and the fourth memory cell 1(4) can be configured substantially the same as the memory cell 1. The first memory cell 1(1) can include an electrode column 12(1), a memory material portion 22(1), a dielectric material portion 42(1), and a field effect transistor structure 30(1). The second memory cell 1(2) can include an electrode column 12(2), a memory material portion 22(2), a dielectric material portion 42(2), and a field effect transistor structure 30(2). The third memory cell 1(3) can include an electrode column 12(3), a memory material portion 22(3), a dielectric material portion 42(3), and a field effect transistor structure 30(3). The fourth memory cell 1 ( 4 ) may include an electrode pillar 12 ( 4 ), a memory material portion 22 ( 4 ), a dielectric material portion 42 ( 4 ), and a field effect transistor structure 30 ( 4 ).

[0230] The memory cell arrangement 10 may include a first electrode layer 24(1). The first electrode layer 24(1) may surround (e.g., circumferentially surround, e.g., completely circumferentially surround) a memory material portion 22(1) associated with a first memory cell 1(1) and a first side portion of an electrode column 12(1). The first electrode layer 24(1), the memory material portion 22(1), and the electrode column 12(1) of the first memory cell 1(1) may form a capacitive memory structure. The first electrode layer 24(1) may surround (e.g., circumferentially surround, e.g., completely circumferentially surround) a memory material portion 22(2) associated with a second memory cell 1(2) and a first side portion of an electrode column 12(2). The first electrode layer 24(1), the memory material portion 22(2), and the electrode column 12(2) of the second memory cell 1(2) may form a capacitive memory structure. Illustratively, the first electrode layer 24(1) may provide a first electrode layer 24 of each of the first memory cell 1(1) and the second memory cell 1(2).

[0231] The memory cell arrangement 10 may include a second electrode layer 24(2). The second electrode layer 24(2) may surround (e.g., circumferentially surround, e.g., completely circumferentially surround) a memory material portion 22(3) associated with a third memory cell 1(3) and a first side portion of an electrode column 12(3). The second electrode layer 24(2), the memory material portion 22(3), and the electrode column 12(3) of the third memory cell 1(3) may form a capacitive memory structure. The second electrode layer 24(2) may surround (e.g., circumferentially surround, e.g., completely circumferentially surround) a memory material portion 22(4) associated with a fourth memory cell 1(4) and a first side portion of an electrode column 12(4). The second electrode layer 24(2), the memory material portion 22(4), and the electrode column 12(4) of the second memory cell 1(4) may form a capacitive memory structure. Illustratively, the second electrode layer 24(2) may provide a first electrode layer 24 of each of the third memory cell 1(3) and the fourth memory cell 1(4).

[0232] The memory cell arrangement 10 may include a third electrode layer 44(1). The third electrode layer 44(1) may surround (e.g., circumferentially surround, e.g., completely circumferentially surround) a dielectric material portion 42(1) associated with the first memory cell 1(1) and a second side portion of the electrode column 12(1). The third electrode layer 44(1), the dielectric material portion 42(1), and the electrode column 12(1) of the first memory cell 1(1) may form a capacitor structure. The third electrode layer 44(1) may surround (e.g., circumferentially surround, e.g., completely circumferentially surround) a dielectric material portion 42(3) associated with the third memory cell 1(3) and a second side portion of the electrode column 12(3). The third electrode layer 44(1), the dielectric material portion 42(3), and the electrode column 12(3) of the third memory cell 1(3) may form a capacitor structure. Illustratively, the third electrode layer 44(1) may provide the second electrode layer 44 of each of the first memory cell 1(1) and the third memory cell 1(3).

[0233] The memory cell arrangement 10 may include a fourth electrode layer 44(2). The fourth electrode layer 44(2) may surround (e.g., circumferentially surround, e.g., completely circumferentially surround) a dielectric material portion 42(2) and an electrode column 12(2) associated with the second memory cell 1(2). The fourth electrode layer 44(2), the dielectric material portion 42(2), and the electrode column 12(2) of the second memory cell 1(2) may form a capacitor structure. The fourth electrode layer 44(2) may surround (e.g., circumferentially surround, e.g., completely circumferentially surround) a dielectric material portion 42(4) and a second side portion of the electrode column 12(4) associated with the fourth memory cell 1(4). The fourth electrode layer 44(2), the dielectric material portion 42(4), and the electrode column 12(4) of the fourth memory cell 1(4) may form a capacitor structure. Illustratively, the fourth electrode layer 44(2) may provide a second electrode layer 44 of each of the second memory cell 1(2) and the fourth memory cell 1(4).

[0234] Thus, each memory cell may include at least two capacitor structures, such as a capacitor memory structure (formed by the corresponding electrode column 12, the corresponding memory material portion 22, and the corresponding electrode layer 24) and a capacitor structure (formed by the corresponding electrode column 12, the corresponding dielectric material portion 42, and the corresponding electrode layer 44). According to various aspects, each memory cell may include multiple capacitor structures. Illustratively, each memory cell 1 may be configured as a 1TnC cell (i.e., a memory cell including one transistor 1T and "n" capacitors nC). For example, each memory cell 1 may be configured as a 1T2C cell (i.e., a memory cell including one transistor 1T and two capacitors 2C).

[0235] The first electrode layer 24(1) and the second electrode layer 24(2) may be arranged in the same layer of the memory cell device. The first electrode layer 24(1) and the second electrode layer 24(2) may each extend in a first plane along a first direction. The third electrode layer 44(1) and the fourth electrode layer 44(2) may be arranged in the same layer of the memory cell device, which layer is different from the layer in which the first electrode layer 24(1) and the second electrode layer 24(2) may be arranged. The third electrode layer 44(1) and the fourth electrode layer 44(2) may each extend in a second plane different from the first plane along a second direction different from the first direction. The third electrode layer 44(1) and the fourth electrode layer 44(2) may each extend in a second plane along the first direction.

[0236] Figure 5B A top view of an example memory cell arrangement 10 including a first memory cell 1(1), a second memory cell 1(2), a third memory cell 1(3), and a fourth memory cell 1(4) according to various aspects is shown. In this example, the third electrode layer 44(1) and the fourth electrode layer 44(2) can each extend in a second plane along a second direction. According to various aspects, the memory cell arrangement 10 can include at least one control circuit 800. The control circuit 800 can be configured to apply one or more voltages to corresponding electrode layers, such as the first electrode layer 24(1), the second electrode layer 24(2), the third electrode layer 44(1), and / or the fourth electrode layer 44(2).

[0237] According to various aspects, each dielectric material portion 42(1), 42(2), 42(3), 42(4) of a respective memory cell 1(1), 1(2), 1(3), 1(4) may include or may consist of a non-spontaneously polarized material, such that each capacitor structure formed by the respective dielectric material portion 42(1), 42(2), 42(3), 42(4), the respective electrode layer 44(1), 44(2), and the respective electrode pillars 12(1), 12(2), 12(3), 12(4) is a capacitive lever structure, such as Figure 5C and Figure 5D According to various aspects, each dielectric material portion 42(1), 42(2), 42(3), 42(4) of the corresponding memory cell 1(1), 1(2), 1(3), 1(4) may include or may be composed of a spontaneously polarized material (e.g., a remanently polarized material, such as a ferroelectric material, such as an antiferroelectric material), such that each capacitor structure formed by the corresponding dielectric material portion 42(1), 42(2), 42(3), 42(4), the corresponding electrode layer 44(1), 44(2) and the corresponding electrode column 12(1), 12(2), 12(3), 12(4) is a capacitive memory structure, such as Figure 5EIn this case, each memory cell 1 (1), 1 (2), 1 (3), 1 (4) may be a multi-bit memory cell including at least two capacitor memory structures.

[0238] Figure 5C An example configuration of a memory cell arrangement 10 including a first memory cell 1 ( 1 ), a second memory cell 1 ( 2 ), a third memory cell 1 ( 3 ), and a fourth memory cell 1 ( 4 ) according to various aspects is shown. Figure 5D A perspective view of a memory cell arrangement driven by one or more control circuits 10 according to various aspects is shown. According to various aspects, the memory cell arrangement 10 may include a plurality of control lines. The memory cell arrangement 10 may include a first word line WL(1). The first electrode layer 24(1) may be conductively connected to the first word line WL(1). The first electrode layer 24(1) may form at least a portion of the first word line WL(1). The memory cell arrangement 10 may include a second word line WL(2). The second electrode layer 24(2) may be conductively connected to the second word line WL(2). The second electrode layer 24(2) may form at least a portion of the second word line WL(2). The memory cell arrangement 10 may include a first lever line LL(1). The third electrode layer 44(1) may be conductively connected to the first lever line LL(1). The third electrode layer 44(1) may form at least a portion of the first lever line LL(1). The memory cell arrangement 10 may include a second lever line LL(2). The fourth electrode layer 44(2) may be conductively connected to the second lever line LL(2). The fourth electrode layer 44(2) may form at least a portion of the second lever line LL(2). According to various aspects, the control circuit 800 may be configured to apply a first word line voltage VWL(1) to the first word line WL(1), apply a second word line voltage VWL(2) to the second word line WL(2), apply the first lever line voltage VLL(1) to the first lever line LL(1), and / or apply the second lever line voltage VLL(2) to the second lever line LL(2).

[0239] According to various aspects, for each memory cell 1(1), 1(2), 1(3), 1(4), the associated first electrode layer 24(1) or second electrode layer 24(2), the memory material portion associated with the memory cell, and the electrode column 12 associated with the memory cell can form a capacitive memory structure (also referred to as a ferroelectric capacitor in some aspects) FE. According to various aspects, for each memory cell 1(1), 1(2), 1(3), 1(4), the associated third electrode layer 44(1) or fourth electrode layer 44(2), the dielectric material portion associated with the memory cell, and the electrode column 12 associated with the memory cell can form a capacitive lever structure (also referred to as a lever capacitor in some aspects) LE.

[0240] According to various aspects, the memory cell arrangement 10 can be as described with reference to Figure 4C and Figure 4D In this case, the memory cells of the memory cell arrangement 10 may be arranged as described with reference to Figure 4C is written as described and can be referred to as Figure 4D At least one control circuit 800 may be configured to apply a reference Figure 4C and / or Figure 4D The voltage described.

[0241] According to various aspects, the memory cell arrangement 10 can be as described with reference to Figure 4E and Figure 4F In this case, the memory cells of the memory cell arrangement 10 may be arranged as described with reference to Figure 4E is written as described and can be referred to as Figure 4F At least one control circuit 800 may be configured to apply a reference Figure 4E and / or Figure 4F The voltage described.

[0242] Figure 5E An example configuration of a memory cell arrangement 10 including a first memory cell 1(1), a second memory cell 1(2), a third memory cell 1(3), and a fourth memory cell 1(4) according to various aspects is shown. Each of the first memory cell 1(1), the second memory cell 1(2), the third memory cell 1(3), and the fourth memory cell 1(4) can be configured as a multi-bit memory cell. In this example, each dielectric material portion 42(1), 42(2), 42(3), 42(4)) of the corresponding memory cell 1(1), 1(2), 1(3), 1(4) can include or can be composed of a spontaneously polarized material, so that each memory cell 1(1), 1(2), 1(3), 1(4) can be a multi-bit memory cell including at least two capacitive memory structures 2A, 2B. The memory cell arrangement 10 may include a first electrode layer 24(1) (hereinafter also referred to as the first electrode layer 24A(1)), a second electrode layer 24(2) (hereinafter also referred to as the second electrode layer 24A(2)), a third electrode layer 44(1) (hereinafter also referred to as the third electrode layer 24B(1)) and a fourth electrode layer 44(2) (hereinafter also referred to as the fourth electrode layer 24B(2)).

[0243] The memory cell arrangement 10 may include a first group of word lines WL(1A), WL(1B) connected to a first memory cell 1(1) and a second memory cell 1(2). The first group of memory cells may include a first word line WL(1A) and a third word line WL(1B). A first electrode layer 24A(1) may be conductively connected to the first word line WL(1). The first electrode layer 24A(1) may form at least a portion of the first word line WL(1A). A third electrode layer 24B(1) may be conductively connected to the third word line WL(1B). The third electrode layer 24B(1) may form at least a portion of the third word line WL(1B).

[0244] The memory cell arrangement 10 may include a second group of word lines WL(2A), WL(2B) connected to the third memory cell 1(3) and the fourth memory cell 1(4). The second group of memory cells may include a second word line WL(2A) and a fourth word line WL(2B). The second electrode layer 24A(2) may be conductively connected to the second word line WL(2A). The second electrode layer 24A(2) may form at least a portion of the second word line WL(2A). The fourth electrode layer 24B(2) may be conductively connected to the fourth word line WL(2B). The fourth electrode layer 24B(2) may form at least a portion of the fourth word line WL(2B).

[0245] According to various aspects, the control circuit 800 can be configured to apply a first word line voltage VWL(1A) to the first word line WL(1A), apply a second word line voltage VWL(2A) to the second word line WL(2A), apply a word line voltage VWL(1B) to the third word line WL(1B), and / or apply a fourth word line voltage VWL(2B) to the fourth word line WL(2B).

[0246] According to various aspects, the memory cell arrangement 10 can be as described with reference to Figure 4C and Figure 4D In this case, the Figure 4G The at least one control circuit 800 may be configured to apply a reference Figure 4G The voltage described.

[0247] According to various aspects, the memory cell arrangement 10 can be as described with reference to Figure 4H In this case, the NAND configuration can be organized as described in reference Figure 4H The at least one control circuit 800 may be configured to apply a reference Figure 4H The voltage described.

[0248] Fig. 5FA cross section of a memory cell arrangement with a NAND architecture according to various aspects is schematically shown. In this example, the height h(24) of the first electrode layer 24 may be greater than the height h(44) of the second electrode layer 44. According to various aspects, each capacitive memory structure formed by the first electrode layer 24, the corresponding electrode column 12, and the corresponding memory material portion 22 may have a first effective area, and each capacitive structure formed by the corresponding second electrode layer 44, the corresponding electrode column 12, and the corresponding memory material portion 42 may have a second effective area different from the first effective area. According to various aspects, the first electrode layer 24 may extend in a first plane (e.g., parallel to the xy plane, e.g., described by one or more first z values) along a first direction (e.g., y direction) different from the first plane, and the second electrode layer 44 may extend in a second plane (e.g., parallel to the xy plane, e.g., different from the first plane, e.g., described by one or more second z values ​​different from the first z value) along a second direction (e.g., x direction) different from the first plane.

[0249] According to various aspects, each memory cell may include at least three capacitor structures. Illustratively, each memory cell of the memory cell arrangement may be configured as a 1TnC cell (i.e., a memory cell including one transistor 1T and "n" capacitors nC, where "n" may be equal to or greater than three). According to various aspects, each memory cell of the memory cell arrangement may include one field effect transistor FT (1T), one lever capacitor LE (1C), and multiple ferroelectric capacitors FE ((n-1)C). According to various aspects, the memory cell including multiple ferroelectric capacitors FE ((n-1)C) may be a multi-bit memory cell as described herein.

[0250] According to various aspects, the 1TnC memory cells of the memory cell arrangement may be organized as an array based on a NOR architecture, such as Fig. 6A (exemplarily for a 1T3C memory cell) and Figure 6B According to various aspects, the 1TnC memory cell of the memory cell arrangement can be organized into an array based on a NAND architecture, such as Figure 6C (exemplarily for a 1T3C memory cell) and Fig.6D According to various aspects, the 1TnC memory cell of the memory cell arrangement can be organized as an array based on an AND architecture, such as Fig. 6E As shown (for a 1T4C memory cell by way of example).

[0251] Fig. 6AA memory cell arrangement 900 having a NOR architecture and including a multi-bit memory cell 902 according to various aspects is schematically shown. Each memory cell 902 can be configured as a 1T3C memory cell. Each memory cell 902 of the memory cell arrangement 900 can include a lever capacitor LE, a first ferroelectric capacitor FE(A), a second ferroelectric capacitor FE(B), and a field effect transistor FT. The lever capacitor LE of the corresponding memory cell 902 can be connected to the corresponding lever line LL(1), LL(2) and the floating gate of the field effect transistor FT of the corresponding memory cell 902. The first ferroelectric capacitor FE(A) of the corresponding memory cell 902 can be connected to the corresponding word line WL(1A), WL(2A) and the floating gate of the field effect transistor FT of the corresponding memory cell 902. The second ferroelectric capacitor FE(B) of the corresponding memory cell 902 can be connected to the corresponding word line WL(1B), WL(2B) and the floating gate of the field effect transistor FT of the corresponding memory cell 902. The field effect transistor FT may be connected with its source S to a common source potential and with its drain D to the corresponding bit line BL(1), BL(2).

[0252] According to various aspects, it can be compared with reference Figure 4C and Figure 4D Addressing (eg, writing, eg, reading) the memory cell 902 of the memory cell arrangement 900 is performed in a similar manner as described above and can be performed with reference to FIG. Figure 4G Addressing (eg, writing, eg, reading) of the ferroelectric capacitor (eg, FE(A), eg, FE(B)) of the memory cell 902 to be addressed is performed in a similar manner as described.

[0253] According to various aspects, a ferroelectric capacitor (e.g., a first ferroelectric capacitor FE(A), for example, a second ferroelectric capacitor FE(B)) can be written. In this example, it can be assumed that only one ferroelectric capacitor (e.g., the first ferroelectric capacitor FE(A) or the second ferroelectric capacitor FE(B)) of a memory cell (1) of the memory cell arrangement 900 is intended to be written (selected to be written, for example, referred to as a selected ferroelectric capacitor of a selected memory cell, also referred to as a selected ferroelectric capacitor in some aspects). In order to program or erase the first ferroelectric capacitor FE(A) of the memory cell (1), a write voltage V PP is applied to the active word line connected to the selected ferroelectric capacitor FE(A) of the selected memory cell (1). In this case, the voltage (V FE，ACT ) can be the write voltage V PP (Also called programming voltage V PP To program or erase a selected ferroelectric capacitor FE(A), the base voltage (e.g., VSS ) or a voltage close to the base voltage is applied to the active bit line of the field effect transistor FT connected to the memory cell (1) corresponding to the selected ferroelectric capacitor FE (A). In addition, in order to program or erase the memory cell (1), the base voltage (e.g., V SS ) or a voltage close to the base voltage is applied to the active lever line connected to the lever capacitor LE of the selected memory cell (1). In this case, the voltage (V LE，ACT ) may be, for example, a base voltage (e.g., 0 V) ​​or a voltage close to the base voltage (e.g., a voltage in the range of about -0.25 V to about 0.25 V). However, a voltage greater than the base voltage (e.g., in the range of about V SS To about V PP / 2) is applied to the active lever line connected to the lever capacitor LE of the selected memory cell (1). In addition, in order to program or erase the memory cell (1), the base voltage (e.g., V SS ) or a voltage close to the base voltage is applied to the active bit line of the field effect transistor FT connected to the selected memory cell (1). In this case, the voltage (V BL，ACT ) can be, for example, a base voltage (e.g., 0 V) ​​or a voltage close to the base voltage (e.g., a voltage in a range of about -0.25 V to about 0.25 V).

[0254] According to various aspects, the field effect transistor structure can be in a non-conductive state during writing of the selected ferroelectric capacitor FE(A) of the selected memory cell. Illustratively, the field effect transistor structure can be closed during writing of the selected ferroelectric capacitor FE(A) of the selected memory cell. This can, for example, increase the speed of writing to the selected ferroelectric capacitor FE(A) of the selected memory cell (e.g., with a writing time of less than 15 ns, such as with a writing time of less than 10 ns). According to various aspects, the write voltage V PP It may be in the range of, for example, about 1V to about 10V, such as about 1.5V to about 6V.

[0255] According to various aspects, interference with other ferroelectric capacitors FE(B) of a selected memory cell (1) can be prevented during writing of a selected ferroelectric capacitor FE(A) of a selected memory cell (1). For example, in order to avoid interference with a second ferroelectric capacitor FE(B) during writing of a selected first ferroelectric capacitor FE(A) of a selected memory cell (1), a ferroelectric capacitor different from V PP A voltage (V ) is applied to an inactive word line connected to a selected memory cell (1). According to various aspects, a voltage (V ) applied to a corresponding word line (WL(1B)) FE(B)，PAS) may be, for example, between about 0 V (or V SS ) to about 1 / 2*|V PP | within the range.

[0256] According to various aspects, the write voltage (V PP ) and the voltage (V FE(B)，PAS The voltage value of the write voltage (V PP ) may have a positive voltage value, and the first prohibition voltage (V FE(B)，PAS ) can have negative voltage values ​​and vice versa.

[0257] According to various aspects, the write voltage V PP The voltage value and the voltage applied to the corresponding lever line (V LE，ACT The voltage value of the write voltage (V PP ) may have a positive voltage value, and the first (active) lever voltage (V LE，ACT ) may have a negative voltage value, and vice versa. According to an example, the write voltage V PP may have a voltage value of +1.0V, and the first lever voltage V LE，ACT May have a voltage value of -1.0V.

[0258] According to various aspects, disturbances to other memory cells 902 of the memory cell arrangement 900 may be prevented during writing to a selected ferroelectric capacitor FE(A) of a selected memory cell (1).

[0259] For example, to avoid disturbing memory cell (2) of memory cell arrangement 900 during writing to memory cell (1), a voltage different from V SS A voltage of V is applied to the passive lever line connected to the lever capacitor LE of the non-selected memory cell (2). Different from V SS A voltage of V may be applied to all passive lever lines connected to the lever capacitors LE of non-selected memory cells of the memory cell arrangement 900 that share the same word line (WL(1A)) as the selected ferroelectric capacitor FE(A) of the selected memory cell (1). According to various aspects, a voltage (V LE，PAS ) may be, for example, between about 1 / 2*|V PP | to about |V PP | within the range.

[0260] According to various aspects, the first lever voltage (V LE，ACT) and the voltage (V LE，PAS The voltage value of the first (active) lever voltage (V LE，ACT ) may have a negative voltage value, and the second (passive) lever voltage (V LE，PAS ) may have a positive voltage value, and vice versa. According to an example, the first lever voltage V LE，ACT may have a voltage value of -1.0V, and the second lever voltage V LE，PAS Can have a voltage value of +0.4V.

[0261] According to various aspects, applying a first lever voltage (V LE，ACT ) and / or with the write voltage (V PP ) compared to the second (passive) lever voltage of opposite sign (V LE，PAS ) ensures that the memory state of unselected memory cells is not changed (eg, neither written nor erased).

[0262] For example, in order to avoid disturbing the memory cells (3), (4) (hereinafter also referred to as the selected ferroelectric capacitor FE (A, 1)) of the memory cell arrangement 900 during writing of the selected ferroelectric capacitor FE (A) of the selected memory cell (1), the ferroelectric capacitors different from V PP A voltage of V is applied to the passive word line connected to the ferroelectric capacitor FE of the non-selected memory cells (3) and (4). PP A voltage of V may be applied to all passive word lines connected to ferroelectric capacitors FE of non-selected memory cells of the memory cell arrangement 900 that do not share the same word line (WL(1A), WL(1B)) as the selected memory cell (1). According to various aspects, a voltage (V FE，PAS ) may be, for example, between about 0 V (or V SS ) to about 1 / 2*|V PP | within the range.

[0263] According to various aspects, the write voltage (V PP ) and the voltage (V FE，PAS The voltage value of the write voltage (V PP ) may have a positive voltage value, and the second prohibition voltage (V FE，PAS ) may have a negative voltage value, and vice versa. According to an example, the write voltage V PPmay have a voltage value of +1.0V, and the second prohibition voltage V FE，PAS Can have a voltage value of -0.2V.

[0264] Furthermore, in order to avoid disturbing the memory cells (3), (4) of the memory cell arrangement 900 during writing to the selected ferroelectric capacitor FE(A,1), the base voltage (e.g., V SS ) or a voltage close to the base voltage is applied to the inactive bit line of the field effect transistor FT connected to the non-selected memory cells (3) and (4). In this case, the voltage (V BL，PAS ) may be, for example, a voltage of 0 V or close to 0 V (eg, a voltage in a range of approximately -0.25 V to approximately 0.25 V).

[0265] As exemplarily described above, individual cells of the memory cell arrangement 900 may be erased. It should be noted that some or all of the described voltages are merely examples and deviations from the described voltages are possible.

[0266] As further described above by way of example, the terminal of the memory cell 902 connected to the bit line (eg, connected to the source / drain region of the field effect transistor of the memory cell 902) may be held at V SS (or at least close to V SS ), thereby eliminating the power consumption from reverse junction leakage from the body to the source and drain during the inhibit period.

[0267] According to various aspects, a ferroelectric capacitor (e.g., a first ferroelectric capacitor FE(A), for example, a second ferroelectric capacitor FE(B)) can be read. In this example, it can be assumed that only one ferroelectric capacitor (e.g., the first ferroelectric capacitor FE(A) or the second ferroelectric capacitor FE(B)) of a selected memory cell (1) of the memory cell arrangement 900 is intended to be read (selected to be read, referred to as a selected ferroelectric capacitor of the selected memory cell, also referred to as a selected ferroelectric capacitor in some aspects). In order to read the selected ferroelectric capacitor FE(A) of the memory cell (1), a read voltage V G is applied to the active word line of the selected ferroelectric capacitor FE(A) (hereinafter also referred to as the selected ferroelectric capacitor FE(A, 1)) connected to the selected memory cell (1). In this case, the voltage (V FE，ACT ) can be the read voltage V G .

[0268] In addition, in order to read the selected ferroelectric capacitor FE(A,1), the voltage (V LE，ACT) is applied to the active lever line connected to the lever capacitor LE of the selected memory cell (1). In this case, the voltage (V LE，ACT ) can be substantially equal to the read voltage V G .

[0269] In addition, to read the selected ferroelectric capacitor FE(A,1), a voltage greater than V SS The potential / voltage is applied to the active bit line of the field effect transistor FT connected to the selected memory cell (1). In this case, the voltage (V BL，ACT ) may be, for example, greater than 0 V. In an example, the voltage (V BL，ACT ) can be 1V.

[0270] The body and source terminals of the field effect transistor of the memory cell can be maintained at or near V SS A voltage (e.g., 0 V or a voltage in a range between about -0.25 V to about 0.25 V).

[0271] According to various aspects, the voltage V G The voltage value and the voltage applied to the corresponding lever line (V LE，ACT The voltage value of the read voltage (V G ) may have a positive voltage value, and the first (active) lever voltage (V LE，ACT ) can have negative voltage values ​​and vice versa.

[0272] According to various aspects, interference with other ferroelectric capacitors FE(B) of a selected memory cell (1) can be prevented during reading of a selected ferroelectric capacitor FE(A) of a selected memory cell (1). For example, in order to avoid interference with a second ferroelectric capacitor FE(B) during reading of a selected first ferroelectric capacitor FE(A) of a selected memory cell (1), a capacitor different from V G A voltage (V ) is applied to an inactive word line connected to a selected memory cell (1). According to various aspects, a voltage (V ) applied to a corresponding word line (WL(1B)) FE(B)，PAS ) may be, for example, between about 0 V (or V SS ) to about 1 / 2*|V PP | within the range.

[0273] According to various aspects, the read voltage (V G ) and the voltage (V FE(B)，PASThe voltage value of the read voltage (V G ) may have a positive voltage value, and the first prohibition voltage (V FE(B)，PAS ) can have negative voltage values ​​and vice versa.

[0274] According to various aspects, disturbance of other memory cells 902 of the memory cell arrangement 900 can be prevented during reading of a selected ferroelectric capacitor FE(A) of a selected memory cell (1).

[0275] For example, to avoid disturbing the memory cell (2) of the memory cell arrangement 900 during reading of the selected ferroelectric capacitor FE (A) of the selected memory cell (1), a capacitor different from V G A voltage different from V is applied to the passive lever line connected to the lever capacitor LE of the non-selected memory cell (2). G A voltage of V is applied to all passive lever lines connected to the lever capacitors LE of the non-selected memory cells of the memory cell arrangement 900 that share the same word line (WL(1A)) as the selected ferroelectric capacitor FE(A,1). According to various aspects, a voltage (V LE，PAS ) may be, for example, between about V SS (e.g., 0V) to about 1 / 2*|V G | within the range.

[0276] According to various aspects, the first lever voltage (V LE，ACT ) and the voltage (V LE，PAS The voltage value of the first (active) lever voltage (V LE，ACT ) may have a positive voltage value, and the second (passive) lever voltage (V LE，PAS ) may have a negative voltage value, and vice versa. According to an example, the first lever voltage V LE，ACT may have a voltage value of +0.6V, and the second lever voltage V LE，PAS Can have a voltage value of -0.1V.

[0277] According to various aspects, applying a first lever voltage (V LE，ACT ) and / or with the read voltage (V G ) compared to the second (passive) lever voltage of opposite sign (V LE，PAS ) ensures that the memory state of unselected memory cells is not changed (eg, neither written nor erased).

[0278] For example, to avoid disturbing the memory cells (3), (4) of the memory cell arrangement 900 during reading of the selected ferroelectric capacitor FE(A, 1), different ferroelectric capacitors may be used. G A voltage of V is applied to the passive word line connected to the ferroelectric capacitor FE of the non-selected memory cells (3) and (4). G A voltage of V may be applied to the passive word lines connected to the ferroelectric capacitors FE of the non-selected memory cells of the memory cell arrangement 900 that do not share the same word line (WL(1A), WL(1B)) as the selected memory cell (1). According to various aspects, a voltage (V FE，PAS ) may be, for example, between about V SS (e.g., 0V) to about 1 / 2*|V G | within the range.

[0279] According to various aspects, the read voltage (V G ) and the voltage (V FE，PAS The voltage value of the read voltage (V G ) may have a positive voltage value, and the second prohibition voltage (V FE，PAS ) can have negative voltage values ​​and vice versa.

[0280] Furthermore, in order to avoid disturbing the memory cells (3), (4) of the memory cell arrangement 900 during reading of the selected ferroelectric capacitor FE(A, 1), the base voltage (e.g., V SS ) or a voltage close to the base voltage is applied to the inactive bit lines of the field effect transistors FT connected to the non-selected memory cells (3), (4). A voltage equal to or close to the base voltage may be applied to all inactive bit lines of the field effect transistors connected to the non-selected memory cells of the memory cell arrangement 900 that do not share the same bit line (BL(1)) as the selected memory cell (1). In this case, the voltage (V BL，PAS ) may be, for example, a voltage of 0 V or close to 0 V (eg, a voltage in a range of approximately -0.25 V to approximately 0.25 V).

[0281] As described above by way of example, individual cells of the memory cell arrangement 900 may be read. It should be noted that some or all of the voltages described are merely examples, and deviations from the described voltages are possible. According to various aspects, the body terminal and the source terminal of the transistor of the memory cell 902 (including the semiconductor material) may be maintained at V SS, but the effective bit line potential can be charged to a level greater than V SS to detect the charge generated by the ferroelectric capacitor FE.

[0282] Figure 6B An example configuration of a memory cell arrangement 910 including six 1T4C memory cells 912 having a NOR configuration is shown. The memory cells 912 of the memory cell arrangement 910 may be as described with reference to Fig. 6A are written and / or read as described.

[0283] Figure 6C A memory cell arrangement 1000 having a NAND architecture and including a multi-bit memory cell 1002 according to various aspects is schematically shown. Each memory cell 1002 can be configured as a 1T3C memory cell. Each memory cell 1002 of the memory cell arrangement 1000 can include a lever capacitor LE, a first ferroelectric capacitor FE(A), a second ferroelectric capacitor FE(B), and a field effect transistor FT. The lever capacitor LE of the corresponding memory cell 1002 can be connected to the corresponding lever line LL(1), LL(2) and the floating gate of the field effect transistor FT of the corresponding memory cell 1002. The first ferroelectric capacitor FE(A) of the corresponding memory cell 1002 can be connected to the corresponding word line WL(1A), WL(2A) and the floating gate of the field effect transistor FT of the corresponding memory cell 1002. The second ferroelectric capacitor FE(B) of the corresponding memory cell 1002 can be connected to the corresponding word line WL(1B), WL(2B) and the floating gate of the field effect transistor FT of the corresponding memory cell 1002.

[0284] According to various aspects, it can be compared with reference Figure 4E and Figure 4F Addressing (eg, writing, eg, reading) the memory cell 1002 of the memory cell arrangement 1000 is performed in a similar manner as described above and can be performed with reference to FIG. Figure 4H Addressing (eg, writing, eg, reading) of the ferroelectric capacitor (eg, FE(A), eg, FE(B)) of the memory cell 1002 to be addressed is performed in a similar manner as described.

[0285] According to various aspects, a ferroelectric capacitor (e.g., a first ferroelectric capacitor FE(A), for example, a second ferroelectric capacitor FE(B)) can be written. In this example, it can be assumed that only one ferroelectric capacitor (e.g., the first ferroelectric capacitor FE(A) or the second ferroelectric capacitor FE(B)) of a memory cell (1) of the memory cell arrangement 1000 is intended to be written (selected to be written, for example, referred to as a selected ferroelectric capacitor of a selected memory cell, also referred to as a selected ferroelectric capacitor in some aspects). In order to program or erase the first ferroelectric capacitor FE(A) of the memory cell (1), a write voltage V PP is applied to the active word line of the selected ferroelectric capacitor FE(A) connected to the selected memory cell (1). In this case, the voltage (V FE，ACT ) can be the write voltage V PP (Also called programming voltage V PP ). In addition, in order to program or erase the memory cell (1), the base voltage (e.g., V SS ) or a voltage close to the base voltage is applied to the active lever line connected to the lever capacitor LE of the selected memory cell (1). In this case, the voltage (V LE，ACT ) may be, for example, a base voltage (e.g., 0 V) ​​or a voltage close to the base voltage (e.g., a voltage in the range of about -0.25 V to about 0.25 V). However, a voltage greater than the base voltage (e.g., in the range of about V SS To about V PP / 2) is applied to the active lever line connected to the lever capacitor LE of the selected memory cell (1). In addition, in order to program or erase the selected ferroelectric capacitor FE (A), the base voltage (e.g., V SS ) or a voltage close to the base voltage is applied to the active bit line of the field effect transistor FT connected to the memory cell (1) corresponding to the selected ferroelectric capacitor FE (A). In this case, the voltage (V BL，ACT ) may be, for example, a base voltage (e.g., 0 V) ​​or a voltage close to the base voltage (e.g., a voltage in a range of about -0.25 V to about 0.25 V). For example, the voltage (V BL，ACT ) can be applied to the third terminal corresponding to the bit line (BL(1)). To program or erase the selected ferroelectric capacitor FE(A), the base voltage (e.g., V SS) or a voltage close to the base voltage is applied to the active source line of the field effect transistor FT connected to the selected ferroelectric capacitor FE(A) of the memory cell (1). In this case, the voltage applied to the corresponding source line (SL(1)) may be, for example, the base voltage (e.g., 0 V) ​​or a voltage close to the base voltage (e.g., a voltage in the range of about -0.25 V to about 0.25 V). For example, the voltage applied to the corresponding source line (SL(1)) may be applied to the fourth terminal corresponding to the source line (SL(1)).

[0286] According to various aspects, the field effect transistor structure can be in a non-conductive state during writing to a selected memory cell. Illustratively, the field effect transistor structure can be closed during writing to a selected memory cell. This can, for example, increase the speed of writing to the selected memory cell (e.g., to a write time of less than 15 ns, such as a write time of less than 10 ns).

[0287] According to various aspects, the write voltage V PP It may be in the range of, for example, about 1V to about 10V, such as about 1.5V to about 6V.

[0288] According to various aspects, the write voltage V PP The voltage value and the voltage applied to the corresponding lever line (V LE，ACT The voltage value of the write voltage (V PP ) may have a positive voltage value, and the first (active) lever voltage (V LE，ACT ) may have a negative voltage value, and vice versa. According to an example, the write voltage V PP may have a voltage value of +1.0V, and the first lever voltage V LE，ACT May have a voltage value of -1.0V.

[0289] According to various aspects, disturbance of other ferroelectric capacitors FE(B) of a selected memory cell (1) can be prevented during writing of a selected ferroelectric capacitor FE(A) of a selected memory cell (1).

[0290] For example, in order to avoid disturbing the second ferroelectric capacitor FE(B) during writing to the selected first ferroelectric capacitor FE(A) of the selected memory cell (1), a voltage different from V PP A voltage (V ) is applied to an inactive word line connected to a selected memory cell (1). According to various aspects, a voltage (V ) applied to a corresponding word line (WL(1B)) FE(B)，PAS ) may be, for example, between about 0 V (or V SS ) to about 1 / 2*|V PP | within the range.

[0291] According to various aspects, the write voltage (V PP ) and the voltage (V FE(B)，PAS The voltage value of the write voltage (V PP ) may have a positive voltage value, and the first prohibition voltage (V FE(B)，PAS ) can have negative voltage values ​​and vice versa.

[0292] According to various aspects, disturbances to other memory cells 1002 of the memory cell arrangement 1000 can be prevented during writing to the selected memory cell (1).

[0293] For example, to avoid disturbing the memory cell (2) of the memory cell arrangement 1000 during writing of the selected first ferroelectric capacitor FE (A) of the selected first memory cell (1), a capacitor different from V SS A voltage of V is applied to the passive lever line connected to the lever capacitor LE of the non-selected memory cell (2). Different from V SS A voltage of V may be applied to all passive lever lines connected to the lever capacitors LE of non-selected memory cells of the memory cell arrangement 100 that share the same word line (WL(1A)) as the selected first ferroelectric capacitor FE(A) of the selected memory cell (1). According to various aspects, a voltage (V LE，PAS ) may be, for example, between about 1 / 2*|V PP | to about |V PP | within the range.

[0294] According to various aspects, the first lever voltage (V LE，ACT ) and the voltage (V LE，PAS The voltage value of the first (active) lever voltage (V LE，ACT ) may have a negative voltage value, and the second (passive) lever voltage (V LE，PAS ) may have a positive voltage value, and vice versa. According to an example, the first lever voltage V LE，ACT may have a voltage value of -1.0V, and the second lever voltage V LE，PAS Can have a voltage value of +0.4V.

[0295] According to various aspects, the second lever voltage V LE，PAS, so that the field effect transistor structures of the non-selected memory cells of the memory cell arrangement 1000 are in an inversion state.

[0296] According to various aspects, applying a first lever voltage (V LE，ACT ) and / or with the write voltage (V PP ) compared to the second (passive) lever voltage of opposite sign (V LE，PAS ) ensures that the memory state of unselected memory cells is not changed (eg, neither written nor erased).

[0297] According to various aspects, in a NAND configuration of multiple memory cells, each field effect transistor structure of the multiple memory cells can be configured such that (e.g., via implantation of a channel of the corresponding field effect transistor structure) an LVT state of the corresponding memory cell corresponds to a normally-on state of the field effect transistor structure.

[0298] For example, in order to avoid disturbing the memory cells (3) and (4) of the memory cell arrangement 1000 during writing to the selected ferroelectric capacitor FE(A) of the selected memory cell (1) (hereinafter also referred to as the selected ferroelectric capacitor FE(A,1)), different ferroelectric capacitors different from V PP A voltage of V is applied to the passive word line connected to the ferroelectric capacitor FE of the non-selected memory cells (3) and (4). PP A voltage of V may be applied to the passive word lines connected to the ferroelectric capacitors FE of the non-selected memory cells of the memory cell arrangement 1000 that do not share the same word line (WL(1A), WL(1B)) as the selected memory cell (1). According to various aspects, a voltage (V FE，PAS ) may be, for example, between about 0 V (or V SS ) to about 1 / 2*|V PP | within the range.

[0299] According to various aspects, the write voltage (V PP ) and the voltage (V FE，PAS The voltage value of the write voltage (V PP ) may have a positive voltage value, and the second prohibition voltage (V FE，PAS ) may have a negative voltage value, and vice versa. According to an example, the write voltage V PP can have a voltage value of +1.0V and prohibits the voltage V FE，PAS Can have a voltage value of -0.2V.

[0300] Furthermore, in order to avoid disturbing the memory cells (3), (4) of the memory cell arrangement 1000 during writing to the selected ferroelectric capacitor FE(A,1), the base voltage (e.g., V SS ) or a voltage close to the base voltage is applied to the inactive bit line of the field effect transistor FT connected to the non-selected memory cells (3) and (4). In this case, the voltage (V BL，PAS ) may be, for example, 0 V or a voltage close to 0 V (eg, a voltage in a range of about -0.25 V to about 0.25 V). For example, the voltage (V BL，ACT ) may be applied to a third terminal corresponding to the bit line (BL(1)). In addition, in order to avoid disturbing the memory cells (3), (4) of the memory cell arrangement 1000 during writing to the selected ferroelectric capacitor FE(A,1), the base voltage (e.g., V SS ) or a voltage close to the base voltage is applied to the inactive source line of the field effect transistor FT connected to the non-selected memory cells (3), (4). In this case, the voltage applied to the corresponding source line (SL(2)) may be, for example, 0 V or a voltage close to 0 V (for example, a voltage in the range of about -0.25 V to about 0.25 V). For example, the voltage applied to the corresponding source line (SL(1)) may be applied to the fourth terminal corresponding to the source line (SL(1)).

[0301] As exemplarily described above, individual cells of the memory cell arrangement 1000 may be erased. It should be noted that some or all of the described voltages are merely examples and deviations from the described voltages are possible.

[0302] As described by way of example further above, the terminal of the memory cell 1002 connected to the bit line (eg, connected to the source / drain region of the field effect transistor of the memory cell 1002) may be held at V SS (or at least close to V SS ), thereby eliminating the power consumption from reverse junction leakage from the body to the source and drain during the inhibit period.

[0303] According to various aspects, a selected ferroelectric capacitor FE(A) of a selected memory cell (1) of the memory cell arrangement 1000 can be read.

[0304] To increase the reading speed, the ferroelectric capacitors of more than one memory cell of the memory cell arrangement 1000 may be read substantially simultaneously.

[0305] In this example, it can be assumed that only one selected ferroelectric capacitor FE(A) of the memory cell (1) of the memory cell arrangement 1000 of the NAND configuration is intended to be read (selected to be read, referred to as the selected ferroelectric capacitor of the selected memory cell). In order to read the selected ferroelectric capacitor FE(A) of the selected memory cell (1), a read voltage V G is applied to the active word line connected to the selected ferroelectric capacitor FE(A) of the selected memory cell (1). In this case, the voltage (V FE，ACT ) can be the read voltage V G .

[0306] Furthermore, in order to select the selected ferroelectric capacitor FE(A) of the selected memory cell (1) for reading, the voltage (V LE，ACT ) is applied to the active lever line connected to the lever capacitor LE of the selected memory cell (1). In this case, the voltage (V LE，ACT ) can be substantially equal to the read voltage V G .

[0307] Furthermore, in order to read the selected ferroelectric capacitor FE(A) of the selected memory cell (1), a voltage greater than V SS The potential / voltage is applied to the active bit line of the field effect transistor FT connected to the selected memory cell (1). In this case, the voltage (V BL，ACT ) may be, for example, greater than 0 V. In an example, the voltage (V BL，ACT ) may be 1V. Furthermore, in order to read the selected ferroelectric capacitor FE(A) of the selected memory cell (1), a potential / voltage may be applied to the active source line of the field effect transistor FT connected to the selected memory cell (1). In this case, the voltage applied to the corresponding source line (SL(1)) may be, for example, equal to 0V. Reading the selected ferroelectric capacitor FE(A) of the selected memory cell (1) may include: providing a voltage to the third terminal and the fourth terminal so that each field effect transistor structure associated with other memory cells in the corresponding first subset of memory cells including the selected memory cell is in a conductive state. For example, a voltage may be applied to the third terminal and the fourth terminal so that each field effect transistor structure connected in series with the selected memory cell (1) is in a conductive state.

[0308] The body and source terminals of the field effect transistor of the memory cell can be maintained at or near V SS A voltage (e.g., 0 V or a voltage in a range between about -0.25 V to about 0.25 V).

[0309] According to the example, the voltage V is read G may have a voltage value of 0.7V, and the voltage (V LE，ACT ) can have a voltage value of 0.5V.

[0310] According to various aspects, the voltage V G The voltage value and the voltage applied to the corresponding lever line (V LE，ACT The voltage value of the read voltage (V G ) may have a positive voltage value, and the first (active) lever voltage (V LE，ACT ) can have negative voltage values ​​and vice versa.

[0311] According to various aspects, interference with other ferroelectric capacitors FE(B) of a selected memory cell (1) can be prevented during writing of a selected ferroelectric capacitor FE(A) of a selected memory cell (1). For example, to avoid interference with a second ferroelectric capacitor FE(B) of a selected memory cell (1) during writing of a selected first ferroelectric capacitor FE(A) of a selected memory cell (1), a voltage different from V may be applied to a passive word line connected to the selected memory cell (1). PP According to various aspects, the voltage (V FE(B)，PAS ) may be, for example, between about 0 V (or V SS ) to about 1 / 2*|V PP | within the range.

[0312] According to various aspects, the write voltage (V PP ) and the voltage (V FE(B)，PAS The voltage value of the write voltage (V PP ) may have a positive voltage value, and the first prohibition voltage (V FE(B)，PAS ) can have negative voltage values ​​and vice versa.

[0313] According to various aspects, disturbance of other memory cells 1002 of the memory cell arrangement 1000 can be prevented during reading of a selected ferroelectric capacitor FE(A) of a selected memory cell (1).

[0314] For example, to avoid disturbing memory cell (2) of memory cell arrangement 1000 during reading of memory cell (1), a voltage different from V GA voltage of V is applied to the passive lever line connected to the lever capacitor LE of the non-selected memory cell (2). Different from V G A voltage of V may be applied to all passive lever lines connected to the lever capacitors LE of non-selected memory cells of the memory cell arrangement 1000 that share the same word line (WL(1A), WL(1B)) as the selected memory cell (1). According to various aspects, a voltage (V LE，PAS ) may be, for example, between about V SS (e.g., 0V) to about 1 / 2*|V G | is within the range of. According to an example, the first lever voltage V LE，ACT can be +0.5V, and the second lever voltage V LE，PAS It can be 1.0V.

[0315] According to various aspects, the first lever voltage (V LE，ACT ) and the voltage (V LE，PAS The voltage value of the first (active) lever voltage (V LE，ACT ) may have a positive voltage value, and the second (passive) lever voltage (V LE，PAS ) can have negative voltage values ​​and vice versa.

[0316] According to various aspects, applying a first lever voltage (V LE，ACT ) and / or with the read voltage (V G ) compared to the second (passive) lever voltage of opposite sign (V LE，PAS ) ensures that the memory state of unselected memory cells is not changed (eg, neither written nor erased).

[0317] As an example, the memory cell arrangement 1000 may include: in order to avoid disturbing the non-selected ferroelectric capacitors of the non-selected memory cells of the memory cell arrangement 1000 during the reading of the selected ferroelectric capacitor FE(A) of the selected memory cell (1), a capacitor different from V G A voltage of V is applied to the passive word line connected to the ferroelectric capacitor FE of the non-selected memory cell. G Voltage (V FE，PAS ) may be applied to all passive word lines connected to the ferroelectric capacitors FE of the non-selected memory cells of the memory cell arrangement 1000 that do not share the same word line (WL(1A), WL(1B)) as the selected memory cell (1). For example, a voltage (V FE，PAS) may be applied to the inactive word lines (WL(2A), WL(2B)) of the non-selected memory cells (3), (4). According to various aspects, the voltage (V FE，PAS ) may be, for example, between about V SS (e.g., 0V) to about 1 / 2*|V G | within the range.

[0318] According to various aspects, the read voltage (V G ) and the voltage (V FE，PAS The voltage value of the read voltage (V G ) may have a positive voltage value, and the second prohibition voltage (V FE，PAS ) can have negative voltage values ​​and vice versa.

[0319] Furthermore, in order to avoid disturbing other memory cells (3), (4) of the memory cell arrangement 1000 during reading of the selected ferroelectric capacitor FE (A) of the selected memory cell (1), the base voltage (e.g., V SS ) or a voltage close to the base voltage is applied to the inactive bit line (BL(2)) of the field effect transistor FT connected to the non-selected memory cells (3), (4). A voltage equal to or close to the base voltage may be applied to all inactive bit lines and / or all inactive source lines of the field effect transistors connected to the non-selected memory cells of the memory cell arrangement 1000 that do not share the same word line (WL(1A), WL(1B)) as the selected memory cell (1). In this case, the voltage applied to the corresponding bit lines and / or source lines of the non-selected memory cells may be, for example, 0V or a voltage close to 0V (for example, a voltage in the range of about -0.25V to about 0.25V).

[0320] As described above, individual NAND cell pairs of the memory cell arrangement 1000 may be read. It should be noted that some or all of the voltages described are merely examples, and deviations from the described voltages are possible. According to various aspects, the body terminal and source terminal of the transistor of the memory cell 1002 (including semiconductor material) may be maintained at V SS , but the effective bit line potential can be charged to a level greater than V SS to detect the charge generated by the ferroelectric capacitor FE.

[0321] Fig.6DAn example configuration of a memory cell arrangement 1010 including six 1T4C memory cells 1012 having a NAND configuration is shown. The memory cells 1012 of the memory cell arrangement 1010 may be as described with reference to Figure 6C are written and / or read as described.

[0322] According to various aspects, multiple 1TnC memory cells can be organized into an AND architecture. Fig. 6E An example configuration of a memory cell arrangement 720 including six 1T4C memory cells 722 having an AND configuration is shown. The memory cells 722 of the memory cell arrangement 720 can be written or read in a manner similar to that described with reference to the NOR configuration, wherein an additional voltage can be applied at the corresponding source line SL. In an example, to read a selected memory cell, a read voltage having a voltage value of approximately 0.6V can be applied to a word line (WL) corresponding to the selected memory cell, and a first (active) lever voltage having a voltage value of approximately 0.9V can be applied to a lever line (LL) corresponding to the selected memory cell. For example, a second (passive) lever voltage having a voltage value of approximately 0.3V can be applied to an inactive lever line corresponding to a non-selected memory cell.

[0323] Fig. 7A and Figure 7B Each schematically illustrates a memory cell arrangement 10 including at least one 1T3C memory cell 1 according to various aspects. The memory cell 1 may include a field effect transistor structure 30, an electrode column 12, a second electrode layer 44, and a dielectric material portion 42. The memory cell 1 may also include a first electrode layer 24 (hereinafter also referred to as the first electrode layer 24 (A)) and a memory material portion 22 (hereinafter also referred to as the first memory material portion 22 (A)). According to various aspects, the memory cell 1 may also include at least one additional electrode layer. The memory cell 1 may include a first additional electrode layer 24B. The first additional electrode layer 24B may be configured substantially similarly to that described with reference to the first electrode layer 24A. The memory cell 1 may also include a second memory material portion 22B. The second memory material portion 22B may be configured substantially similarly to that described with reference to the first memory material portion 22A. For example, the memory cell 1 may include a first capacitive memory structure formed by the electrode column 12, the first memory material portion 22A and the first electrode layer 24A and a second capacitive memory structure formed by the electrode column 12, the second memory material portion 22B and the first additional electrode layer 24B.

[0324] According to various aspects, the first capacitive memory structure 2 and the second capacitive memory structure 2 can be addressed (e.g., written to, e.g., read from) together. Illustratively, the first capacitive memory structure 2 and the second capacitive memory structure 2 can provide a redundant solution for storing the same bit value (see, e.g., Fig. 7A).

[0325] According to various aspects, the first capacitive memory structure 2A and the second capacitive memory structure 2B can be addressed (e.g. written, e.g. read) independently. In this case, the memory cell 1 can be a multi-bit memory cell storing two bit values ​​(see e.g. Figure 7B ).

[0326] Figure 7C A memory cell arrangement 10 including a memory cell 1 according to various aspects is shown. In this example, the memory cell 1 may further include a memory material layer 52. The memory material layer 52 may substantially continuously surround (e.g., circumferentially surround, e.g., completely circumferentially surround) at least a portion of the side 18 of the electrode pillar 12. The memory material layer 52 may provide a first memory material portion 22A and a second memory material portion 22B.

[0327] According to various aspects, the dielectric material portion 42 may include or may consist of a memory material (e.g., a spontaneously polarized material). According to various aspects, the memory material layer 52 may provide a first memory material portion 22A, a second memory material portion 22B, and a dielectric material portion 42A. In this case, the height h(44) of the second electrode layer 44 may be greater than the height h(22A) of the first electrode layer 24A and / or the height h(24B) of the first additional electrode layer 24B.

[0328] Fig.7D A memory cell arrangement 10 including a memory cell 1 according to various aspects is shown. In this example, the memory cell 1 may also include a second additional electrode layer 44A. The second additional electrode layer 44B may be configured substantially similarly as described with reference to the second electrode layer 44 (hereinafter also referred to as the second electrode layer 44A). The memory cell 1 may also include a second dielectric material portion 42B. The second dielectric material portion 42B may be configured substantially similarly as described with reference to the dielectric material portion 42 (hereinafter also referred to as the first dielectric material portion 42A).

[0329] According to various aspects, the memory cell 1 may include a dielectric material layer 50. The dielectric material layer 50 may provide a first dielectric material portion 42A and a second dielectric material portion 42B (see also, for example, Figure 3D And refer to Figure 3D description).

[0330] According to various aspects, the first dielectric material portion 42A and the second dielectric material portion 42B may each include or may consist of a memory material. For example, the memory material layer 52 may provide the first memory material portion 22A, the second memory material portion 22B, the first dielectric material portion 42A, and the second dielectric material portion 42A. Illustratively, the memory material layer 52 may also form the dielectric material layer 50. In this case, at least the sum of the height h(44A) of the second electrode layer 44A and the height h(44B) of the second additional electrode layer 44B may be greater than the height h(24A) of the first electrode layer 24A and may be greater than the height h(24B) of the first additional electrode layer 24B. For example, the height h(44A) of the second electrode layer 44A may be greater than the height h(24A) of the first electrode layer 24A and may be greater than the height h(24B) of the first additional electrode layer 24B. For example, the height h( 44B) of the second additional electrode layer 44B may be greater than the height h( 24A) of the first electrode layer 24A and may be greater than the height h( 24B) of the first additional electrode layer 24B.

[0331] Fig. 7E An example configuration of a memory cell arrangement 10 according to various aspects is shown. The memory cell arrangement 10 may include a first memory cell 1(1), a second memory cell 1(2), a third memory cell 1(3), and a fourth memory cell 1(4). Each of the first memory cell 1(1), the second memory cell 1(2), the third memory cell 1(3), and the fourth memory cell 1(4) may be a 1T3C memory cell. Each of the first memory cell 1(1), the second memory cell 1(2), the third memory cell 1(3), and the fourth memory cell 1(4) may be as described in reference FIG. 7B to FIG. 7D In this example, each memory cell 1(1), 1(2), 1(3), 1(4) may include a first capacitive memory structure 2A, a second capacitive memory structure 2B, and a capacitive lever structure LE.

[0332] The memory cell arrangement 10 may include a first common electrode layer 24A(1) providing a first electrode layer 24A of each of the first memory cell 1(1) and the second memory cell 1(2). The memory cell arrangement 10 may include a second common electrode layer 24A(2) providing a first electrode layer 24A of each of the third memory cell 1(3) and the fourth memory cell 1(4). The memory cell arrangement 10 may include a third common electrode layer 24B(1) providing a first additional electrode layer 24B of each of the first memory cell 1(1) and the second memory cell 1(2). The memory cell arrangement 10 may include a fourth common electrode layer 24B(2) providing a first additional electrode layer 24B of each of the third memory cell 1(3) and the fourth memory cell 1(4). The memory cell arrangement 10 may include a fifth common electrode layer 44(1) providing a second electrode layer 44 of each of the first memory cell 1(1) and the third memory cell 1(3). The memory cell arrangement 10 may include a sixth common electrode layer 44 ( 2 ) that provides a second electrode layer 44 for each of the second memory cell 1 ( 2 ) and the fourth memory cell 1 ( 4 ).

[0333] The memory cell arrangement 10 may include a first group of word lines WL(1A), WL(1B) connected to a first memory cell 1(1) and a second memory cell 1(2). The first group of memory cells may include a first word line WL(1A) and a third word line WL(1B). A first common electrode layer 24A(1) may be conductively connected to the first word line WL(1). The first common electrode layer 24A(1) may form at least a portion of the first word line WL(1A). A third common electrode layer 24B(1) may be conductively connected to the third word line WL(1B). The third common electrode layer 24B(1) may form at least a portion of the third word line WL(1B).

[0334] The memory cell arrangement 10 may include a second group of word lines WL(2A), WL(2B) connected to the third memory cell 1(3) and the fourth memory cell 1(4). The second group of memory cells may include a second word line WL(2A) and a fourth word line WL(2B). The second common electrode layer 24A(2) may be conductively connected to the second word line WL(2A). The second common electrode layer 24A(2) may form at least a portion of the second word line WL(2A). The fourth common electrode layer 24B(2) may be conductively connected to the fourth word line WL(2B). The fourth common electrode layer 24B(2) may form at least a portion of the fourth word line WL(2B).

[0335] The memory cell arrangement 10 may include a first lever line LL(1). The fifth common electrode layer 44(1) may be conductively connected to the first lever line LL(1). The fifth common electrode layer 44(1) may form at least a portion of the first lever line LL(1). The memory cell arrangement 10 may include a second lever line LL(2). The sixth common electrode layer 44(2) may be conductively connected to the second lever line LL(2). The sixth common electrode layer 44(2) may form at least a portion of the second lever line LL(2).

[0336] According to various aspects, the control circuit 800 can be configured to apply a first word line voltage VWL(1A) to the first word line WL(1A), apply a second word line voltage VWL(2A) to the second word line WL(2A), apply a word line voltage VWL(1B) to the third word line WL(1B), apply a fourth word line voltage VWL(2B) to the fourth word line WL(2B), apply a first lever line voltage VLL(1) to the first lever line LL(1) and / or apply a second lever line voltage VLL(2) to the second lever line LL(2).

[0337] According to various aspects, the memory cell arrangement 10 can be organized into a NOR configuration. In this case, the selected field effect transistor structure 2A or 2B of the selected memory cell 1(1), 1(2), 1(3), or 1(4) of the memory cell arrangement 10 can be as described with reference to Fig. 6A is written or read as described.

[0338] At least one control circuit 800 may be configured to apply a reference Fig. 6A The voltage described.

[0339] According to various aspects, the memory cell arrangement 10 can be organized into a NAND configuration. In this case, the selected field effect transistor structure 2A or 2B of the selected memory cell 1(1), 1(2), 1(3), or 1(4) of the memory cell arrangement 10 can be as described with reference to Figure 6C At least one control circuit 800 may be configured to apply a reference Figure 6C The voltage described.

[0340] Various aspects are directed to memory cells and memory cell arrangements. The memory cell arrangement may include one or more 1TnC memory cells, each 1TnC memory cell including a transistor (e.g., field effect transistor structure 30, such as field effect transistor FT) and a number n of capacitor structures (referred to as capacitive memory structures in some aspects). The number n may be an integer greater than zero. The number n of capacitor structures may be a number n of lever capacitors (referred to as capacitive structures in some aspects, referred to as capacitive lever structures in some aspects). 1and the number n of memory capacitors (referred to in some aspects as capacitive memory structures and in some aspects as ferroelectric capacitors) 2 The sum of the number of lever capacitors n 1 Can be an integer equal to or greater than zero. The number of memory capacitors n 2 can be an integer greater than zero. The number of memory capacitors n 2 In the case of equal to or greater than two, the memory cell may be a multi-bit memory cell and may be configured to store more than one bit. According to various aspects, the lever capacitor and / or the memory capacitor may be as described in reference Figures 1A to 3D , FIG. 5A to FIG. 5F and 7A to 7E The memory cell arrangement 10 is configured as described above. According to various aspects, the memory cell arrangement may include a plurality of 1TnC memory cells. For example, the plurality of 1TnC memory cells may be organized as described in reference Figure 4C , Figure 4D , Figure 4G , Fig. 4I , Fig. 6A and Figure 6B For example, multiple 1TnC memory cells can be organized as shown in reference Figure 4E , Figure 4F , Figure 4H , Figure 4J , Figure 6C and Fig.6D For example, multiple 1TnC memory cells can be organized as shown in reference Figure 4K , Figure 4K and Fig. 6E According to various examples, n 1 = 0 and n 2 = 2 (ie, there is no lever capacitor and there are two memory capacitors) provides a memory cell arrangement, as shown in reference Figure 4G , Figure 4H and Figure 5E As described. According to the example, n 1 = 0 and n 2 = 3 (ie, there is no lever capacitor and there are three memory capacitors) provides a memory cell arrangement, as shown in reference Figure 4L According to various examples, n 1 =1 and n 2 = 1 (ie, there is one lever capacitor and one memory capacitor) provides a memory cell arrangement, as shown in reference FIG. 4C to FIG. 4F , Figures 4I to 4K , Figure 5C and Figure 5D According to various examples, n 1 =1 and n2 = 2 (ie, there is one lever capacitor and two memory capacitors) provides a memory cell arrangement, as shown in reference Fig. 6A , Figure 6C and Fig. 7E According to various examples, n 1 =1 and n 2 =3 (ie, there is one lever capacitor and three memory capacitors) provides a memory cell arrangement, as shown in reference Figure 6B , Fig.6D and Fig. 6E Just as described.

[0341] Note that these memory cell arrangements are provided as examples, and the memory cell arrangements may include any kind of 1TnC memory cells having a number n greater than one.

[0342] Figure 8 A schematic flow chart of a method 1100 for manufacturing a memory cell arrangement according to various aspects is shown.

[0343] The method 1100 may include forming (at 1102 ) one or more field effect transistor structures.

[0344] The method 1100 may include forming an electrode layer stack over the one or more field effect transistor structures in 1104. The electrode layer stack may include at least a first electrode layer, a second electrode layer, and an electrically isolating intermediate layer disposed between the first electrode layer and the second electrode layer.

[0345] The method 1100 may include forming one or more recesses (e.g., holes) in the electrode layer stack, each of the one or more recesses corresponding to one of the one or more field effect transistor structures (in 1006). For example, each of the one or more recesses may be formed substantially above the corresponding field effect transistor structure. According to various aspects, each of the one or more recesses may be formed substantially above the gate structure of the corresponding field effect transistor structure.

[0346] Method 1100 may include partially filling one or more grooves with a memory material (e.g., a spontaneous polarization material as described herein), wherein the memory material may cover at least a sidewall of each of the one or more grooves (in 1108). According to various aspects, partially filling the one or more grooves with the memory material may include partially filling (e.g., conformally, such that the memory material has a linear shape) the one or more grooves with the memory material such that the sidewalls and a bottom of each of the one or more grooves are covered, and then at least partially removing (e.g., completely removing, such as etching) the memory material at the bottom of each of the one or more grooves. According to various aspects, partially filling the one or more grooves with the memory material may include completely filling the one or more grooves with the memory material and then partially etching the memory material.

[0347] The method 1100 may include at least partially filling the remaining space in each of the one or more recesses with the electrode material (in 1110). According to various aspects, a portion of the memory material may be disposed in each of the one or more recesses between a portion of the electrode material and at least one of the first electrode layer and / or the second electrode layer. The electrode material in each of the one or more recesses may be conductively connected to a gate of the field effect transistor structure corresponding to the recess in the one or more field effect transistor structures.

[0348] Fig. 9 A schematic flow chart of a method 1200 for operating a memory cell arrangement according to various aspects is shown.

[0349] Method 1200 may include applying a control voltage to a first control node selected from a plurality of first control nodes of a memory cell, each of the plurality of first control nodes being connected to a corresponding first capacitor structure of a plurality of first capacitor structures (e.g., a plurality of memory capacitor structures) (at 1202). The control voltage may be a write voltage (V PP ), and method 1200 may be a method for writing to a memory cell of a memory cell arrangement. The control voltage may be a read voltage (V G ) and method 1200 may be a method for reading a memory cell of a memory cell arrangement.

[0350] Method 1200 may include applying a lever voltage to a second control node of the memory cell, the second control node connected to a second capacitor (eg, a second capacitor structure, eg, a levered capacitor, eg, a levered capacitor structure) of the memory cell (at 1204).

[0351] The method 1200 may include applying a bit line voltage to a third control node of the memory cell, the third control node connected to at least one source / drain region of a transistor (eg, a field effect transistor structure) of the memory cell (at 1206).

[0352] According to various aspects, method 1200 may optionally further include applying a source line voltage to a fourth control node of the memory cell, the third control node being connected to the first source / drain region of the transistor and the fourth control node being connected to the second source / drain region of the transistor.

[0353] In the following, various examples are provided that may include one or more aspects described above with reference to the memory cell arrangement 10, the memory cell arrangement 100, the method 1100, and the method 1200. It is contemplated that aspects described with respect to the memory arrangement 10 or the memory cell arrangement 100 may also be applied to the method 1100 or the method 1200, and vice versa.

[0354] Example 1 is a memory cell arrangement, comprising: one or more memory cells, each of the one or more memory cells comprising: an electrode column having a bottom surface and a top surface; a memory material portion surrounding a side portion of the electrode column; an electrode layer surrounding the memory material portion and the side portion of the electrode column, wherein the electrode column, the memory material portion and the electrode layer form a capacitor memory structure; and a field effect transistor structure, comprising a gate structure, wherein the bottom surface of the electrode column faces the gate structure and is conductively connected to the gate structure, and wherein the top surface of the electrode column faces away from the gate structure.

[0355] In Example 2, the memory cell arrangement of Example 1 may optionally further include: a height of the electrode column is greater than a width of the electrode column.

[0356] In Example 3, the memory cell arrangement of Example 1 or 2 may optionally further include: the height of the electrode column is defined as being defined by the distance between the bottom surface and the top surface perpendicular to the bottom surface, and / or the width of the electrode column is defined as the extension of the electrode column perpendicular to the height direction (for example, defined by the geometry of the bottom surface and / or the top surface).

[0357] In Example 4, the memory cell arrangement of any one of Examples 1 to 3 may optionally further include: the memory material portion circumferentially surrounding the side surface portion of the electrode column.

[0358] In Example 5, the memory cell arrangement of Example 3 may optionally further include: the memory material portion completely circumferentially surrounds the side surface portion of the electrode column.

[0359] In Example 6, the memory cell arrangement of any one of Examples 1 to 5 may optionally further include: the electrode layer peripherally surrounding the memory material portion.

[0360] In Example 7, the memory cell arrangement of Example 6 may optionally further include: the electrode layer completely circumferentially surrounds the memory material portion.

[0361] In Example 8, the memory cell arrangement of any one of Examples 1 to 7 may optionally further include: the memory material portion directly contacting a side portion of the electrode column.

[0362] In Example 9, the memory cell arrangement of any one of Examples 1 to 8 may optionally further include: the electrode layer directly contacting the memory material portion.

[0363] In Example 10, the memory cell arrangement of any one of Examples 1 to 9 may optionally further include: a side surface of the memory material portion faces a side surface portion of the electrode column and may be substantially parallel to the side surface portion of the electrode column.

[0364] In Example 11, the memory cell arrangement of any one of Examples 1 to 10 may optionally further include: a side surface of the electrode layer faces a side surface portion of the electrode column and may be substantially parallel to the side surface portion of the electrode column. The memory material portion may be disposed between the side surface of the electrode layer and the side surface portion of the electrode column.

[0365] In Example 12, the memory cell arrangement of any one of Examples 1 to 11 may optionally further include: a side surface of the memory material portion faces the side surface portion of the electrode column and is substantially coaxial with the side surface portion of the electrode column.

[0366] In Example 13, the memory cell arrangement of any one of Examples 1 to 12 may optionally further include: a side surface of the electrode layer faces a side surface portion of the electrode column and is substantially coaxial with the side surface portion of the electrode column, wherein the memory material portion is disposed between the side surface of the electrode layer and the side surface portion of the electrode column.

[0367] In Example 14, the memory cell arrangement of any one of Examples 1 to 13 may optionally further include: the electrode layer extends in a lateral plane. For example, the electrode layer may have or may include a planar shape. According to various aspects, the highest point of the gate structure may be located in another lateral plane, and the vertical distance between the lateral plane in which the electrode layer extends and the other lateral plane may be substantially consistent. For example, the gate structure may include a flat top surface facing the electrode layer, and the electrode layer may include a flat bottom surface facing the gate structure, wherein the flat top surface of the gate structure and the flat bottom surface of the electrode layer may be parallel. According to various aspects, the electrode layer may be formed directly on the planarization layer.

[0368] In Example 15, the memory cell arrangement of any one of Examples 1 to 14 may optionally further include: the electrode layer having a first surface and a second surface opposite to the first surface, wherein the first surface and / or the second surface is substantially parallel to a surface of the gate structure.

[0369] In Example 16, the memory cell arrangement of any one of Examples 1 to 15 may optionally further include: a vertical distance (eg, a distance perpendicular to the bottom surface and / or the top surface) between the electrode layer and the gate structure is substantially consistent.

[0370] In Example 17, the memory cell arrangement of any one of Examples 1 to 16 may optionally further include: a distance between a bottom surface of the electrode column and the gate structure is smaller than a distance between a top surface of the electrode column and the gate structure.

[0371] In Example 18, the memory cell arrangement of any one of Examples 1 to 17 may optionally further include: the electrode layer is substantially flat.

[0372] In Example 19, the memory cell arrangement of any one of Examples 1 to 18 may optionally further include: a substrate having a lateral dimension, wherein the electrode layer extends substantially parallel to the lateral dimension of the substrate.

[0373] In Example 20, the memory cell arrangement of Example 19 may optionally further include: the electrode pillars extending substantially perpendicular to a lateral dimension of the substrate.

[0374] In Example 21, the memory cell arrangement of any one of Examples 1 to 20 may optionally further include: a substrate having a lateral direction and a vertical direction, and the electrode layer extends in the lateral direction of the substrate and / or the electrode column extends in the vertical direction of the substrate.

[0375] In Example 22, the memory cell arrangement of any one of Examples 1 to 21 may optionally further include: a chip having a chip surface, wherein the electrode layer is arranged on or above the chip surface substantially parallel to the chip surface.

[0376] In Example 23, the memory cell arrangement of any one of Examples 1 to 22 may optionally further include: the electrode pillars extending substantially perpendicular to the chip surface.

[0377] In Example 24, the memory cell arrangement of any one of Examples 1 to 23 may optionally further include: one or more metallization layers extending substantially parallel to the electrode layer.

[0378] In Example 25, the memory cell arrangement of any one of Examples 1 to 24 may optionally further include: a common electrode layer providing a corresponding electrode layer for each of the one or more memory cells.

[0379] In Example 26, the memory cell arrangement of any one of Examples 1 to 25 may optionally further include: the bottom surface and / or top surface of the electrode column has or includes one of the following geometric shapes: circle, triangle, square, parallelogram, trapezoid, ellipse, polygon, etc.

[0380] In Example 27, the memory cell arrangement of any one of Examples 1 to 26 may optionally further include: the electrode column has a cylindrical shape (e.g., a cylinder, e.g., a truncated cylinder, e.g., a prism) or a frustum (e.g., a frustum of a pyramid, e.g., a frustum of a cone).

[0381] In Example 28, the memory cell arrangement of any one of Examples 1 to 27 may optionally further include: the electrode layer is a first electrode layer and the side portion of the electrode column is a first side portion of the electrode column. Each memory cell may further include: a dielectric material portion surrounding a second side portion of the electrode column that is different from the first side portion; and a second electrode layer surrounding the dielectric material portion and the second side portion of the electrode column, wherein the electrode column, the dielectric material portion and the second electrode layer form a capacitor structure (e.g., a capacitor lever structure, e.g., a capacitor memory structure).

[0382] In Example 29, the memory cell arrangement of Example 28 may optionally further include: a first electrode layer extending in or along a first direction, and wherein the second electrode layer extends in or along a second direction different from the first direction (for example, the first electrode layer and the second electrode layer extend at an angle of approximately 45° or greater relative to each other).

[0383] In Example 30, the memory cell arrangement of any one of Examples 28 or 29 may optionally further include: a first electrode layer extends in a first plane along a first direction and a second electrode layer extends in a second plane along a second direction different from the first direction, wherein the first plane is parallel to the second plane.

[0384] In Example 31, the memory cell arrangement of any one of Examples 28 to 30 may optionally further include: the first electrode layer and the second electrode layer of each of the one or more memory cells are conductively connected to a corresponding control line of a plurality of control lines to allow (e.g., selectively) addressing of the one or more memory cells corresponding to the first electrode layer (e.g., during a read operation and / or a write operation).

[0385] In Example 32, the memory cell arrangement of any one of Examples 28 to 30 may optionally further include: each of the first electrode layer and the second electrode layer forms at least a portion of a corresponding control line.

[0386] In Example 33, the memory cell arrangement of any one of Examples 28 to 32 may optionally further include: one or more memory cells are multiple memory cells and the memory cell arrangement further includes: one or more first control lines (WL), wherein each of the one or more first control lines is connected to a first electrode layer of a first subset of memory cells in the multiple memory cells; and one or more second control lines (LL), wherein each of the one or more second control lines is connected to a second electrode layer of a second subset of memory cells in the multiple memory cells.

[0387] In Example 34, the memory cell arrangement of any one of Examples 28 to 33 may optionally further include: the memory material portion directly contacting the first side portion of the electrode column.

[0388] In Example 35, the memory cell arrangement of any one of Examples 28 to 34 may optionally further include: the dielectric material portion directly contacting the second side portion of the electrode column.

[0389] In Example 36, the memory cell arrangement of Examples 34 and 35 may optionally further include: a contact area between the memory material portion and the first side portion is greater than a contact area between the dielectric material portion and the second side portion.

[0390] In Example 37, the memory cell arrangement of any one of Examples 28 to 36 may optionally further include: a capacitor memory structure having a first effective capacitor area defined by a first electrode layer, and wherein the capacitor structure has a second effective capacitor area defined by a second electrode layer, wherein the second effective capacitor area is different from the first effective capacitor area.

[0391] In Example 38, the memory cell arrangement of any one of Examples 28 to 37 may optionally further include: the memory material portion directly contacting the first side portion of the electrode column.

[0392] In Example 39, the memory cell arrangement of any one of Examples 28 to 38 may optionally further include: the dielectric material portion directly contacting the second side portion of the electrode column.

[0393] In Example 40, the memory cell arrangements of Examples 38 and 39 may optionally further include: a contact area of ​​the dielectric material portion with the second side portion being greater than a contact area of ​​the memory material portion with the first side portion.

[0394] In Example 41, the memory cell arrangement of any one of Examples 28 to 40 may optionally further include: the first electrode layer directly contacting the memory material portion.

[0395] In Example 42, the memory cell arrangement of any one of Examples 28 to 41 may optionally further include: the second electrode layer directly contacting the dielectric material portion.

[0396] In Example 43, the memory cell arrangement of Examples 41 and 42 may optionally further include: a contact area between the first electrode layer and the memory material portion is greater than a contact area between the second electrode layer and the dielectric material portion.

[0397] In Example 44, the memory cell arrangement of any one of Examples 28 to 43 may optionally further include: the first electrode layer directly contacting the memory material portion.

[0398] In Example 45, the memory cell arrangement of any one of Examples 28 to 44 may optionally further include: the second electrode layer directly contacting the dielectric material portion.

[0399] In Example 46, the memory cell arrangement of Examples 44 and 45 may optionally further include: a contact area between the second electrode layer and the dielectric material portion is greater than a contact area between the first electrode layer and the memory material portion.

[0400] In Example 47, the memory cell arrangement of any one of Examples 28 to 46 may optionally further include: the memory material portion is a first memory material portion; and the dielectric material portion includes a dielectric memory material (e.g., is a dielectric memory material) and is configured as a second memory material portion.

[0401] In Example 48, the memory cell arrangement of Example 47 may optionally further include: a substantially continuous memory material layer surrounding at least a portion of (eg, on a perimeter of) a side of the electrode column, wherein the memory material layer provides a first memory material portion and a second memory material portion.

[0402] In Example 49, the memory cell arrangement of any one of Examples 28 to 48 may optionally further include: a common second electrode layer providing a respective second electrode layer for each of the one or more memory cells.

[0403] In Example 50, the memory cell arrangement of any one of Examples 28 to 30 may optionally further include: one or more additional dielectric material portions, each of the one or more additional dielectric material portions surrounding corresponding side portions of the electrode column that are different from each other; one or more additional electrode layers, each of the one or more additional electrode layers surrounding corresponding dielectric material portions in the one or more dielectric material portions and corresponding side portions of the electrode column associated with the corresponding dielectric material portions; wherein the one or more additional electrode layers, the one or more dielectric material portions and the electrode column form a capacitor structure (e.g., a capacitor lever structure, e.g., a capacitor memory structure).

[0404] In Example 51, the memory cell arrangement of any one of Examples 28 to 50 may optionally further include: all electrode layers are spaced apart from each other.

[0405] In Example 52, the memory cell arrangement of any one of Examples 28 to 51 may optionally further include: all electrode columns are spaced apart from each other.

[0406] In Example 53, the memory cell arrangement of any one of Examples 28 to 52 may optionally further include: at least one intermediate layer disposed between two adjacent electrode layers among the electrode layers (the additional electrode layer, the first electrode layer, the second electrode layer).

[0407] In Example 54, the memory cell arrangement of any one of Examples 28 to 53 may optionally include: all electrode pillars are physically separated (and / or electrically isolated) from all electrode layers.

[0408] In Example 55, the memory cell arrangement of any one of Examples 28 to 54 may optionally include: all electrode layers are physically separated (and / or electrically isolated) from each other, and / or all electrode columns are physically separated (and / or electrically isolated) from each other.

[0409] In Example 56, the memory cell arrangement of any one of Examples 28 to 55 may optionally include: each electrode layer includes a metal or a metal alloy (e.g., Cu, Au, Ag, W, Al, Ru, Ti, TiN, Ta, TaN, Co, CoN, Nb, NbN, Pd, Pt, Ir, IrO 2 、RuO 2 etc.) or composed of metal or metal alloy.

[0410] In Example 57, the memory cell arrangement of any one of Examples 28 to 56 may optionally include: each electrode pillar includes a metal or a metal alloy (e.g., Cu, Au, Ag, W, Al, Ru, Ti, TiN, Ta, TaN, Co, CoN, Nb, NbN, Pd, Pt, Ir, IrO 2 、RuO 2 etc.) or composed of metal or metal alloy.

[0411] Example 58 is a memory cell arrangement, comprising: one or more memory cells, each of the one or more memory cells comprising: an electrode column extending from the bottom surface of the electrode column to the top surface of the electrode column; one or more memory material portions, each of the one or more memory material portions surrounds a corresponding first side portion of the electrode column; one or more first electrode layers, each of the one or more first electrode layers surrounds a corresponding memory material portion of the one or more memory material portions and a first side portion of the electrode column associated with the corresponding memory material portion; wherein the first electrode layer, the corresponding memory material portion and the electrode column form a corresponding capacitor memory structure; and a dielectric material portion surrounding a second side portion of the electrode column that is different from each of the first side portions; a second electrode layer surrounding the dielectric material portion and the second side portion of the electrode column, wherein the electrode column, the dielectric material portion and the second electrode layer form a capacitor lever structure; and a field effect transistor structure, comprising a gate structure, wherein the gate structure faces the bottom surface of the electrode column and is conductively connected to the electrode column.

[0412] According to various examples, the memory cell arrangement of Example 58 can be configured as previously described (eg, with reference to Examples 1 to 57).

[0413] Example 59 is a memory cell arrangement, comprising: a first memory cell, a second memory cell, a third memory cell and a fourth memory cell, each of the first memory cell, the second memory cell, the third memory cell and the fourth memory cell comprising: an electrode column extending from a bottom surface of the electrode column to a top surface of the electrode column; a memory material portion surrounding a corresponding first side portion of the electrode column; a dielectric material portion surrounding a corresponding second side portion of the electrode column that is different from the first side portion; and a field effect transistor structure including a gate structure, wherein the gate structure faces the bottom surface of the electrode column and is conductively connected to the electrode column. The memory cell arrangement may further include: a first electrode layer, surrounding a first side portion of the memory material portion and the electrode column associated with the first memory cell, and surrounding a first side portion of the memory material portion and the electrode column associated with the second memory cell, wherein the corresponding electrode column, the corresponding memory material portion and the first electrode layer form a corresponding capacitor memory structure; a second electrode layer, surrounding a first side portion of the memory material portion and the electrode column associated with the third memory cell, and surrounding a first side portion of the memory material portion and the electrode column associated with the fourth memory cell, wherein the corresponding electrode column, the corresponding memory material portion and the second electrode layer form a corresponding capacitor memory structure. structure; a third electrode layer, surrounding the second side portion of the dielectric material portion and the electrode column associated with the first memory cell, and surrounding the second side portion of the dielectric material portion and the electrode column associated with the third memory cell, wherein the corresponding electrode column, the corresponding dielectric material portion and the third electrode layer form a corresponding capacitor structure (for example, a corresponding capacitor memory structure); and a fourth electrode layer, surrounding the second side portion of the dielectric material portion and the electrode column associated with the second memory cell, and surrounding the second side portion of the dielectric material portion and the electrode column associated with the fourth memory cell, wherein the corresponding electrode column, the corresponding dielectric material portion and the fourth electrode layer form a corresponding capacitor structure.

[0414] In Example 60, the memory cell arrangement of Example 59 may optionally include: a first word line conductively connected to the first electrode layer, a second word line conductively connected to the second electrode layer, a first lever line conductively connected to the third electrode layer, and a second lever line conductively connected to the fourth electrode layer.

[0415] In Example 61, the memory cell arrangement of Example 59 may optionally include: a first word line conductively connected to the first electrode layer, a second word line conductively connected to the second electrode layer, a third word line conductively connected to the third electrode layer, and a fourth word line conductively connected to the fourth electrode layer.

[0416] In Example 62, the subject matter of any one of Examples 1 to 61 can optionally include: the memory material portion includes or consists of a spontaneously polarized material.

[0417] In Example 63, the subject matter of Example 62 can optionally include that the spontaneous polarization material is a remanent polarization material (eg, a ferroelectric material). The remanent polarization material can include a first polarization state having a first remanent polarization and a second polarization state having a second remanent polarization.

[0418] In Example 64, the subject matter of Example 63 can optionally include that the remanent polarization material includes or consists of (e.g., ferroelectric) hafnium oxide, (e.g., ferroelectric) zirconium oxide, or a mixture of hafnium oxide and zirconium oxide.

[0419] In Example 65, the subject matter of Example 62 can optionally include: the spontaneous polarization material is an antiferroelectric material.

[0420] In Example 66, the memory cell of any one of Examples 1 to 65 may optionally further include: the memory material portion includes or consists of a material having a first relative dielectric constant, and the dielectric material portion includes or consists of a material having a second relative dielectric constant different from the first relative dielectric constant.

[0421] Example 67 is a method, such as a method for manufacturing a memory cell arrangement, the method comprising: forming one or more field effect transistor structures; forming an electrode layer stack above the one or more field effect transistor structures, wherein the electrode layer stack comprises at least a first electrode layer, a second electrode layer, and an electrically isolating intermediate layer disposed between the first electrode layer and the second electrode layer; forming one or more grooves in the electrode layer stack, each of the one or more grooves corresponding to one of the one or more field effect transistor structures, wherein the one or more grooves extend at least through the first electrode layer, the electrically isolating intermediate layer, and the second electrode layer; partially filling the one or more grooves with a memory material, the memory material at least covering the sidewalls of each of the one or more grooves; and subsequently; and at least partially filling the remaining space in each of the one or more grooves with an electrode material, wherein, in each of the one or more grooves, a portion of the memory material is disposed between a portion of the electrode material and at least one of the first electrode layer and / or the second electrode layer, wherein the electrode material in each of the one or more grooves is conductively connected to a gate of the field effect transistor structure corresponding to the groove of the one or more field effect transistor structures.

[0422] In Example 68, the method of Example 67 may optionally further include: the memory material is a spontaneous polarization material (e.g., a residual polarization material).

[0423] Example 69 is a memory cell comprising: a field effect transistor structure; a first control node and a second control node; a first capacitor structure comprising a first electrode connected to the first control node, a second electrode connected to a gate region of the field effect transistor structure, and a spontaneous polarization region (e.g., a residual polarization region) disposed between the first electrode and the second electrode of the first capacitor structure; and a second capacitor structure (e.g., a lever capacitor structure) comprising a first electrode connected to the second control node, a second electrode connected to the gate region of the field effect transistor structure. The first capacitor structure may have a first capacitance and the second capacitor structure may have a second capacitance different from the first capacitance. An electrical isolation region may be disposed between the first electrode and the second electrode of the second capacitor structure.

[0424] In Example 70, the memory cell of Example 69 may optionally further include: a third control node (e.g., a first source / drain node) coupled to a first region (e.g., a first source / drain region) of the field effect transistor structure and a fourth control node (e.g., a second source / drain node) coupled to a second region (e.g., a second source / drain region) of the field effect transistor structure.

[0425] In Example 71, the memory cell of Example 69 or 70 may optionally further include: the second capacitance is greater than the first capacitance. The second capacitance may be twice as large as the first capacitance. The second capacitance may be five times or ten times as large as the first capacitance. The second capacitance may be fifty times or thirty times smaller than the first capacitance.

[0426] In Example 72, the memory cell of any one of Examples 69 to 71 optionally further includes: the first capacitor structure having a first effective capacitor area and the second capacitor structure having a second effective capacitor area different from the first effective capacitor area.

[0427] In Example 73, the memory cell of any one of Examples 69 to 72 may optionally further include: two electrodes of the first capacitor structure have a first distance from each other, and wherein the two electrodes of the second capacitor structure have a second distance from each other that is different from the first distance.

[0428] In Example 74, the memory cell of any one of Examples 69 to 73 may optionally further include: the spontaneous polarization region (e.g., the residual polarization region) of the first capacitor structure includes or is composed of the first material, and wherein the electrical isolation region of the second capacitor structure includes or is composed of a second material different from the first material.

[0429] In Example 75, the memory cell of any one of Examples 69 to 74 may optionally further include: the spontaneous polarization region (e.g., the residual polarization region) of the first capacitor structure includes or is composed of a material having a first relative dielectric constant, and wherein the electrical isolation region of the second capacitor structure includes or is composed of a material having a second relative dielectric constant different from the first relative dielectric constant.

[0430] In Example 76, the memory cell of any one of Examples 69 to 75 may optionally further include: a spontaneous polarization region (eg, a remnant polarization region) in direct physical contact with both the first electrode of the first capacitor structure and the second electrode of the first capacitor structure.

[0431] In Example 77, the memory cell of any one of Examples 69 to 76 may optionally further include: the electrical isolation region includes or consists of a dielectric material.

[0432] In Example 78, the memory cell of any one of Examples 69 to 77 may optionally further include: the electrically isolated region is free of spontaneous polarization material (eg, remanent polarization material).

[0433] In Example 79, the memory cell of any one of Examples 69 to 78 may optionally further include: the electrically isolated region being in direct physical contact with both the first electrode of the second capacitor structure and the second electrode of the second capacitor structure.

[0434] In Example 80, the memory cell of any one of Examples 69 to 79 may optionally further include: the second capacitor structure is a three-dimensional capacitor structure. The three-dimensional capacitor structure may include at least one curved and / or angled portion.

[0435] In Example 81, the memory cell of any one of Examples 69 to 80 may optionally further include: the second capacitor structure includes a plurality of capacitors coupled in parallel to each other.

[0436] In Example 82, the memory cell of any one of Examples 69 to 81 may optionally further include: the field effect transistor structure has a third capacitance associated therewith, and the second capacitance is greater than the third capacitance. The second capacitance may be twice as large as the third capacitance. The second capacitance may be five times as large as the third capacitance. The second capacitance may be ten times as large as the third capacitance. The second capacitance may be fifty times or thirty times smaller than the third capacitance.

[0437] In Example 83, the memory cell of any one of Examples 69 to 82 may optionally further include: the field effect transistor structure has a third capacitance, and the sum of the second capacitance and the third capacitance is greater than the first capacitance. The sum of the second capacitance and the third capacitance may be twice greater than the first capacitance. The sum of the second capacitance and the third capacitance may be five times greater than the first capacitance. The sum of the second capacitance and the third capacitance may be ten times greater than the first capacitance. The sum of the second capacitance and the third capacitance may be fifty times or thirty times smaller than the first capacitance.

[0438] In Example 84, the memory cell of any one of Examples 69 to 83 may optionally further include: the second capacitor structure is configured as a linear capacitor. A linear capacitor may have a linear dependence in current-voltage characteristics, ie, a linear IV curve.

[0439] Example 85 is a memory cell arrangement comprising: a plurality of memory cells, each of the plurality of memory cells being configured as a memory cell as in any one of Examples 69 to 84; the memory cell arrangement may further comprise one or more first control lines (e.g., word lines) and one or more second control lines (e.g., lever lines), the first control line being connected to a first control node of each memory cell in a first subset of one or more memory cells in the plurality of memory cells, and the second control line being connected to a second control node of each memory cell in a second subset of one or more memory cells in the plurality of memory cells.

[0440] Example 86 is a memory cell arrangement comprising: a plurality of memory cells, each memory cell in the plurality of memory cells comprising: a field effect transistor structure; a first control node; a first capacitor structure connected to the first control node and a gate region of the field effect transistor; a second control node; and a second capacitor structure connected to the second control node and the gate region of the field effect transistor; one or more first control lines (e.g., word lines) connected to the first control node of each memory cell in a first subset of one or more memory cells in the plurality of memory cells; and one or more second control lines (e.g., lever lines, e.g., other word lines) connected to the second control node of each memory cell in a second subset of one or more memory cells in the plurality of memory cells. Each first subset of the one or more memory cells in the first subset may be different from (not equal to, i.e., not including the same memory cells) each subset of the one or more memory cells in the second subset.

[0441] In Example 87, the memory cell arrangement of Example 85 or 86 may optionally further include: memory cells in the plurality of memory cells being in a NOR configuration.

[0442] In Example 88, the memory cell arrangement of Example 87 may optionally further include: each of the multiple memory cells also includes: a third control node (e.g., a first source / drain node) coupled to a first region (e.g., a first source / drain region) of the field effect transistor structure and a fourth control node (e.g., a second source / drain node) coupled to a second region (e.g., a second source / drain region) of the field effect transistor structure.

[0443] In Example 89, the memory cell arrangement of Example 87 or 88 may optionally further include: one or more third control lines (e.g., bit lines) connected to a third control node of each memory cell in the first subset of the one or more memory cells. Each of the one or more third control lines may connect the first region of each memory cell in the corresponding first subset of memory cells.

[0444] In Example 90, the memory cell arrangement of any one of Examples 87 to 89 may optionally further include: a fourth control node of each memory cell in the plurality of memory cells being connected to a common control node (eg, a common source node).

[0445] In Example 91, the memory cell arrangement of any one of Examples 87 to 90 may optionally further include: a control circuit configured to write to a selected memory cell among the plurality of memory cells. Writing to the selected memory cell may include providing a write voltage (e.g., V FE，ACT =V PP Writing to a selected memory cell may include providing a first (active) lever voltage (eg, V LE，ACT =V SS ). Write voltage (for example, V FE，ACT =V PP ) may be different from the first (active) lever voltage (first V LE，ACT =V SS ) voltage value.

[0446] In Example 92, the memory cell arrangement of Example 91 may optionally include: a write voltage (eg, V FE，ACT =V PP ) and the first (active) lever voltage (|V LE，ACT |) can be bipolar (e.g., opposite in sign). The write voltage (e.g., V FE，ACT =V PP ) may have a positive voltage value, and the first (active) lever voltage (V LE，ACT) can have negative voltage values ​​and vice versa.

[0447] In Example 93, the memory cell arrangement of Example 87 and Example 91 or 92 may optionally further include: writing to the selected memory cell further includes: setting the first control voltage (V BL，ACT =V SS ) is provided to a third control line (e.g., a bit line) connected to a third control node of the selected memory cell.

[0448] In Example 94, the memory cell arrangement of any one of Examples 93 may optionally further include: an absolute voltage value of the write voltage (eg, |V FE，ACT |=|V PP |) is greater than the first control voltage (e.g., |V BL，ACT |=|V SS |)’s absolute voltage value.

[0449] In Example 95, the memory cell arrangement of Example 93 or 94 may optionally further include: a voltage value of the first control voltage (eg, |V BL，ACT |=|V SS |) is substantially equal to the base voltage (e.g., V SS =0V).

[0450] In Example 96, the memory cell arrangement of any one of Examples 91 and Examples 92 to 95 may optionally further include: writing to the selected memory cell further includes: providing a second control voltage (V SL，ACT =V SS ).

[0451] In Example 97, the memory cell arrangement of Example 96 may optionally further include: an absolute voltage value of the write voltage (eg, |V FE，ACT |=|V PP |) is greater than the absolute voltage value of the second control voltage (for example, |V SL，ACT |=|V SS |).

[0452] In Example 98, the memory cell arrangement of Example 96 or 97 may optionally further include: a voltage value of the second control voltage (eg, |V SL，ACT |=|V SS |) is substantially equal to the base voltage (e.g., V SS =0V).

[0453] In Example 99, the memory cell arrangement of any one of Examples 91 to 98 may optionally further include: an absolute voltage value of the write voltage (eg, |V FE，ACT |=|V PP|) is greater than the absolute voltage value of the first (active) lever voltage (e.g., |V LE，ACT |=|V SS |).

[0454] In Example 100, the memory cell arrangement of any one of Examples 91 to 99 may optionally further include: setting a second (inactive) lever voltage (eg, |V LE，PAS |) is applied to a second control line connected to the (lever) capacitor of non-selected memory cells of the memory cell arrangement that share the same first control line as the selected memory cell. A second (passive) lever voltage (e.g., |V LE，PAS |) can be equal to or greater than the base voltage (e.g., |V FE，ACT |≥V SS ).

[0455] In Example 101, the memory cell arrangement of any one of Examples 91 to 100 may optionally further include: a first (active) lever voltage (eg, V LE，ACT =V SS ) is equal to or substantially equal to the base voltage (e.g., V SS =0V). The absolute voltage value of the first (active) lever voltage (eg, |V LE，ACT |) may be equal to or less than half the absolute voltage value of the write voltage (e.g., |V FE，ACT |=1 / 2*|V PP |).

[0456] In Example 102, the memory cell arrangement of any one of Examples 91 to 101 may optionally further include: the control circuit is further configured to prevent writing to one or more non-selected memory cells of the plurality of memory cells during writing to the selected memory cell. FE，ACT =V PP ) is provided to a first control line (e.g., a word line) connected to a first control node of the non-selected memory cells, preventing writing to one or more non-selected memory cells may include providing a second (inactive) lever voltage (V LE，PAS ). The second (passive) lever voltage (V LE，PAS ) may be different from the voltage value of the first (active) lever voltage (eg, V LE，ACT =V SS ).

[0457] In Example 103, the memory cell arrangement of Example 102 may optionally include: a first (active) lever voltage (|V LE，ACT |) and the second (passive) lever voltage (VLE，PAS ) can be bipolar (eg, opposite in sign). The first (active) lever voltage (V LE，ACT ) may have a positive voltage value, and the second (passive) lever voltage (V LE，PAS ) can have negative voltage values ​​and vice versa.

[0458] In Example 104, the memory cell arrangement of Example 102 or 103 may optionally further include: an absolute voltage value of the second (inactive) lever voltage (|V LE，PAS |) is equal to or less than the absolute voltage value of the write voltage (for example, |V FE，ACT |=|V PP |); and / or the absolute voltage value of the second (passive) lever voltage (|V LE，PAS |) is equal to or greater than half the absolute voltage value of the write voltage (for example, |V FE，ACT | / 2=|V PP | / 2).

[0459] In Example 105, the memory cell arrangement of any one of Examples 91 to 104 may optionally further include: the control circuit is further configured to prevent writing to one or more non-selected memory cells in the plurality of memory cells during writing to the selected memory cell. Preventing writing to the one or more non-selected memory cells may include providing a prohibition voltage (V FE，PAS ). Prohibition voltage (V FE，PAS ) may be different from the voltage value of the write voltage (eg, V FE，ACT =V PP ).

[0460] In Example 106, the memory cell arrangement of Example 105 may optionally include: a prohibition voltage (V FE，PAS ) and the write voltage (e.g., V FE，ACT ) can be bipolar (e.g., opposite in sign). FE，PAS ) can have a positive voltage value, and a write voltage (e.g., V FE，ACT ) can have negative voltage values ​​and vice versa.

[0461] In Example 107, the memory cell arrangement of Example 105 or 106 may optionally further include: an absolute voltage value of the prohibition voltage value (|V FE，PAS |) is equal to or less than half the absolute voltage value of the write voltage - (for example, |V FE，ACT | / 2=|V PP | / 2); and / or the absolute voltage value of the prohibited voltage value (|V FE，PAS|) is equal to or greater than the base voltage (e.g., V SS =0V).

[0462] In Example 108, the memory cell arrangement of any one of Examples 87 to 107 may optionally further include: a control circuit configured to read a selected memory cell from the plurality of memory cells. Reading the selected memory cell may include providing a read voltage (e.g., V FE，ACT =V G ). Reading the selected memory cell may include providing a first (active) lever voltage (eg, V LE，ACT =V G ).

[0463] In Example 109, the memory cell arrangement of Example 108 may optionally include: a read voltage (eg, V FE，ACT =V G ) and the first (active) lever voltage (|V LE，ACT )|) can be bipolar (e.g., opposite in sign). Reading a voltage (e.g., V FE，ACT =V G ) may have a positive voltage value, and the first (active) lever voltage (|V LE，ACT |) can have a negative voltage value and vice versa.

[0464] In Example 110, the memory cell arrangement of Example 108 or 109 may optionally further include: a read voltage (eg, V FE，ACT =V G ) has a voltage value substantially the same as the voltage value of the first (active) lever voltage (e.g., V LE，ACT =V G ). The absolute voltage value of the first (active) lever voltage (|V LE，ACT |) may be equal to or greater than half the absolute voltage value of the first (active) lever voltage (e.g., |V LE，ACT |=>1 / 2*|V G |).

[0465] In Example 111, the memory cell arrangement of Examples 87 and 110 or Examples 87 and 126 may optionally further include: reading the selected memory cell further includes: setting the first control voltage (eg, V BL，ACT >V SS ) is provided to a third control line (e.g., a bit line) connected to a third control node of the selected memory cell.

[0466] In Example 112, the memory cell arrangement of Example 111 may optionally further include: an absolute voltage value of the first control voltage (|V BL，ACT |) is greater than the base voltage (e.g., V SS =0V).

[0467] In Example 113, the memory cell arrangement of any one of Examples 87 and Examples 109 to 112 may optionally further include: reading the selected memory cell further includes: providing a second control voltage (V SL，ACT =V SS ). The second control voltage (eg, V SL，ACT =V SS ) may be equal to or substantially equal to the base voltage (e.g., V SS =0V).

[0468] In Example 114, the memory cell arrangement of Example 113 may optionally further include: a second control voltage (|V SL，ACT ||) is equal to or greater than the base voltage (e.g., |V SL，ACT |=>V SS ).

[0469] In Example 115, the memory cell arrangement of any one of Examples 109 to 114 may optionally further include: the control circuit is further configured to prevent interference caused by one or more non-selected memory cells in the plurality of memory cells during reading of the selected memory cell. FE，ACT =V G ) is provided to a first control line (e.g., a word line) connected to a first control node of a non-selected memory cell, preventing interference may include providing a second (inactive) lever voltage (V LE，PAS ). The second (passive) lever voltage (V LE，PAS ) may be different from the voltage value of the first (active) lever voltage (eg, V LE，ACT =V SS ).

[0470] In Example 116, the memory cell arrangement of Example 115 may optionally include: a first (active) lever voltage (|V LE，ACT |) and the second (passive) lever voltage (V LE，PAS ) can be bipolar (eg, opposite in sign). The first (active) lever voltage (V LE，ACT ) may have a positive voltage value, and the second (passive) lever voltage (V LE，PAS ) can have negative voltage values ​​and vice versa.

[0471] In Example 117, the memory cell arrangement of Example 115 or 116 may optionally further include: an absolute voltage value of the second (inactive) lever voltage (|V LE，PAS |) is equal to or less than half of the absolute voltage value of the read voltage (e.g., |V FE，ACT | / 2=|V G | / 2); and / or the absolute voltage value of the second (passive) lever voltage (|V LE，PAS |) is equal to or greater than the base voltage (e.g., V SS =0V).

[0472] In Example 118, the memory cell arrangement of any one of Examples 109 to 117 may optionally further include: the control circuit is further configured to prevent interference caused by one or more non-selected memory cells in the plurality of memory cells during reading of the selected memory cell. Preventing interference may include providing a prohibition voltage (V FE，PAS ). Prohibition voltage (V FE，PAS ) may be different from the voltage value of the read voltage (eg, V FE，ACT =V G ).

[0473] In Example 119, the memory cell arrangement of Example 118 may optionally further include: an absolute voltage value of the prohibition voltage value (|V FE，PAS |) is equal to or less than half the absolute voltage value of the read voltage (e.g., |V FE，ACT | / 2=|V G | / 2); and / or the absolute voltage value of the prohibited voltage value (|V FE，PAS |) is equal to or greater than the base voltage (e.g., V SS =0V).

[0474] In Example 120, the memory cell arrangement of Examples 87 and 1|9 or Examples 87 and 134 may optionally further include: preventing interference further includes: setting the first control voltage (eg, V BL，PAS =V SS ) is provided to a third control line (e.g., a bit line) connected to a third control node of the selected memory cell.

[0475] In Example 121, the memory cell arrangement of Example 120 may optionally further include: a first control voltage (V BL，PAS ) is substantially equal to the base voltage (e.g., V SS =0V).

[0476] In Example 122, the memory cell arrangement of any one of Examples 118 to 121 may optionally further include: reading the selected memory cell further includes: providing a second control voltage (V SL，PAS =V SS ).

[0477] In Example 123, the memory cell arrangement of Example 122 may optionally further include: a second control voltage (eg, VS L，PAS =V SS ) is substantially equal to the base voltage (e.g., V SS =0V).

[0478] In Example 124, the memory cell arrangement of any one of Examples 119 to 124 may optionally include: a prohibition voltage (V FE，PAS ) and read voltage (e.g., V FE，ACT ) can be bipolar (e.g., opposite in sign). FE，PAS ) can have a positive voltage value, and read voltage (e.g., V FE，ACT ) can have negative voltage values ​​and vice versa.

[0479] Example 125 is a method according to various aspects, such as a method for operating (eg, writing to) a memory cell. The method may include: applying a write voltage (V PP ), the first control node is connected to the first capacitor (e.g., to the ferroelectric capacitor FE) or the first memory element of the memory cell; the lever voltage (e.g., a voltage lower than the write voltage, e.g., equal to or close to V SS ) is applied to a second control node of the memory cell, the second control node is connected to a second capacitor (e.g., a lever capacitor LE, such as a ferroelectric or dielectric capacitor) of the memory cell; and a bit line voltage (e.g., a voltage lower than the write voltage, such as equal to or close to V) is applied to a third control node of the memory cell. SS The third control node is connected to the source / drain region of the transistor (eg, field effect transistor FT) of the memory cell.

[0480] Example 126 is a method according to various aspects, such as a method for operating (eg, reading) a memory cell. The method may include applying a read voltage (V G ), the first control node is connected to the first capacitor (eg, to the ferroelectric capacitor FE) or the first memory element of the memory cell; the lever voltage (eg, greater than V SSThe voltage, for example, is equal to or close to the read voltage V G A voltage of the read voltage (e.g., a voltage lower than the read voltage) is applied to a second control node of the memory cell, the second control node is connected to a second capacitor (e.g., a lever capacitor LE, such as a ferroelectric or dielectric capacitor) of the memory cell; and a bit line voltage (e.g., a voltage lower than the read voltage) is applied to a third control node of the memory cell, the third control node is connected to the source / drain region of a transistor (e.g., a field effect transistor FT) of the memory cell.

[0481] Example 127 is a method according to various aspects, such as a method for operating (e.g., reading and writing) a memory cell. The method may include: reading the memory cell and writing the memory cell, wherein reading the memory cell includes: applying a read voltage (V G ), the first control node is connected to the first capacitor (eg, to the ferroelectric capacitor FE) or the first memory element of the memory cell; the first lever voltage (eg, greater than V SS The voltage, for example, is equal to or close to the read voltage V G ) is applied to a second control node of the memory cell, the second control node being connected to a second capacitor (e.g., a lever capacitor LE, e.g., a ferroelectric or dielectric capacitor) of the memory cell; and wherein writing to the memory cell comprises applying a write voltage (V PP ) and applying a second lever voltage different from the first lever voltage (eg, a voltage lower than the write voltage, eg, equal to or close to V SS voltage).

[0482] In Example 128, the method of Example 127 may optionally further include applying a bit line voltage (e.g., a voltage lower than the read voltage) to a third control node of the memory cell, the third control node being connected to a source / drain region of a transistor (e.g., a field effect transistor FT) of the memory cell.

[0483] In Example 129, the method of Example 128 may optionally further include: applying a bit line voltage (eg, a voltage lower than the write voltage, eg, equal to or close to V SS voltage).

[0484] In Example 130, the memory cell arrangement of Example 85 or 86 may optionally further include: memory cells in the plurality of memory cells being in a NAND configuration.

[0485] In Example 131, the memory cell arrangement of Example 130 may optionally further include: each field effect transistor structure includes a first region (e.g., to a first source / drain region) and a second region (e.g., to a second source / drain region), and the memory cell arrangement further includes: one or more third control lines (e.g., bit lines, such as source / drain lines), including a series connection of corresponding first and second regions of corresponding memory cells in the first subset of one or more memory cells.

[0486] In Example 132, the memory cell arrangement of Example 130 or 131 may optionally further include: two corresponding adjacent memory cells in each of the first subset of one or more memory cells are connected to the second region at the first region.

[0487] In Example 133, the memory cell arrangement of Examples 130 to 132 may optionally further include: two corresponding adjacent memory cells in each memory cell in the first subset of one or more memory cells include a shared first / second region, including a first region of a field effect transistor structure and a second region of another field effect transistor structure.

[0488] In Example 134, the memory cell arrangement of Examples 130 to 133 may optionally further include: a third control node and a fourth control node connected to a corresponding third control line of the one or more third control lines. Each third control node may be connected to a first region of each field effect transistor structure associated with the third control node of the first subset of memory cells. Each fourth control node may be connected to a second region of each field effect transistor structure associated with the fourth control node of the first subset of memory cells.

[0489] In Example 135, the memory cell arrangement of any one of Examples 130 to 134 may optionally further include: a control circuit configured to write to a selected memory cell among the plurality of memory cells. Writing to the selected memory cell may include providing a write voltage (e.g., V FE，ACT =V PP Writing to a selected memory cell may include providing a first (active) lever voltage (eg, V LE，ACT =V SS ). Write voltage (for example, V FE，ACT =V PP ) may be different from the first (active) lever voltage (first V LE，ACT =V SS ) voltage value.

[0490] In Example 136, the memory cell arrangement of Example 135 may optionally include: a write voltage (eg, V FE，ACT =V PP ) and the first (active) lever voltage (V LE，ACT ) can be bipolar (eg, opposite in sign). The write voltage (eg, V FE，ACT =V PP ) may have a positive voltage value, and the first (active) lever voltage (V LE，ACT ) can have negative voltage values ​​and vice versa.

[0491] In Example 137, the memory cell arrangement of Example 130 and Example 135 or Example 136 may optionally further include: writing to the selected memory cell also includes: providing a prohibition voltage at each first control line so that the memory state of the memory cells in the first subset of other memory cells is not changed (for example, neither written nor erased).

[0492] In Example 138, the memory cell arrangement of Examples 130 and 137 may optionally also include: writing to the selected memory cell also includes: providing a control voltage to a third control node corresponding to a third control line (e.g., a bit line), and applying a control voltage to a fourth control node corresponding to the third control line of the selected memory cell.

[0493] In Example 139, the memory cell arrangement of Example 138 may optionally further include: a voltage value of the control voltage being substantially equal to the base voltage (eg, V SS =0V).

[0494] In Example 140, the memory cell arrangement of any one of Examples 130 to 139 may optionally further include: an absolute voltage value of the write voltage (eg, |V FE，ACT |=|V PP |) is greater than the absolute voltage value of the first (active) lever voltage (e.g., |V LE，ACT |=|V SS |).

[0495] In Example 141, the memory cell arrangement of any one of Examples 130 to 140 may optionally further include: setting a second (inactive) lever voltage (eg, |V LE，PAS |) is applied to a second control line connected to the (lever) capacitor of non-selected memory cells of the memory cell arrangement that share the same first control line as the selected memory cell. A second (passive) lever voltage (e.g., |V LE，PAS |) can be equal to or greater than the base voltage (e.g., |V FE，ACT |≥VSS ).

[0496] In Example 142, the memory cell arrangement of any one of Examples...

Claims

1. A memory cell arrangement comprising: One or more memory cells, each of the one or more memory cells comprising: Field effect transistor structure; a plurality of first control nodes; a plurality of first capacitor structures, each of the plurality of first capacitor structures comprising a first electrode connected to a corresponding first control node of the plurality of first control nodes, a second electrode connected to a gate region of the field effect transistor structure, and a spontaneous polarization region disposed between the first electrode and the second electrode of the first capacitor structure; A second control node; a second capacitor structure comprising a first electrode connected to the second control node and a second electrode connected to the gate region of the field effect transistor; and A control circuit configured to read a selected first capacitor structure of a selected memory cell among the one or more memory cells; wherein reading the selected first capacitor structure comprises: providing a read voltage to a first control line connected to a first control node of the selected first capacitor structure of the selected memory cell; and providing a first lever voltage to a second control line connected to a second control node of the selected memory cell, wherein the control circuit is further configured to prevent interference caused by a non-selected first capacitor structure of the selected memory cell during reading of the selected first capacitor structure of the selected memory cell, wherein preventing the interference comprises: A first inhibit voltage is provided to each first control line connected to the first control nodes of the non-selected first capacitor structures of the selected memory cell.

2. The memory cell arrangement according to claim 1, in, Each first capacitor structure of the plurality of first capacitor structures is configured to be in one of at least two memory states.

3. The memory cell arrangement according to claim 1, in, Each first capacitor structure of the plurality of first capacitor structures has a respective first capacitance, and wherein the second capacitor structure has a second capacitance different from one or more of the first capacitances.

4. The memory cell arrangement according to claim 1, Each of the one or more memory cells further comprises: A third control node is coupled to the first region and / or the second region of the field effect transistor structure.

5. The memory cell arrangement according to claim 1, in, The one or more memory cells are a plurality of memory cells, the memory cell arrangement further comprising: a plurality of first control lines, including a first subset of one or more first control lines, each first control line in a first subset of the one or more first control lines being connected to a corresponding first control node of a first subset of memory cells in the plurality of memory cells; and One or more second control lines are connected to a second control node of each memory cell in a second subset of memory cells in the plurality of memory cells.

6. The memory cell arrangement of claim 5 , further comprising: One or more third control lines are connected to a third control node of each memory cell in a corresponding first subset of the one or more memory cells, wherein the third control node is coupled to the first region and / or the second region of the corresponding field effect transistor structure.

7. The memory cell arrangement according to claim 1, wherein the control circuit is further configured to write to a selected first capacitor structure of a selected memory cell of the plurality of memory cells; in, Writing to the selected first capacitor structure includes: providing a write voltage to a first control line connected to a first control node of the selected first capacitor structure of the selected memory cell; and A first lever voltage is provided to a second control line connected to a second control node of the selected memory cell.

8. The memory cell arrangement according to claim 7, Each of the one or more memory cells further comprises: a third control node coupled to the first region and / or the second region of the field effect transistor structure; Wherein, writing the selected first capacitor structure of the selected memory cell further comprises: A first control voltage is provided to a third control line connected to a third control node of the selected memory cell.

9. The memory cell arrangement according to claim 7, in, The control circuit is further configured to prevent writing to unselected first capacitor structures of the selected memory cell during writing to the selected first capacitor structure of the selected memory cell, wherein preventing writing to the unselected first capacitor structures comprises: A first inhibit voltage is provided to each of the first control lines connected to the first control nodes of the non-selected first capacitor structures of the selected memory cell.

10. The memory cell arrangement according to claim 7, in, The control circuit is further configured to prevent writing to the first capacitor structure of one or more non-selected memory cells of the plurality of memory cells during writing to the selected first capacitor structure of the selected memory cell, wherein preventing writing to the one or more non-selected memory cells comprises: In the case where the write voltage is supplied to a first control line connected to a first control node of the non-selected memory cell, a second lever voltage is supplied to a second control line connected to a second control node of the non-selected memory cell, wherein a voltage value of the second lever voltage is different from a voltage value of the first lever voltage.

11. The memory cell arrangement according to claim 7, in, The control circuit is further configured to prevent writing to the first capacitor structure of one or more non-selected memory cells of the plurality of memory cells during writing to the selected first capacitor structure of the selected memory cell, wherein preventing writing to the one or more non-selected memory cells comprises: A second inhibit voltage is provided to one or more first control lines connected to the first control nodes of the non-selected memory cells, wherein a voltage value of the second inhibit voltage is different from a voltage value of the write voltage.

12. The memory cell arrangement according to claim 1, Each of the one or more memory cells further comprises: a third control node coupled to the first region and / or the second region of the field effect transistor structure; Wherein, reading the selected first capacitor structure of the selected memory cell further comprises: A first control voltage is provided to a third control line connected to a third control node of the selected memory cell.

13. The memory cell arrangement according to claim 1, in, The control circuit is further configured to prevent disturbance caused by the first capacitor structure of one or more non-selected memory cells of the plurality of memory cells during reading of the selected first capacitor structure of the selected memory cell, wherein preventing the disturbance comprises: In a case where the read voltage is supplied to a first control line connected to a first control node of the non-selected memory cell, a second lever voltage is supplied to a second control line connected to a second control node of the non-selected memory cell, wherein a voltage value of the second lever voltage is different from a voltage value of the first lever voltage.

14. The memory cell arrangement according to claim 1, in, The control circuit is further configured to prevent disturbance caused by the first capacitor structure of one or more non-selected memory cells of the plurality of memory cells during reading of the selected first capacitor structure of the selected memory cell, wherein preventing the disturbance comprises: A second inhibit voltage is provided to one or more first control lines connected to the first control nodes of the non-selected memory cells, wherein a voltage value of the second inhibit voltage is different from a voltage value of the read voltage.

15. A method of operating a memory cell in a memory cell arrangement according to any one of claims 1 to 14, the method comprising: applying a control voltage to a corresponding first control node selected from the plurality of first control nodes of the memory cell via a corresponding word line, each of the plurality of first control nodes being connected to a corresponding first capacitor structure of the plurality of first capacitor structures of the memory cell; applying the first lever voltage to the second control node of the memory cell via a corresponding lever line, the second control node being connected to the second capacitor structure of the memory cell; applying a bit line voltage to a third control node of the memory cell, the third control node being connected to at least one source / drain region of the field effect transistor of the memory cell; as well as A first inhibit voltage is applied to a first control line connected to a first control node of the non-selected first capacitor structure to prevent disturbance caused by the non-selected first capacitor structure during reading of the corresponding first capacitor structure of the memory cell.

16. The method according to claim 15, in, The control voltage is a write voltage or a read voltage.

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