Computing system and method of operating the same

Abstract

The present disclosure relates to a computing system, including: a memory device including a plurality of memory cells; a memory controller configured to control the memory device; and a host configured to detect an error occurring in a first memory cell of the memory device while performing an operation corresponding to a workload, and transmit a target address corresponding to the first memory cell and a request for performing a test operation on an adjacent memory cell adjacent to the first memory cell to the memory controller. The memory controller controls the memory device to perform a test operation on the adjacent memory cell by using at least one of a built-in self-test (BIST) engine or a scrubbing engine based on the target address, and generates memory error information including information associated with a second memory cell in which an error occurs, the second memory cell being one of the adjacent memory cells. The host controls access to the second memory cell based on the memory error information.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent document claims priority to and the benefit of Korean Patent Application No. 10-2020-0143524, filed on October 30, 2020, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The techniques and embodiments disclosed in this patent document relate generally to an electronic device, and more particularly, to a computing system and method of operating the same. Background Art

[0004] A storage device refers to an electronic component configured to store data permanently or temporarily. Each storage device may include one or more storage media to store data and operate based on a request from a host device that includes a processor that reads data from or writes data to a storage device such as a computer or a smart phone. A storage device may include a storage medium for storing data, and may further include a memory controller for controlling the storage medium to store or retrieve data. Storage devices may be classified based on the type of storage medium. For example, memory devices used as storage media are classified into volatile memory devices and non-volatile memory devices.

[0005] A volatile memory device can store data only when powered. Therefore, such a volatile memory device loses its data when there is no power. Examples of volatile memory devices include static random access memory (SRAM) or dynamic random access memory (DRAM).

[0006] A non-volatile memory device can retain its data without power. Examples of non-volatile memory devices include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEROM), or flash memory. Summary of the invention

[0007] The embodiment provides a computing system capable of preemptively blocking access to a memory cell in which an error occurs and an operating method of the computing system.

[0008] According to one aspect of the disclosed technology, a computing system is provided, comprising: a memory device including a plurality of memory cells for storing data; a memory controller communicating with the memory device and configured to control the memory device; and a host communicating with the memory controller for reading data in the memory device or writing data to the memory device, and configured to detect an error occurring in a first memory cell of the memory device while performing an operation corresponding to a workload, and transmit to the memory controller i) a target address corresponding to the first memory cell and ii) a request for performing a test operation on a neighboring memory cell adjacent to the first memory cell; and wherein the memory controller is further configured to control the memory device to perform the test operation on the neighboring memory cell by using at least one of a built-in self-test (BIST) engine or a scrubbing engine based on the target address, and generate memory error information including information associated with a second memory cell in which an error occurs, the second memory cell being one of the neighboring memory cells, and wherein the host is further configured to control access to the second memory cell based on the memory error information.

[0009] According to another aspect of the disclosed technology, a method for operating a computing system is provided, comprising: detecting, by a host communicating with a storage device, an error occurring in a first memory unit included in the memory device, the storage device comprising a memory device and a memory controller configured to control the memory device, the memory device comprising one or more memory units; setting an operation mode of the host to a system management mode; transmitting to the memory controller a target address corresponding to the first memory unit and a request for a test operation on an adjacent memory unit adjacent to the first memory unit; receiving memory error information from the memory controller, the memory error information being based on a result of the test operation and including information associated with a second memory unit in which an error occurred, the second memory unit being one of the adjacent memory units; and enabling or disabling access to the second memory unit based on the memory error information.

[0010] According to another aspect of the disclosed technology, a data storage device is provided, comprising: a memory device including a plurality of memory cells for storing data; a memory controller communicating with the memory device and configured to control the memory device, the memory controller being configured to communicate with a host device external to the data storage device to receive information about an error occurring in a first memory cell of the memory device from the host device, the information comprising a target address corresponding to the first memory cell and a request for a test operation on an adjacent memory cell adjacent to the first memory cell, and wherein the memory controller is configured to control the memory device to perform a test operation on the adjacent memory cell based on the target address, and to generate memory error information including information associated with a second memory cell in which an error occurs, the second memory cell being one of the adjacent memory cells, and wherein the memory controller is configured to communicate the memory error information to the host device, and the host device further controls access to the second memory cell based on the memory error information.

[0011] The memory controller may include: a test operation controller configured to control the memory device to perform a test operation in response to a request for a test operation; and an error information storage device configured to store memory error information.

[0012] The test operation controller may store data, which has been stored in an adjacent memory cell, in an empty memory cell among the plurality of memory cells.

[0013] The test operation controller may control the test operation by using at least one of a built-in self test (BIST) engine or a scrubbing engine.

[0014] The test operation controller may use the BIST engine to perform a test operation including operations of programming test data to adjacent memory cells, reading data from the programmed memory cells, and comparing the test data with the read data.

[0015] The test operation controller may control the test operation by using the scrubbing engine, and the test operation includes reading data from adjacent memory cells and detecting an error of the read data by using an error correction code (ECC).

[0016] The memory error information may include: error type information including information on the type of the error; and address information including an address of the second memory unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art.

[0018] In the accompanying drawings, the dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intermediate elements may also be present. Throughout the specification, the same reference numerals refer to the same elements.

[0019] Figure 1 is a diagram illustrating a computing system according to an embodiment of the disclosed technology.

[0020] Figure 2 is a diagram illustrating an example of a test operation according to an embodiment of the disclosed technology.

[0021] Figure 3 is a flow chart illustrating an example of a testing operation according to an embodiment of the disclosed technology.

[0022] Figure 4 is a diagram illustrating another example of a test operation according to an embodiment of the disclosed technology.

[0023] Figure 5 is a flowchart illustrating another example of a test operation according to an embodiment of the disclosed technology.

[0024] Figure 6 is a diagram illustrating another example of a test operation according to an embodiment of the disclosed technology.

[0025] Figure 7 is a flowchart illustrating another example of a test operation according to an embodiment of the disclosed technology.

[0026] Figure 8 is a flow chart illustrating a method of operation of a computing system according to an embodiment of the disclosed technology.

[0027] Fig. 9 is a flowchart illustrating an example of a method for performing a test operation according to an embodiment of the disclosed technology.

[0028] Fig.10 is a flowchart illustrating another example of a method for performing a test operation according to an embodiment of the disclosed technology.

[0029] Fig.11 It is shown Figure 1 A diagram of a memory controller is shown. DETAILED DESCRIPTION

[0030] The specific structural features or functions disclosed herein are merely illustrative examples for specific embodiments or implementations of the disclosed technology, and the implementations of the disclosed technology are not limited to those specific examples.

[0031] Figure 1 is a diagram illustrating a computing system according to an embodiment of the disclosed technology.

[0032] Reference Figure 1 , the computing system 10 may include a storage device 50 and a host 300 .

[0033] The storage device 50 may include a memory device 100 and a memory controller 200 for controlling the operation of the memory device 100. The storage device 50 may be a device for storing data under the control of a host 300. The host 300 is communicatively coupled with the memory controller for reading data from the memory device or writing data to the memory device, and includes one or more processors as a computing device, such as a mobile phone, a smart phone, an MP3 player, a laptop computer, a desktop computer, a game console, a smart TV, a tablet PC, or an in-vehicle infotainment system.

[0034] The memory device 100 may store data. The memory device 100 operates under the control of the memory controller 200. The memory device 100 may include a plurality of memory banks for storing data. Each of the plurality of memory banks may include a memory cell array (not shown) including a plurality of memory cells.

[0035] Each of the memory cells may be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a triple-level cell (TLC) storing three data bits, or a quad-level cell (QLC) storing four data bits.

[0036] The memory cell array (not shown) may include a plurality of memory blocks. Each memory block may include a plurality of memory cells. A memory block may include a plurality of pages. In an embodiment, a page may be a unit for storing data in the memory device 100 or reading data stored in the memory device 100. A memory block may be a unit for erasing data.

[0037] The memory device 100 may be a volatile random access memory, such as a dynamic random access memory (DRAM), a synchronous RAM (SDRAM), a double data rate SDRAM (DDR SDRAM), a DDR2 SDRAM, a DDR3 SDRAM, a low power DDR (LPDDR) SDRAM, or a LPDDR2 SDRAM or a LPDDR3 SDRAM. In this specification, for ease of description, it is assumed that the memory device 100 is a NAND and described in this regard.

[0038] The memory device 100 may receive a command CMD and an address ADDR from the memory controller 200, and access an area selected by the address ADDR in the memory cell array. The memory device 100 may perform an operation indicated by the command CMD on the area selected by the address ADDR. For example, the memory device 100 may perform a write operation (programming operation), a read operation, and an erase operation. In a programming operation, the memory device 100 may program data to an area selected by the address ADDR. In a read operation, the memory device 100 may read data from an area selected by the address ADDR. In an erase operation, the memory device 100 may erase data stored in an area selected by the address ADDR.

[0039] The memory controller 200 may control the overall operations of the memory device 50 .

[0040] When power is applied to the memory device 50 , the memory controller 200 may execute firmware (FW).

[0041] In an embodiment, the memory controller 200 may receive data and a logical block address (LBA) from the host 300, and convert the LBA into a physical block address (PBA), which represents an address of a memory cell included in the memory device 100 where data is to be stored. The LBA may be referred to as a "logical address" or a "logical address". The PBA may be referred to as a "physical address".

[0042] The memory controller 200 may control the memory device 100 to perform a program operation, a read operation, an erase operation, or other operations in response to a request from the host 300. In a program operation, the memory controller 200 may provide a program command, a PBA, and data to the memory device 100. In a read operation, the memory controller 200 may provide a read command and a PBA to the memory device 100. In an erase operation, the memory controller 200 may provide an erase command and a PBA to the memory device 100.

[0043] In an embodiment, the memory controller 200 may control at least two memory devices 100. In some embodiments, the memory controller 200 may control the memory devices based on an interleaving technique to improve operation performance. The interleaving technique may allow the operations of at least two memory devices 100 to be controlled to overlap with each other.

[0044] The host 300 may request the storage device 50 to store data ("raw data") in the storage device 50. In response to the request to store the raw data from the host 300, the memory controller 200 may perform error correction encoding on the raw data and generate an error correction code (ECC) for error correction. The memory controller may generate write data including the error correction code (ECC) and control the memory device 100 to store the write data in the memory device 100.

[0045] The host 300 may send a read request to the storage device 50. The read request provided from the host 300 is used to request the storage device 50 to provide the host 300 with original data that has been stored in the storage device 50 based on the write request from the host 300. In response to the read request from the host 300, the memory controller 200 may provide a read command and a physical address representing a location of a memory cell storing data to be read to the memory device 100, thereby acquiring data corresponding to the read request from the host 300 from the memory device 100.

[0046] The memory device 100 may perform a read operation by using a default read voltage. The read voltage may be applied to identify data stored in a memory cell. The default read voltage may be determined by testing during the manufacturing process of the memory device 100.

[0047] The memory device 100 may provide read data obtained by reading data stored at the received physical address using a default read voltage to the memory controller 200. The memory controller 200 may perform error correction decoding on the read data.

[0048] Error correction decoding may be an operation of obtaining original data by correcting the error bits included in the read data. Whether the error correction decoding is successful or failed may be determined based on whether the number of error bits included in the read data is equal to or less than the number of correctable error bits. When the number of error bits included in the read data is equal to or less than the number of correctable error bits, the error correction decoding may be successful. On the contrary, when the number of error bits included in the read data exceeds the number of correctable error bits, the error correction decoding may fail. When the error correction decoding passes, the original data corresponding to the logical address included in the read request from the host 300 may be obtained. Therefore, when the error correction decoding passes, the read operation may be successfully performed. When the error correction decoding fails, the original data cannot be obtained, and the read operation performed by the memory device 100 fails.

[0049] The computing system 10 can detect errors on specific memory areas during workload operations by analysis techniques such as predictive failure analysis (PFA) techniques. Once the host 300 detects an error in a specific memory area, the host 300 can send relevant information including the address of the specific memory area to the storage device 50. A workload operation in a computing device can refer to any operation that uses computing resources to perform a specific task, and in the context of a data storage device, a workload operation is a data storage operation such as reading or writing data. When an error on a specific memory area is detected during a workload operation, the computing system 10 restricts access to the corresponding specific memory area. However, current predictions of errors during workload operations are only related to specific memory areas corresponding to the workload operations, and errors in another memory area that is not related to the workload operations are not detected. Therefore, when accessing other memory areas other than the specific memory area, an uncorrectable error (UE) may still occur in the computing system 10, where the host 300 can detect errors in the specific memory area based on prediction techniques such as PFA.

[0050] Therefore, some embodiments of the disclosed technology suggest a technique for detecting errors of memory cells adjacent to a specific memory cell corresponding to a workload operation. Therefore, according to an embodiment of the disclosed technology, the computing system 10 also detects errors of adjacent memory cells during the workload operation of the host 300. Therefore, the occurrence of UE can be prevented by blocking access to the memory area where the error occurs in advance.

[0051] In an embodiment, the memory controller 200 may receive a target address corresponding to a memory cell where an error has occurred from the host 300. The memory controller 200 may receive a request to perform a test operation to determine whether an error has occurred in any memory cell adjacent to the memory cell corresponding to the target address received from the host 300. The memory controller 200 may control the memory device 100 to perform the test operation based on the target address.

[0052] In an embodiment, the memory controller 200 may include a test operation controller 210 and an error information storage device 220 .

[0053] The test operation controller 210 may control a test operation in response to a request from the host 300 .

[0054] In an embodiment, the test operation controller 210 may control a test operation on memory cells adjacent to a memory cell in which an error occurs.

[0055] In an embodiment, the test operation controller 210 may control the test operation by using at least one of a built-in self test (BIST) engine and a scrub engine.

[0056] The BIST engine may be included in the memory controller 200. In an embodiment, a test operation using the BIST engine may include an operation of programming test data to an adjacent memory cell, reading data from a memory cell to which the test data has been programmed, and comparing the test data with the read data. The test operation controller 210 may determine whether an error has occurred in the adjacent memory cell based on a result obtained by comparing the test data with the read data.

[0057] The scrubbing engine may be included in at least one of the memory controller 200 and the memory device 100. The test operation using the scrubbing engine may include an operation of reading data from an adjacent memory cell and detecting an error of the read data by using an error correction code. The test operation controller 210 may determine whether an error has occurred in the adjacent memory cell based on an error detection operation using an error correction code.

[0058] In an embodiment, the test operation controller 210 may generate memory error information including information associated with a memory cell in which an error occurs among neighboring memory cells based on a result obtained by performing the test operation.

[0059] In an embodiment, the memory error information may include: error type information including information about the type of the error; and address information including an address of a memory cell where the error occurs.

[0060] The types of errors may include: a single bit error occurring in a single bit unit, a row error occurring in a row unit, a multi-row error occurring in a plurality of rows unit, and a column error occurring in a column unit.

[0061] A single bit error may indicate a situation where one or less errors occur in the same word line or the same bit line. A row error may indicate a situation where at least two errors occurring in the memory device 100 occur at the same row address in the same memory bank. A multi-row error may indicate a situation where at least two row errors occur in the same memory bank. A column error may indicate a situation where at least two errors occurring in the memory device 100 occur at the same column address.

[0062] The test operation controller 210 may generate error type information by selecting one of a single bit error, a row error, a multi-row error, and a column error based on a result obtained by performing the test operation.

[0063] The address information may include a bank address, a row address, and a column address of a memory cell where an error occurs.

[0064] In an embodiment, the test operation controller 210 may provide the memory error information to the host 300 based on a request from the host 300 .

[0065] The error information storage device 220 may store memory error information.

[0066] The host 300 may provide an operation request for a plurality of memory cells, such as a write request, a read request, or an erase request, to the storage device 50 based on a workload.

[0067] In an embodiment, the host may include an error manager 310 and a mode controller 320. The error manager 310 and the mode controller 320 may be firmware included in a BIOS (not shown).

[0068] Error manager 310 may include error monitoring software.

[0069] In an embodiment, the error manager 310 may detect an error occurring in the memory device 100 while an operation corresponding to a workload is being performed. In an embodiment, when an error is detected, the error manager 310 may provide a target address corresponding to a memory cell where the error occurred to the memory controller 200. Moreover, the error manager 310 may request a test operation to be performed on a memory cell adjacent to the memory cell where the error occurred. Subsequently, the error manager 310 may request memory error information and receive the memory error information from the memory controller 200.

[0070] In an embodiment, the error manager 310 may control access to the memory unit where the error occurs based on the memory error information. For example, the error manager 310 may disable access to the memory unit where the error occurs based on the memory error information. Specifically, the error manager 310 may disable access to the memory unit where the error occurs based on information about the type of error and the address of the memory unit where the error occurs. Moreover, the error manager 310 may provide a request to the memory controller 200 to perform an offline operation on the memory unit where the error occurs.

[0071] The mode controller 320 may set the operation mode of the host 300. For example, the operation mode of the host 300 may include a normal operation mode, a system management mode (SMM), or others. The normal operation mode may represent a mode in which an operating system (not shown) included in the host performs an operation corresponding to a workload. The SMM may represent a mode for allowing access to all memory areas included in the memory device 100 to handle system-wide functions such as power management, system hardware control, etc., but restricting the operation of the operating system.

[0072] Figure 2 is a diagram illustrating an example of a test operation according to an embodiment of the disclosed technology. Figure 3 is a flow chart illustrating an example of a testing operation according to an embodiment of the disclosed technology.

[0073] Figure 2 and Figure 3 2 is a diagram showing an example of performing a test operation by using a BIST engine included in the memory controller 200. Figure 2 and Figure 3 In the embodiment, it is assumed that the memory controller 200 includes a BIST engine.

[0074] Reference Figure 2 and Figure 3 , when the host 300 is performing an operation corresponding to a workload, the host 300 may detect an error of a specific memory unit (S301).

[0075] Subsequently, the host 300 may set the operation mode to a system management mode (SMM) ( S303 ).

[0076] Subsequently, the host 300 may provide the memory controller 200 with a target address target_addr corresponding to the memory cell where the error occurs and a request test_req for performing a test operation on memory cells adjacent to the memory cell where the error occurs ( S305 ).

[0077] In an embodiment, the host 300 may disable operation requests and error correction operations for the plurality of memory units ( S307 ).

[0078] In an embodiment, the test operation controller 210 may control the memory device 100 to store data stored in adjacent memory cells in an empty memory cell among the plurality of memory cells.

[0079] Specifically, the test operation controller 210 may provide the memory device 100 with a command for storing data stored in adjacent memory cells in an empty memory cell among the plurality of memory cells ( S309 ).

[0080] The memory device 100 may store data stored in adjacent memory cells in an empty memory cell among a plurality of memory cells ( S311 ).

[0081] In an embodiment, the test operation controller 210 may control the test operation on the adjacent memory cells by using a BIST engine based on the target address target_addr.

[0082] In some embodiments, the test operation controller 210 may provide the memory device 100 with test data and a write command write_cmd for programming the test data to adjacent memory cells ( S313 ).

[0083] The memory device 100 may program the test data to the adjacent memory cells based on the write command write_cmd ( S315 ).

[0084] Subsequently, the test operation controller 210 may provide the memory device 100 with a read command read_cmd for reading data from the memory cells to which the test data is programmed ( S317 ).

[0085] The memory device 100 may provide read data to the memory controller 200 based on the read command read_cmd ( S319 ).

[0086] Subsequently, the test operation controller 210 may generate memory error information based on the result obtained by comparing the test data with the read data (S321). In an embodiment, when the type of error is determined to be a single bit error, the test operation controller 210 may suspend the test operation. The error information storage device 220 may store the memory error information generated by the test operation controller 210.

[0087] When the test operation of the test operation controller 210 is finished, the host 300 may set the operation mode to a normal operation mode (S323).

[0088] The test operation controller 210 may provide memory error information to the host 300 (S325).

[0089] The host 300 may disable access to the memory unit where the error occurs based on memory error information (S327).

[0090] Figure 4 is a diagram illustrating another example of a test operation according to an embodiment of the disclosed technology. Figure 5 is a flowchart illustrating another example of a test operation according to an embodiment of the disclosed technology.

[0091] Figure 4 and Figure 5 2 is a diagram showing an example of performing a test operation by using the SCRUB engine included in the memory controller 200. Figure 4 and Figure 5 In FIG. 1 , it is assumed that the memory controller 200 includes a SCRUB engine. Furthermore, in Figure 4 and Figure 5 In the embodiment, the operation mode of the host 300 may be a normal operation mode.

[0092] Reference Figure 4 and Figure 5 , when the host 300 performs an operation corresponding to a workload, the host 300 may detect an error of a specific memory unit (S501).

[0093] Subsequently, the host 300 may provide the memory controller 200 with a target address target_addr corresponding to the memory cell where the error occurs and a request test_req for performing a test operation on memory cells adjacent to the memory cell where the error occurs ( S503 ).

[0094] In an embodiment, the test operation controller 210 may control a test operation on adjacent memory cells by using an SCRUB engine included in the memory controller 200 based on a target address.

[0095] The test operation controller 210 may provide the memory device 100 with a read command read_cmd for reading data from adjacent memory cells ( S505 ).

[0096] The memory device 100 may provide read data to the memory controller 200 according to the read command read_cmd ( S507 ).

[0097] Subsequently, the test operation controller 210 may detect an error of the read data by using an error correction code (S509).

[0098] Subsequently, the test operation controller 210 may generate memory error information based on the result obtained by detecting the error (S511). In an embodiment, when the type of error is determined to be a single bit error, the test operation controller 210 may suspend the test operation. The error information storage device 220 may store the memory error information generated by the test operation controller 210.

[0099] The test operation controller 210 may provide memory error information to the host 300 (S513).

[0100] The host 300 may disable access to the memory unit where the error occurs based on memory error information (S515).

[0101] Figure 6 is a diagram illustrating yet another example of a test operation according to an embodiment of the disclosed technology. Figure 7 is a flowchart illustrating yet another example of a test operation according to an embodiment of the disclosed technology.

[0102] Specifically, Figure 6 and Figure 7 2 is a diagram showing an example of performing a test operation by using the SCRUB engine included in the memory controller 200. Figure 6 and Figure 7 In FIG. 1 , it is assumed that the memory controller 200 includes a SCRUB engine. Furthermore, in Figure 6 and Figure 7 In the embodiment, the operation mode of the host 300 may be a normal operation mode.

[0103] Reference Figure 6 and Figure 7 , when the host 300 is performing an operation corresponding to a workload, the host 300 may detect an error of a specific memory unit (S701).

[0104] Subsequently, the host 300 may provide the memory controller 200 with a target address target_addr corresponding to the memory cell where the error occurs and a request test_req for performing a test operation on memory cells adjacent to the memory cell where the error occurs ( S703 ).

[0105] In an embodiment, the test operation controller 210 may control a test operation on adjacent memory cells by using an SCRUB engine included in the memory controller 200 based on a target address.

[0106] In some embodiments, the test operation controller 210 may provide the memory device 100 with a command cmd for performing a test operation on adjacent memory cells ( S705 ).

[0107] The memory device 100 may read data from the adjacent memory cells according to the command cmd ( S707 ), and detect an error of the read data by using an error correction code ( S709 ).

[0108] Subsequently, the memory device 100 may generate memory error information based on the result obtained by detecting the error (S711). In an embodiment, when the type of error is determined to be a single bit error, the memory device 100 may suspend the test operation.

[0109] The memory device 100 may provide memory error information to the memory controller 200 ( S713 ). The error information storage device 220 may store the memory error information provided from the memory device 100 .

[0110] The test operation controller 210 may provide memory error information to the host 300 (S715).

[0111] The host 300 may disable access to the memory unit where the error occurs based on memory error information (S717).

[0112] Figure 8 is a flow chart illustrating a method of operation of a computing system according to an embodiment of the disclosed technology.

[0113] Figure 8 The operation method shown can be performed, for example, by Figure 1 The computing system 10 shown executes.

[0114] Reference Figure 8, in step S801, the computing system 10 may detect an error.

[0115] In step S803 , the computing system 10 may provide a target address corresponding to the memory cell where the error occurs to the memory controller.

[0116] In step S805 , the computing system 10 may request the memory controller to perform a test operation to determine whether an error occurs in a memory cell adjacent to the memory cell in which the error occurs among the plurality of memory cells.

[0117] In step S807 , the computing system 10 may perform a test operation on the adjacent memory cells.

[0118] In step S809 , the computing system 10 may generate memory error information indicating a result obtained by performing the test operation.

[0119] In step S811 , the computing system 10 may disable access to a memory cell in which an error occurs among neighboring memory cells based on the memory error information.

[0120] Fig. 9 is a flowchart illustrating an example of a method for performing a test operation according to an embodiment of the disclosed technology.

[0121] Fig. 9 The method shown can be accomplished, for example, by Figure 1 The computing system 10 shown executes.

[0122] In an embodiment, Fig. 9 The illustrated method may be a method for performing a test operation by using a BIST engine included in a memory controller.

[0123] Reference Fig. 9 , in step S901, the computing system 10 may detect an error.

[0124] In step S903 , the computing system 10 may set the operation mode of the host to a system management mode.

[0125] In step S905 , the computing system 10 may provide a target address corresponding to the memory cell where the error occurs to the memory controller.

[0126] In step S907 , the computing system 10 may request the memory controller to perform a test operation to determine whether an error occurs in a memory cell adjacent to the memory cell in which the error occurs among the plurality of memory cells.

[0127] In step S909 , the computing system 10 may disable operation requests for the plurality of memory units except for requests for test operations.

[0128] In step S911 , the computing system 10 may disable error correction operations.

[0129] In step S913 , the computing system 10 may store the data stored in the adjacent memory cells in an empty memory cell among the plurality of memory cells.

[0130] In step S915 , the computing system 10 may program the test data to the adjacent memory cells.

[0131] In step S917 , the computing system 10 may read data from the memory cells into which the test data is programmed.

[0132] In step S919 , the computing system 10 may compare the test data with the read data.

[0133] In step S921 , the computing system 10 may generate memory error information based on a result obtained by comparing the test data with the read data.

[0134] In step S923 , the computing system 10 may set the operation mode of the host to a normal operation mode.

[0135] In step S925 , the computing system 10 may provide memory error information to the host.

[0136] In step S927 , the computing system 10 may disable access to a memory cell in which an error occurs among neighboring memory cells based on the memory error information.

[0137] Fig.10 is a flowchart illustrating another example of a method for performing a test operation according to an embodiment of the disclosed technology.

[0138] Fig.10 The method shown can be accomplished, for example, by Figure 1 The computing system 10 shown executes.

[0139] In an embodiment, Fig.10 The illustrated method may be a method for performing a test operation by using a scrubbing engine included in at least one of a memory controller and a memory device.

[0140] and, Fig.10 The illustrated method may be performed in a state where the operation mode of the host is set to the normal operation mode.

[0141] Reference Fig.10, in step S1001, the computing system 10 may detect an error.

[0142] In step S1003 , the computing system 10 may provide a target address corresponding to a memory cell where an error occurs to the memory controller.

[0143] In step S1005 , the computing system 10 may request the memory controller to perform a test operation to determine whether an error occurs in a memory cell adjacent to the memory cell in which the error occurs among the plurality of memory cells.

[0144] In step S1007 , the computing system 10 may read data from adjacent memory cells.

[0145] In step S1009 , the computing system 10 may detect errors in read data by using an error correction code.

[0146] In step S1011 , the computing system 10 may generate memory error information based on a result obtained by detecting an error.

[0147] In step S1013 , the computing system 10 may provide memory error information to the host.

[0148] In step S1015 , the computing system 10 may disable access to a memory cell in which an error occurs among neighboring memory cells based on the memory error information.

[0149] Fig.11 It is shown Figure 1 A diagram of a memory controller is shown.

[0150] Reference Figure 1 and Fig.11 , the memory controller 200 may include a processor 230 , a RAM 240 , an error correction circuit 250 , a ROM 260 , a host interface 270 , and a memory interface 280 .

[0151] The processor 230 may control the overall operation of the memory controller 200. The RAM 240 may be used as a buffer memory, a cache memory, a working memory, etc. of the memory controller 200.

[0152] The error correction circuit 250 may perform error correction. The error correction circuit 250 may perform ECC encoding based on data to be written to the memory device through the memory interface 280. The ECC-encoded data may be transmitted to the memory device through the memory interface 280. The error correction circuit 250 may perform ECC decoding on data received from the memory device through the memory interface 280. Exemplarily, the error correction circuit 250 may be included in the memory interface 280 as a component of the memory interface 280.

[0153] The ROM 260 may store various information required in the operation of the memory controller 200 in the form of firmware. In an example, Figure 1 The illustrated test operation controller 210 and the error information storage device 220 may be firmware stored in the ROM 260 .

[0154] The memory controller 200 may communicate with an external device (eg, the host 300 , an application processor, etc.) through the host interface 270 .

[0155] The memory controller 200 may communicate with the memory device 100 through the memory interface 280. The memory controller 200 may transmit commands, addresses, control signals and / or others to the memory device 100 through the memory interface 280, and receive data.

[0156] According to the disclosed technology, a computing system capable of preemptively blocking access to a memory cell in which an error occurs and an operating method of the computing system can be provided.

[0157] Although the disclosed technology has been shown and described with reference to certain exemplary embodiments of the disclosed technology, it will be understood by those skilled in the art that various changes in form and detail may be made to the disclosed examples. Various modifications and improvements may be made to the disclosed embodiments and other embodiments based on what is disclosed in this patent document.

Claims

1. A computing system comprising: a memory device comprising a plurality of memory cells storing data; a memory controller communicating with the memory device and controlling the memory device; as well as a host, in communication with the memory controller, for reading data from or writing data to the memory device, and detecting an error occurring in a first memory cell of the memory device while performing an operation corresponding to a workload, and transmitting to the memory controller i) a target address corresponding to the first memory cell and ii) a request for a test operation to be performed on a neighboring memory cell adjacent to the first memory cell, wherein the memory controller further controls the memory device to perform the test operation on the adjacent memory cell based on the target address, determines a second memory cell where an error occurs based on a result of the test operation, the second memory cell being one of the adjacent memory cells, and generates memory error information including information associated with the second memory cell, and The host further controls access to the second memory unit based on the memory error information.

2. The computing system of claim 1 , wherein the memory controller comprises: a test operation controller, in response to a request for the test operation, controlling the memory device to perform the test operation; as well as An error information storage device stores the memory error information. 3 . The computing system of claim 2 , wherein the test operation is performed on the adjacent memory cells according to a command stored in at least one of the memory controller and the memory device. 4 . The computing system according to claim 2 , wherein the host further sets its operation mode to a system management mode, and transmits the target address and the request for the test operation to the test operation controller in the system management mode. 5 . The computing system according to claim 4 , wherein the test operation controller stores the data, which has been stored in the adjacent memory cell, in an empty memory cell among the plurality of memory cells. 6 . The computing system of claim 4 , wherein the host further disables, in the system management mode, operation requests for the plurality of memory units other than a request for the test operation and an error correction operation.

7. The computing system of claim 4, wherein the test operation comprises an operation of programming test data to the adjacent memory cells, reading data from the programmed memory cells, and comparing the test data with read data. 8 . The computing system of claim 2 , wherein the host further transmits the target address and the request for the test operation to the test operation controller in a normal operation mode. 9 . The computing system of claim 8 , wherein the test operation includes an operation of reading data from the adjacent memory cells and detecting an error of the read data by using an error correction code (ECC).

10. The computing system of claim 1, wherein the memory error information comprises: Error type information, including information about the type of error; and address information, including an address of the second memory unit.

11. The computing system of claim 1, wherein the host further disables access to the second memory unit based on the memory error information.

12. A method of operating a computing system, comprising: detecting, by a host communicating with a storage device, an error occurring in a first memory unit included in a memory device, the storage device including the memory device and a memory controller controlling the memory device, the memory device including one or more memory units; Setting the operating mode of the host to system management mode; transmitting, to the memory controller, a target address corresponding to the first memory cell and a request for performing a test operation on a neighboring memory cell adjacent to the first memory cell; determining a second memory cell in which an error occurs based on a result of the test operation, the second memory cell being one of the adjacent memory cells; receiving memory error information from the memory controller, the memory error information including information associated with the second memory unit; and Access to the second memory unit is enabled or disabled based on the memory error information.

13. The method of claim 12, wherein transmitting the target address and the request for the test operation is performed in the system management mode.

14. The method of claim 13, wherein the memory controller performs the test operation according to a command stored in at least one of the memory controller and the memory device.

15. The method according to claim 14, further comprising: In response to setting the operating mode of the host to the system management mode: disabling i) operation requests for the one or more memory cells other than requests for the test operations and disabling ii) error correction operations; and The data already stored in the adjacent memory cells are stored in an empty memory cell among the one or more memory cells.

16. The method of claim 15, wherein the memory controller further performs the test operation by: programming test data into the adjacent memory cells; reading data from the adjacent memory cells; and The test data is compared with the read data.

17. The method of claim 12, wherein transmitting the target address and the request for the test operation is performed in a normal operating mode of the host.

18. The method of claim 14, wherein the memory controller further performs the test operation by: reading data from the adjacent memory cells; and Errors in read data are detected by using an error correction code, namely, ECC.

19. A data storage device comprising: a memory device comprising a plurality of memory cells storing data; and a memory controller that communicates with the memory device and controls the memory device, the memory controller further communicating with a host device outside the data storage device to receive information about an error occurring in a first memory cell of the memory device from the host device, the information including a target address corresponding to the first memory cell and a request for a test operation to be performed on a neighboring memory cell adjacent to the first memory cell, wherein the memory controller further controls the memory device to perform the test operation on the adjacent memory cell based on the target address, determines a second memory cell where an error occurs based on a result of the test operation, the second memory cell being one of the adjacent memory cells, and generates memory error information including information associated with the second memory cell, and wherein the memory controller further communicates the memory error information to the host device, and Wherein the host device further controls access to the second memory unit based on the memory error information.

20. The data storage device of claim 19, wherein the memory controller further determines the second memory unit based on a result of the test operation.

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