A preparation process for improving the threshold voltage stability of a silicon carbide VDMOSFET device

Abstract

The present invention discloses a preparation process for improving the threshold voltage stability of a silicon carbide VDMOSFET device, including: obtaining a silicon carbide EPI substrate; growing a sacrificial oxide layer on the N-SiC epitaxial layer in the silicon carbide EPI substrate; removing the sacrificial oxide layer; growing a SiO2 barrier layer on the N-SiC epitaxial layer; growing a C thin film layer on the N-SiC epitaxial layer and the SiO2 barrier layer; forming a PWELL region at the ion implantation window of the PWELL region; removing the C thin film layer and the SiO2 barrier layer; forming a P+ implantation region at the ion implantation window of the P+ implantation region; forming an N+ source region at the ion implantation window of the N+ source region; growing an oxide layer on the N-SiC epitaxial layer; growing an N-type polysilicon thin film layer on the oxide layer; etching away the oxide layer and the N-type polysilicon thin film layer outside the gate region to form a gate oxide layer and an N-type polysilicon gate. The present invention improves the threshold voltage stability.

Description

Technical Field

[0001] The present invention belongs to the technical field of power semiconductors, and particularly relates to a preparation process for improving the threshold voltage stability of a silicon carbide VDMOSFET device. Background Art

[0002] Power device semiconductors have characteristics such as high voltage resistance and high temperature resistance, and are widely used in the field of power electronics technology. Since the development of the Vertical Double-Diffused Metal Oxide Semiconductor Field Effect Transistor (abbreviated as VDMOSFET) device, the VDMOSFET has occupied an increasingly important position in the electronics field with its advantages such as high switching speed, low switching power consumption, low driving power, and high input impedance and high voltage resistance.

[0003] In recent years, due to the development of third-generation semiconductors such as SiC and GaN, the SiC VDMOSFET has been greatly improved in terms of on-resistance, switching time, switching loss, and heat dissipation performance. The SiC VDMOSFET has three electrodes: a gate, a source, and a drain. The turn-off and turn-on of the VDMOSFET are controlled by controlling the voltage of the gate. When the gate voltage is lower than the threshold voltage, the device is turned off; when the gate voltage is higher than the threshold voltage, an inversion layer conductive channel is formed under the gate, and the device is turned on; when the gate voltage is lower than the threshold voltage, the device is turned off. Therefore, the threshold voltage stability of the device has a great impact on the reliability of the power device. In the manufacturing process of the SiC VDMOSFET device, currently, the most commonly used method is to perform multiple Al ion implantations on the epitaxial layer to form a PWELL region, and the threshold voltage of the device is adjusted by adjusting the Al ion concentration implanted in the PWELL region.

[0004] However, in the process of forming the PWELL region in the existing SiC VDMOSFET device, at the interface between the PWELL region and the epitaxial layer, due to multiple bombardments of Al ions, and the aluminum atom is much larger than the carbon atom, some carbon-silicon bonds in the epitaxial layer of silicon carbide are broken, the carbon atoms deviate from their original positions, vacancies and interstitial sites are formed in the silicon carbide structure, and deep-level traps are formed. The deep-level traps at the interface between the PWELL region and the epitaxial layer caused by this traditional process will directly affect the threshold voltage stability. Summary of the Invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a preparation process for improving the threshold voltage stability of a silicon carbide VDMOSFET device.

[0006] The technical problems to be solved by the present invention are achieved through the following technical solutions:

[0007] The present invention provides a preparation process for improving the threshold voltage stability of a silicon carbide VDMOSFET device, including:

[0008] Select a silicon carbide EPI substrate; wherein, the silicon carbide EPI substrate includes an N+ SiC substrate and an N-SiC epitaxial layer located on the N+ SiC substrate;

[0009] Grow a sacrificial oxide layer on the N-SiC epitaxial layer;

[0010] Remove the sacrificial oxide layer;

[0011] Grow a SiO 2 barrier layer;

[0012] On the upper surfaces at both ends of the SiO 2 barrier layer, lithographically pattern the lithography regions of the PWELL regions, and etch away the SiO 2 barrier layer within the lithography regions of the PWELL regions to form ion implantation windows for the PWELL regions;

[0013] Grow a C thin film layer on the N-SiC epitaxial layer and the SiO 2 barrier layer;

[0014] Perform multiple ion implantations on the C thin film layer within the ion implantation windows of the PWELL regions to form the PWELL regions;

[0015] Remove the C thin film layer outside the ion implantation windows of the PWELL regions;

[0016] Remove the SiO 2 barrier layer;

[0017] On the upper surfaces at both ends of the PWELL regions, lithographically pattern the ion implantation windows for the P+ implantation regions, and perform ion implantation within the ion implantation windows for the P+ implantation regions to form the P+ implantation regions;

[0018] On the PWELL regions, lithographically pattern the ion implantation windows for the N+ source regions, and perform ion implantation within the ion implantation windows for the N+ source regions to form the N+ source regions; wherein, the ion implantation windows for the N+ source regions are adjacent to the ion implantation windows for the P+ implantation regions;

[0019] Grow an oxide layer on the N-SiC epitaxial layer, the PWELL regions, the P+ implantation regions, and the N+ source regions;

[0020] Grow an N-type polysilicon thin film layer on the oxide layer;

[0021] A gate region is lithographically patterned on the N-type polysilicon thin film layer, and the oxide layer and the N-type polysilicon thin film layer outside the gate region are etched away to form a gate oxide layer and an N-type polysilicon gate respectively.

[0022] In an embodiment of the present invention, the growth of the sacrificial oxide layer on the N-SiC epitaxial layer includes:

[0023] Using a thermal oxidation process, a sacrificial oxide layer with a thickness of is grown on the N-SiC epitaxial layer.

[0024] In an embodiment of the present invention, the growth of the SiO 2 barrier layer on the N-SiC epitaxial layer includes:

[0025] Using a PECVD process, a SiO barrier layer with a thickness of 2 is grown on the N-SiC epitaxial layer.

[0026] In an embodiment of the present invention, the growth of the C thin film layer on the N-SiC epitaxial layer and the SiO 2 barrier layer includes:

[0027] Using a magnetron sputtering process, a C thin film layer with a thickness of 2 is grown on the N-SiC epitaxial layer and the SiO barrier layer.

[0028] In an embodiment of the present invention, the formation of the PWELL region by performing multiple ion implantations on the C thin film layer within the ion implantation window of the PWELL region includes:

[0029] Using an ion implantation process, 3 to 5 times of Al ion implantations are performed on the C thin film layer within the ion implantation window of the PWELL region to form the PWELL region; wherein, the dose of each Al ion implantation is 5×10 16 cm -3 ~5×10 18 cm -3 and the implantation energy is 80 Kev to 160 Kev.

[0030] In an embodiment of the present invention, the removal of the C thin film layer outside the ion implantation window of the PWELL region includes:

[0031] Using a thermal oxidation process, the C thin film layer outside the ion implantation window of the PWELL region is removed.

[0032] In an embodiment of the present invention, the formation of the P+ implantation region by performing ion implantation within the ion implantation window of the P+ implantation region includes:

[0033] Using an ion implantation process, Al ions with an implantation dose of 1×10 19 cm -3 ~1×10 20 cm -3 and an implantation energy of 80 keV to 160 keV are implanted to form the P+ implantation region within the ion implantation window of the P+ implantation region.

[0034] In an embodiment of the present invention, the ion implantation within the ion implantation window of the N+ source region to form the N+ source region includes:

[0035] Using an ion implantation process, B ions with an implantation dose of 1×10 19 cm -3 ~1×10 20 cm -3 and an implantation energy of 100 keV to 180 keV are implanted to form the N+ source region.

[0036] In an embodiment of the present invention, growing an oxide layer on the N-SiC epitaxial layer, the PWELL region, the N+ source region, and the P+ implantation region includes:

[0037] Using a thermal oxidation process, an oxide layer with a thickness of is grown on the N-SiC epitaxial layer, the PWELL region, the N+ source region, and the P+ implantation region.

[0038] In an embodiment of the present invention, growing an N-type polysilicon thin film layer on the gate oxide layer includes:

[0039] Using a PECVD process, an N-type polysilicon thin film layer with a thickness of is grown on the gate oxide layer.

[0040] Advantages of the present invention:

[0041] The manufacturing process for improving the threshold voltage stability of a silicon carbide VDMOSFET device provided by the present invention, when forming the PWELL region by ion implantation, first deposits a C thin film layer at the ion implantation window of the PWELL region, and then performs multiple ion implantations to form the PWELL region. Due to the introduction of the C thin film layer, it can effectively fill the missing carbon atoms due to multiple ion implantation bombardments, reduce the vacancies and interstitial atoms in the silicon carbide structure, and decrease the number of deep-level traps, thereby improving the threshold voltage stability. Since the C thin film layer is only used to fill the missing carbon atoms due to multiple ion implantation bombardments, its introduction does not change other performance parameters of the device, such as the breakdown voltage and the characteristic on-resistance of the device. Before forming the PWELL region, the present invention grows and removes a sacrificial oxide layer on the N-SiC epitaxial layer. Such a treatment method can effectively remove the surface defects pre-existing on the surface of the silicon carbide EPI substrate to reduce the influence of such defects on the performance of subsequent device manufacturing. Since the growth and removal of the sacrificial oxide layer are performed on the N-SiC epitaxial layer, it does not affect the threshold voltage of the device. The introduced C thin film layer in the present invention solves the defect problem generated during the ion implantation process in the traditional manufacturing process, and at the same time introduces a SiO 2 barrier layer, which can control the good deposition of the C thin film layer at the ion implantation window of the PWELL region and prevent the deposition of the C thin film layer from affecting other regions except the PWELL region, improving the performance of device manufacturing.

[0042] The following will further elaborate on the present invention in conjunction with the drawings. Description of the Drawings

[0043] Figure 1 is a schematic process flow diagram of a manufacturing process for improving the threshold voltage stability of a silicon carbide VDMOSFET device provided by an embodiment of the present invention;

[0044] Figure 2 (a) to 2(m) are schematic structural diagrams corresponding to the manufacturing process of a manufacturing process for improving the threshold voltage stability of a silicon carbide VDMOSFET device provided by an embodiment of the present invention;

[0045] Figure 3 is a schematic structural diagram of a silicon carbide VDMOSFET device provided by an embodiment of the present invention.

[0046] Description of the Reference Numerals in the Drawings:

[0047] 1 - N+SiC substrate; 2 - N-SiC epitaxial layer; 3 - PWELL region; 4 - P+ implantation region; 5 - N+ source region; 6 - gate oxide layer; 7 - polysilicon gate; 8 - sacrificial oxide layer; 9 - SiO 2 barrier layer; 10 - C thin film layer. Detailed Embodiments

[0048] The present invention will be further described in detail below in conjunction with specific embodiments, but the implementation manners of the present invention are not limited thereto.

[0049] In order to improve the stability of the threshold voltage of a silicon carbide VDMOSFET device, an embodiment of the present invention provides a preparation process for improving the stability of the threshold voltage of a silicon carbide VDMOSFET device, and a silicon carbide VDMOSFET device.

[0050] In a first aspect, an embodiment of the present invention provides a preparation process for improving the stability of the threshold voltage of a silicon carbide VDMOSFET device, including the following steps:

[0051] S101. Select a silicon carbide EPI substrate; wherein, the silicon carbide EPI substrate includes an N+ SiC substrate 1 and an N-SiC epitaxial layer 2 located on the N+ SiC substrate 1.

[0052] Specifically, please refer to Figure 2 (a), the silicon carbide EPI substrate selected in the embodiment of the present invention sequentially includes, from bottom to top, an N+ SiC substrate 1 with a thickness of and an N-SiC epitaxial layer 2 with a thickness of located on the N+ SiC substrate 1. Among them, the silicon carbide EPI substrate can be an existing integrated silicon carbide EPI substrate, or can be obtained by growing an N-SiC epitaxial layer 2 on the N+ SiC substrate 1 using a Metal-organic Chemical Vapor Deposition (MOCVD) process.

[0053] S102. Grow a sacrificial oxide layer 8 on the N-SiC epitaxial layer 2.

[0054] Specifically, please refer to Figure 2 (b), in the embodiment of the present invention, a sacrificial oxide layer 8 is grown on the N-SiC epitaxial layer 2, and the material of the sacrificial oxide layer 8 can be SiO 2 , specifically including: using a thermal oxidation process to grow a sacrificial oxide layer 8 with a thickness of For the sacrificial oxide layer 8, the thermal oxidation process can be wet oxidation, and the temperature of the wet oxidation is 950°C to 1000°C. Since there may be defects on the surface of the selected SiC EPI substrate or the prepared SiC EPI substrate, such defects will affect the performance of subsequent device fabrication. Therefore, in the embodiment of the present invention, a sacrificial oxide layer 8 is grown on the N-SiC epitaxial layer 2 and then removed. Such a treatment method can effectively remove the pre-existing surface defects on the surface of the SiC EPI substrate, so as to reduce the influence of such defects on the performance of subsequent device fabrication. In the present invention, since the growth and removal of the sacrificial oxide layer 8 are carried out on the N-SiC epitaxial layer 2, it will not affect the threshold voltage of the device.

[0055] In the embodiment of the present invention, the thermal oxidation process is adopted to grow the sacrificial oxide layer 8, and the in-situ growth of the sacrificial oxide layer 8 is realized on the N-SiC epitaxial layer 2, and part of the N-SiC epitaxial layer 2 is oxidized into the sacrificial oxide layer 8, avoiding the problem of interface damage introduced by etching when the traditional atomic layer deposition (ALD) process is used to grow the sacrificial oxide layer 8, and effectively reducing the surface defects at the interface at this time.

[0056] S103. Remove the sacrificial oxide layer 8.

[0057] Specifically, after achieving the above purpose, the sacrificial oxide layer 8 is removed by a wet etching process, and specifically, a wet etching is carried out using a buffered oxide etch (BOE) solution to form Figure 2 the structure shown in (a). Only the surface defects of the device after being treated with the sacrificial oxide layer 8 are relatively small, improving the performance of subsequent device fabrication. Among them, the BOE solution is composed of a mixture of 49% HF aqueous solution: 40% NH 4 F aqueous solution = 1:6 (volume ratio).

[0058] S104. Grow a SiO 2 barrier layer 9 on the N-SiC epitaxial layer 2.

[0059] Specifically, please refer to Figure 2 (c). The embodiment of the present invention provides an optional solution to grow a SiO 2 barrier layer 9 on the N-SiC epitaxial layer 2, which specifically includes: using a plasma enhanced chemical vapor deposition (PECVD) process to grow a SiO with a thickness of 2 barrier layer 9 on the N-SiC epitaxial layer 2. In the embodiment of the present invention, the SiO 2The purpose of the barrier layer 9 is to control the subsequent C thin film layer to be well deposited on the ion implantation window of the PWELL region and prevent the deposition of the C thin film layer from affecting other regions except the PWELL region, thereby improving the performance of device fabrication. The SiO of the present invention 2 The growth of the barrier layer 9 is closely related to the introduction of the C thin film layer of the present invention.

[0060] Another alternative is provided in the embodiments of the present invention. SiO is grown on the N-SiC epitaxial layer 2 2 Barrier layer 9, specifically including: using a thermal oxidation process to grow a SiO with a thickness of on the N-SiC epitaxial layer 2 of SiO 2 Barrier layer 9. The thermal oxidation process can be wet oxidation, and the temperature of the wet oxidation is 950°C to 1000°C. Similar to S102, using the thermal oxidation process can reduce the surface defects at the interface at this time.

[0061] In the embodiments of the present invention, the preferred solution for growing SiO 2 Barrier layer 9 is selected as: using a thermal oxidation process to grow SiO on the N-SiC epitaxial layer 2 2 Barrier layer 9.

[0062] S105. Lithographically pattern the photolithography regions of the PWELL region 3 on the upper surfaces at both ends of the SiO 2 Barrier layer 9, and etch away the SiO within the photolithography regions of the PWELL region 3 2 Barrier layer 9 to form the ion implantation window of the PWELL region 3.

[0063] Specifically, please refer to Figure 2 (d). In the embodiments of the present invention, the photolithography regions of the PWELL region 3 are lithographically patterned on the upper surfaces at both ends of the SiO 2 Barrier layer 9 using photoresist development technology, and then the SiO within the photolithography regions of the PWELL region 3 is etched away using an Inductive Coupled Plasma Emission Spectrometer (ICP) process 2 Barrier layer 9 to form the ion implantation window of the PWELL region 3.

[0064] S106. Grow a C thin film layer 10 on the N-SiC epitaxial layer 2 and the SiO 2 Barrier layer 9.

[0065] Specifically, please refer to Figure 2 (e). In the embodiments of the present invention, a C thin film layer 10 is grown on the N-SiC epitaxial layer 2 and the SiO 2 Barrier layer 9, specifically including: using a magnetron sputtering process to grow a C thin film layer with a thickness of on the N-SiC epitaxial layer 2 and the SiO 2 Barrier layer 9 C thin film layer 10. In the embodiments of the present invention, the C thin film layer 10 is grown here because the inventors have found through research that the reason for the poor stability of the threshold voltage of existing SiC VDMOS devices is that during the formation of the PWELL region, at the interface between the PWELL region and the epitaxial layer, due to multiple bombardments of Al ions, and since aluminum atoms are much larger than carbon atoms, some carbon-silicon bonds in the silicon carbide in the epitaxial layer are broken, carbon atoms break away from their original positions, forming vacancies and interstitial sites in the silicon carbide structure and forming deep-level traps. Based on this analysis, the inventors propose that before multiple ion implantations, a C thin film layer is deposited at the ion implantation window of the PWELL region, and then multiple ion implantations are carried out. Due to the introduction of the C thin film layer, the carbon atoms missing due to multiple ion implantation bombardments can be effectively filled, reducing the vacancies and interstitial sites in the silicon carbide structure and reducing the number of deep-level traps, thereby improving the stability of the threshold voltage; at the same time, the C thin film layer in the embodiments of the present invention is only used to fill the carbon atoms missing due to multiple ion implantation bombardments. Its introduction improves the stability of the threshold voltage and does not change other performance parameters of the device, such as the breakdown voltage and the characteristic on-resistance of the device. During the growth of the C thin film layer 10, SiO 2 barrier layer is needed. Under the action of the SiO 2 barrier layer, the PWELL region 3 can be formed better.

[0066] In the embodiments of the present invention, the magnetron sputtering process is used to grow the C thin film layer 10. The magnetron sputtering process is selected because: the thickness of the C thin film layer 10 is very critical for the formation of the PWELL region 3. If the thickness of the C thin film layer 10 is too thick, C atoms will remain, and the residual C atoms have a great impact on the device performance. If the thickness of the C thin film layer 10 is too thin, too few C atoms will fill the defects during the ion implantation process, and it will not play its due role. After research by the inventors, when the thickness of the C thin film layer 10 reaches , the best effect can be achieved. And by using this fast and low-temperature magnetron sputtering process, the growth thickness of the C thin film layer 10 and the uniformity of the growth of the C thin film layer 10 can be better controlled, realizing the effective filling of the carbon atoms missing due to multiple ion implantation bombardments.

[0067] S107. Multiple ion implantations are carried out on the C thin film layer within the ion implantation window of the PWELL region 3 to form the PWELL region 3.

[0068] Specifically, please refer to Figure 2 (f). In the embodiments of the present invention, multiple ion implantations are carried out on the C thin film layer within the ion implantation window of the PWELL region 3 to form the PWELL region 3, including: using the ion implantation process, 3 to 5 times of Al ion implantations are carried out on the C thin film layer within the ion implantation window of the PWELL region 3 to form the PWELL region 3; where the dose of each Al ion implantation is 5×1016 cm -3 ~5×10 18 cm -3 , the injection energy is 80Kev~160Kev. In the embodiment of the present invention, in order to make the introduced C thin film layer 10 fill the missing C atoms in the N-SiC epitaxial layer 2 as much as possible without leaving any residue on the surface of the N-SiC epitaxial layer 2, compared with the method of directly performing ion implantation on the N-SiC epitaxial layer 2, a larger ion implantation energy is required when ion implantation is performed to form the PWELL area 3. Due to the addition of the structure of the C thin film layer 10 during the preparation process, the process parameters in the preparation, namely the ion implantation energy, need to be considered more. According to the research of the inventors, 3 to 5 Al ion implantations are required to form the PWELL area 3, and the Al ion implantation dose is 5×10 16 cm -3 ~5×10 18 cm -3 , the implantation energy is 80Kev~160Kev. Such preparation process parameters can control the formation of a PWELL region 3 of a preset depth in the N-SiC epitaxial layer 2.

[0069] The embodiment of the present invention can also control the ion implantation dose of the PWELL region 3 by adjusting the junction pushing temperature, and the junction pushing temperature can be 800° C. to 950° C.

[0070] S108 , removing the C thin film layer 10 outside the ion implantation window of the PWELL region 3 .

[0071] Specifically, see Figure 2 (g) In the embodiment of the present invention, a thermal oxidation process is used to remove the C film layer 10 outside the ion implantation window of the PWELL region 3. The thermal oxidation process may be wet oxidation, and the temperature of the wet oxidation is 950° C. to 1000° C. As in S102, the use of the thermal oxidation process can reduce the surface defects of the interface at this time.

[0072] S108, Removal of SiO 2 Barrier layer 9.

[0073] Specifically, see Figure 2 (h) The SiO2 outside the ion implantation window of PWELL region 3 is removed by wet etching process. 2 The blocking layer 9 is specifically etched by wet etching using a BOE solution, which is composed of 49% HF aqueous solution: 40% NH 4 F aqueous solution = a mixture of components in a ratio of 1:6 (volume ratio).

[0074] S109. Lithographically pattern the ion implantation windows for the P+ implantation regions 4 on the upper surfaces at both ends of the PWELL region 3, and perform ion implantation within the ion implantation windows of the P+ implantation regions 4 to form the P+ implantation regions 4.

[0075] Specifically, please refer to Figure 2 (i). In the embodiments of the present invention, the ion implantation windows for the P+ implantation regions 4 are lithographically patterned on the upper surfaces at both ends of the PWELL region 3 by using photoresist development technology, and then ion implantation is performed within the ion implantation windows of the P+ implantation regions 4 to form the P+ implantation regions 4. Specifically, it includes: using the ion implantation process, performing Al ion implantation with a dose of 1×10 19 cm -3 ~1×10 20 cm -3 and an implantation energy of 80 Kev to 160 Kev to form the P+ implantation regions 4.

[0076] Similarly, in the embodiments of the present invention, the ion implantation dose of the P+ implantation regions 4 can also be controlled by adjusting the drive-in temperature, and the drive-in temperature can be 800 °C to 950 °C.

[0077] S110. Lithographically pattern the ion implantation windows for the N+ source regions 5 on the PWELL region 3, and perform ion implantation within the ion implantation windows of the N+ source regions 5 to form the N+ source regions 5; wherein, the ion implantation windows of the N+ source regions are adjacent to the ion implantation windows of the P+ implantation regions.

[0078] Specifically, please refer to Figure 2 (j). In the embodiments of the present invention, the ion implantation windows for the N+ source regions 5 are lithographically patterned on the PWELL region 3 by using photoresist development technology. The ion implantation windows of the N+ source regions are adjacent to the ion implantation windows of the P+ implantation regions, and then ion implantation is performed within the ion implantation windows of the N+ source regions 5 to form the N+ source regions 5. Specifically, it includes: using the ion implantation process, performing B ion implantation with a dose of 1×10 19 cm -3 ~1×10 20 cm -3 and an implantation energy of 100 Kev to 180 Kev to form the N+ source regions 5.

[0079] Similarly, in the embodiments of the present invention, the ion implantation dose of the N+ source regions 5 can also be controlled by the drive-in temperature, and the drive-in temperature can be 800 °C to 950 °C.

[0080] S111. Grow an oxide layer on the N-SiC epitaxial layer 2, the PWELL region 3, the P+ implantation regions 4, and the N+ source regions 5.

[0081] Specifically, please refer toFigure 2 (k), in the embodiment of the present invention, an oxide layer is grown on the N-SiC epitaxial layer 2, PWELL region 3, N+ source region 5 and P+ implantation region 4, and the material of the oxide layer can be SiO 2 , specifically including: using a thermal oxidation process, an oxide layer with a thickness of is grown on the N-SiC epitaxial layer 2, PWELL region 3, N+ source region 5 and P+ implantation region 4. The thermal oxidation process can be wet oxidation, and the temperature of the wet oxidation is 950°C to 1000°C. Similar to S102, using the thermal oxidation process can reduce the surface defects at the interface at this time.

[0082] S112. Grow an N-type polysilicon thin film layer on the oxide layer.

[0083] Specifically, please refer to Figure 2 (l), in the embodiment of the present invention, an N-type polysilicon thin film layer is grown on the oxide layer, specifically including: using the PECVD process, an N-type polysilicon thin film layer with a thickness of is grown on the oxide layer.

[0084] S113. Lithographically define a gate region on the N-type polysilicon thin film layer, and etch away the oxide layer and the N-type polysilicon thin film layer outside the gate region to form a gate oxide layer 6 and an N-type polysilicon gate 7 respectively.

[0085] Specifically, please refer to Figure 2 (m), in the embodiment of the present invention, a gate region is lithographically defined on the N-type polysilicon thin film layer using photoresist development technology, and then the oxide layer and the N-type polysilicon thin film layer outside the gate region are etched away using the ICP etching process to form a gate oxide layer 6 and an N-type polysilicon gate 7 respectively, so as to complete the preparation of the silicon carbide VDMOSFET device.

[0086] The operations such as MOCVD, PECVD, ICP etching method, wet etching and ion implantation mentioned in the embodiments of the present invention are all prior arts and will not be elaborated here.

[0087] In summary, for the manufacturing process provided by the embodiments of the present invention for improving the threshold voltage stability of a silicon carbide VDMOSFET device, when forming the PWELL region 3 by ion implantation, a C thin film layer is first deposited at the ion implantation window of the PWELL region 3, and then multiple ion implantations are performed to form the PWELL region 3. Due to the introduction of the C thin film layer, the carbon atoms missing due to multiple ion implantation bombardments can be effectively filled, reducing the vacancies and interstitial atoms in the silicon carbide structure and the number of deep-level traps, thereby improving the stability of the threshold voltage. Since the C thin film layer 10 is only used to fill the carbon atoms missing due to multiple ion implantation bombardments, its introduction does not change other performance junction parameters in the device, such as the breakdown voltage and the characteristic on-resistance of the device. Before forming the PWELL region 3, a sacrificial oxide layer 8 is grown and removed on the N-SiC epitaxial layer 2 in the embodiments of the present invention. Such a treatment method can effectively remove the surface defects pre-existing on the surface of the silicon carbide EPI substrate, reducing the influence of such defects on the performance of subsequent device manufacturing. Since the growth and removal of the sacrificial oxide layer 8 are performed on the N-SiC epitaxial layer 2, it does not affect the threshold voltage of the device. The C thin film layer introduced in the embodiments of the present invention solves the defect problem generated in the ion implantation process of the traditional manufacturing process, and at the same time introduces SiO 2 barrier layer 9, which can control the C thin film layer to be well deposited at the ion implantation window of the PWELL region 3 and prevent the deposition of the C thin film layer from affecting other regions except the PWELL region 3, improving the performance of device manufacturing.

[0088] In a second aspect, please refer to Figure 3 for a silicon carbide VDMOSFET device provided by the embodiments of the present invention, including:

[0089] A silicon carbide EPI substrate; wherein, the silicon carbide EPI substrate includes an N+SiC substrate 1 and an N-SiC epitaxial layer 2 located on the N+SiC substrate 1;

[0090] The PWELL region 3, located at both ends within the N-SiC epitaxial layer 2;

[0091] The P+ implantation region 4, located at both ends within the PWELL region 3;

[0092] The N+ source region 5, located within the PWELL region 3, connected to the P+ implantation region, and flush with the surface of the P+ implantation region;

[0093] The gate oxide layer 6, located on the N+ source region 5, the PWELL region 3, and the N-SiC epitaxial layer 2;

[0094] The N-type polysilicon gate 7, located on the gate oxide layer 6;

[0095] Among them, the silicon carbide VDMOSFET device is formed by the above preparation method, and the silicon carbide VDMOSFET device prepared by this preparation method has a stable threshold voltage.

[0096] It should be noted that for the device embodiments, since they are basically similar to the preparation method embodiments, the relevant parts can be referred to the partial descriptions of the preparation method embodiments.

[0097] In the description of the present invention, it should be understood that the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality of" means two or more, unless otherwise specifically defined.

[0098] In the description of the embodiments of the present invention, the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the indicated device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be understood as a limitation to the present invention.

[0099] In the description of this specification, the descriptions referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification.

[0100] Although the present application has been described in connection with various embodiments herein, however, in the process of implementing the claimed present application, those skilled in the art can understand and achieve other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims.

[0101] The above content is a further detailed description of the present invention in combination with specific preferred embodiments. It cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several simple deductions or substitutions can still be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. A preparation process for improving the threshold voltage stability of a silicon carbide VDMOSFET device, characterized in that, it includes: Select a silicon carbide EPI substrate; wherein, the silicon carbide EPI substrate includes an N+ SiC substrate and an N-SiC epitaxial layer located on the N+ SiC substrate; Grow a sacrificial oxide layer on the N-SiC epitaxial layer; Remove the sacrificial oxide layer; Grow SiO on the N-SiC epitaxial layer 2 Barrier layer; On the SiO 2 Photolithography regions of the PWELL region are lithographed on the upper surfaces at both ends of the barrier layer, and the SiO within the photolithography regions of the PWELL region is etched away 2 to form ion implantation windows for the PWELL region in the barrier layer; Using a magnetron sputtering process, on the N-SiC epitaxial layer and the SiO 2 barrier layer, grow a C thin film layer with a thickness of ; Perform multiple ion implantations on the C thin film layer within the ion implantation window of the PWELL region to form the PWELL region; Remove the C thin film layer outside the ion implantation window of the PWELL region; Remove the SiO 2 Barrier layer; Lithograph ion implantation windows for the P+ implantation region on the upper surfaces at both ends of the PWELL region, and perform ion implantation within the ion implantation windows of the P+ implantation region to form the P+ implantation region; Lithograph an ion implantation window for the N+ source region on the PWELL region, and perform ion implantation within the ion implantation window of the N+ source region to form the N+ source region; wherein, the ion implantation window of the N+ source region is adjacent to the ion implantation window of the P+ implantation region; Grow an oxide layer on the N-SiC epitaxial layer, the PWELL region, the P+ implantation region, and the N+ source region; Grow an N-type polysilicon thin film layer on the oxide layer; Lithograph a gate region on the N-type polysilicon thin film layer, and etch away the oxide layer and the N-type polysilicon thin film layer outside the gate region to form a gate oxide layer and an N-type polysilicon gate respectively.

2. The preparation process for improving the threshold voltage stability of a silicon carbide VDMOSFET device according to claim 1, characterized in that, The growing of the sacrificial oxide layer on the N-SiC epitaxial layer includes: Using a thermal oxidation process, grow the sacrificial oxide layer with a thickness of on the N-SiC epitaxial layer.

3. The preparation process for improving the threshold voltage stability of a silicon carbide VDMOSFET device according to claim 1, characterized in that, growing SiO on the N-SiC epitaxial layer 2 a barrier layer, comprising: Using the PECVD process, a SiO barrier layer with a thickness of 2 is grown on the N-SiC epitaxial layer.

4. The preparation process for improving the threshold voltage stability of a silicon carbide VDMOSFET device according to claim 1, characterized in that, The performing of multiple ion implantations on the C thin film layer within the ion implantation window of the PWELL region to form the PWELL region includes: Using the ion implantation process, perform 3 to 5 times of Al ion implantation on the C thin film layer within the ion implantation window of the PWELL region to form the PWELL region; wherein, the dose of each Al ion implantation is 5×10 16 cm -3 ~5×10 18 cm -3 , and the implantation energy is 80 Kev to 160 Kev.

5. The preparation process for improving the threshold voltage stability of a silicon carbide VDMOSFET device according to claim 1, characterized in that, The removing of the C thin film layer outside the ion implantation window of the PWELL region includes: Using a thermal oxidation process to remove the C thin film layer outside the ion implantation window of the PWELL region.

6. The preparation process for improving the threshold voltage stability of a silicon carbide VDMOSFET device according to claim 1, characterized in that, The performing of ion implantation within the ion implantation window of the P+ implantation region to form the P+ implantation region includes: Using an ion implantation process, Al ions with an implantation dose of 1×10 19 cm -3 ~1×10 20 cm -3 and an implantation energy of 80 keV to 160 keV are implanted to form the P+ implantation region within the ion implantation window of the P+ implantation region.

7. The preparation process for improving the threshold voltage stability of a silicon carbide VDMOSFET device according to claim 1, characterized in that, The performing of ion implantation within the ion implantation window of the N+ source region to form the N+ source region includes: Using the ion implantation process, B ions are implanted with a dose of 1×10 19 cm -3 ~1×10 20 cm -3 and an implantation energy of 100 keV to 180 keV to form the N+ source region within the ion implantation window of the N+ source region.

8. The preparation process for improving the threshold voltage stability of a silicon carbide VDMOSFET device according to claim 1, characterized in that, Growing an oxide layer on the N-SiC epitaxial layer, the PWELL region, the N+ source region, and the P+ implantation region includes: Using a thermal oxidation process, an oxide layer with a thickness of is grown on the N-SiC epitaxial layer, the PWELL region, the N+ source region, and the P+ implantation region.

9. The preparation process for improving the threshold voltage stability of a silicon carbide VDMOSFET device according to claim 1, characterized in that, Growing an N-type polysilicon thin film layer on the gate oxide layer includes: Using the PECVD process, grow an N-type polysilicon thin film layer with a thickness of on the gate oxide layer.

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