Transistor structure with air gap and method of making the same

Abstract

A transistor structure with air gap and a method of fabricating the same are disclosed. The transistor structure with air gap includes a substrate, a transistor disposed on the substrate, an etch stop layer covering and contacting the transistor and the substrate, a first dielectric layer covering and contacting the etch stop layer, a second dielectric layer covering the first dielectric layer, a trench located above the gate structure and within the first dielectric layer and the second dielectric layer, wherein the width of the trench within the second dielectric layer is less than the width of the trench within the first dielectric layer, a fill layer disposed in the trench and covering an upper surface of the second dielectric layer, and an air gap disposed in the fill layer.

Description

Technical Field

[0001] This invention relates to an air gap structure and its manufacturing method, and particularly to a manufacturing method and structure for forming an air gap in a groove that is wider at the bottom and narrower at the top. Background Technology

[0002] As the integration density of semiconductor devices increases, the distance between devices also decreases. Because the dielectric layer covering the transistor, such as silicon nitride, has a relatively high dielectric constant, this leads to high parasitic capacitance in the gate and surrounding metal components. This increases power consumption and degrades the performance of the semiconductor wafer. Therefore, current improvements include depositing materials with lower dielectric constant (k) values ​​(such as oxides) in the spaces between devices to replace silicon nitride. However, this approach is no longer sufficient for designs beyond the 30-nanometer generation.

[0003] Therefore, a material that can provide a lower dielectric constant is needed to replace traditional dielectric layer materials. Summary of the Invention

[0004] In view of this, since air can provide a lower dielectric constant than general dielectric materials, the present invention provides a method for manufacturing an air gap structure and the structure thereof, in order to further reduce parasitic capacitance.

[0005] According to a preferred embodiment of the present invention, a transistor structure with an air gap includes a substrate, a transistor disposed on the substrate, wherein the transistor includes a gate structure disposed on the substrate, a source doped region and a drain doped region are respectively buried in the substrate on both sides of the gate structure, an etch stop layer covers and contacts the transistor and the substrate, a first dielectric layer covers and contacts the etch stop layer, a second dielectric layer covers the first dielectric layer, a first plug is disposed in the first dielectric layer and contacts the source doped region, a second plug is disposed in the first dielectric layer and contacts the drain doped region, a first metal layer is disposed in the second dielectric layer and contacts the first plug, a second metal layer is disposed in the second dielectric layer and contacts the second plug, a trench is located above the gate structure and within the first and second dielectric layers, wherein the width of the trench located in the second dielectric layer is smaller than the width of the trench located in the first dielectric layer, a fill layer is disposed in the trench and covers the upper surface of the second dielectric layer, and an air gap is disposed in the fill layer.

[0006] According to another preferred embodiment of the present invention, a method for fabricating a transistor structure with an air gap includes providing a substrate, wherein: a transistor is disposed on the substrate, the transistor includes a gate structure disposed on the substrate, a source doped region and a drain doped region are respectively buried in the substrate on both sides of the gate structure, an etch stop layer covers and contacts the transistor and the substrate, a first dielectric layer covers and contacts the etch stop layer, a second dielectric layer covers the first dielectric layer, and then a dry etching process is performed, using the etch stop layer above the gate structure as a stop layer, etching the second dielectric layer and the first dielectric layer to form a trench, wherein the width of the trench located in the second dielectric layer is smaller than the width of the trench located in the first dielectric layer, and finally a fill layer is formed to cover the trench and close the opening of the trench to form an air gap in the fill layer.

[0007] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. However, the following preferred embodiments and drawings are for reference and illustration only and are not intended to limit the present invention. Attached Figure Description

[0008] Figures 1 to 5 A schematic diagram illustrating a method for fabricating a transistor structure with an air gap, as shown in a preferred embodiment of the present invention;

[0009] Figure 6 A schematic diagram illustrating a transistor structure with an air gap, as shown in another preferred embodiment of the present invention;

[0010] Figure 7 A schematic diagram illustrating a transistor structure with an air gap, as shown in another preferred embodiment of the present invention;

[0011] Figures 8 to 9 A schematic diagram illustrating a method for fabricating an air gap on a transistor, as shown in another preferred embodiment of the present invention;

[0012] Figure 10 This is a schematic diagram of a transistor structure with an air gap, illustrating an exemplary example of the present invention.

[0013] Explanation of main component symbols

[0014] 10: Base

[0015] 12: Transistor

[0016] 14: Gate Structure

[0017] 16: Gate

[0018] 18: Gate dielectric layer

[0019] 20: Interstitial wall

[0020] 22: Source doped region

[0021] 24: Drain doped region

[0022] 26: Etching Stop Layer

[0023] 28: First dielectric layer

[0024] 30: Dielectric layer

[0025] 32: Second dielectric layer

[0026] 34: First plug

[0027] 36: Second plug

[0028] 38: First metal layer

[0029] 40: Second metal layer

[0030] 42: Hard Mask

[0031] 44: Photoresist layer

[0032] 46: Trench

[0033] 46a: Bottom

[0034] 46b: Corner

[0035] 48: Fill layer

[0036] 50: Air gap

[0037] 146: Trench

[0038] D1: First shortest distance

[0039] D2: Second shortest distance

[0040] W1: Width

[0041] W2: Width

[0042] W3: Width

[0043] W4: Width

[0044] W5: Width

[0045] W6: Width

[0046] W7: Width

[0047] W8: Width

[0048] X: Horizontal direction Detailed Implementation

[0049] Figures 1 to 5A method for fabricating a transistor structure with an air gap is illustrated according to a preferred embodiment of the present invention.

[0050] like Figure 1 As shown, a substrate 10 is first provided, a transistor 12 is disposed on the substrate 10, the transistor 12 includes a gate structure 14 disposed on the substrate 10, the gate structure 14 includes a gate 16 and a gate dielectric layer 18, the gate dielectric layer 18 is disposed between the substrate 10 and the gate 16, a spacer 20 surrounds the gate structure 14, a source doped region 22 and a drain doped region 24 are respectively buried in the substrate 10 on both sides of the gate structure 14, an etch stop layer 26 conformally covers and contacts the transistor 12 and the substrate 10, a first dielectric layer 28 conformally covers and contacts the etch stop layer 26, a dielectric layer 30 is selectively formed, a second dielectric layer 32 covers the first dielectric layer 28. Since the dielectric layer 30 is selectively disposed, if a dielectric layer 30 is disposed, the dielectric layer 30 will be located between the first dielectric layer 28 and the second dielectric layer 32. In this embodiment, the presence of a dielectric layer 30 is taken as an example. A horizontal direction X is defined as a direction parallel to the upper surface of the substrate 10.

[0051] In addition, a first plug 34 is disposed in the first dielectric layer 28 and the etch stop layer 26 and contacts the source doped region 22, a second plug 36 is disposed in the first dielectric layer 28 and the etch stop layer 26 and contacts the drain doped region 22, a first metal layer 38 is disposed in the second dielectric layer 32 and contacts the first plug 34, and a second metal layer 40 is disposed in the second dielectric layer 32 and contacts the second plug 36. The width W1 of the first plug 34 and the width W2 of the second plug 36 are both smaller than the width W3 of the first metal layer 38 and the width W4 of the second metal layer 40. The aforementioned widths W1 / W2 / W3 / W4 are all parallel to the horizontal direction X. The first plug 34 and the second plug 36 have a first shortest distance D1 in the horizontal direction X, and the first metal layer 38 and the second metal layer 40 have a second shortest distance D2 in the horizontal direction X. Since the widths of the plugs and the metal layers are different, the second shortest distance D2 is smaller than the first shortest distance D1. That is to say, the space between the first metal layer 38 and the second metal layer 40 is smaller than the space between the first plug 34 and the second plug 36.

[0052] Next, a hard mask 42 and a photoresist layer 44 are formed on the second dielectric layer 32. Then, the photoresist layer 44 is patterned, and the positions where trenches will be formed are transferred onto the photoresist layer 44. After that, the hard mask 42 is etched using the photoresist layer 44 as a mask to transfer the pattern on the photoresist layer 44 onto the hard mask 42.

[0053] like Figure 2 and Figure 3As shown, an anisotropic etching process is performed using a hard mask 42 as a mask, such as a dry etching process. This dry etching process includes etching the second dielectric layer 32, dielectric layer 30, and first dielectric layer 28, using an etch stop layer 26 as a stop layer. More specifically, in Figure 2 In the process, the second dielectric layer 32 is etched using a dry etching process. When the dielectric layer 30 is etched, the etching gas is switched and the etching of the dielectric layer 30 continues until the first dielectric layer 28 is exposed.

[0054] Then Figure 3 As shown, the etching gas is adjusted again to use the etch stop layer 26 above the gate structure 12 as the stop layer for etching the first dielectric layer 28. That is, the etching of the first dielectric layer 28 is stopped when the etch stop layer 26 is exposed. At this time, a trench 46 is formed in the second dielectric layer 32, the dielectric layer 30, and the first dielectric layer 28. It is worth noting that the width W5 of the trench 46 located in the second dielectric layer 32 is smaller than the width W6 of the trench 46 located in the first dielectric layer 28. The widths W5 / W6 here are also parallel to the horizontal direction X. The dry etching process of the present invention utilizes the adjustment of the flow rate of each component of the etching gas so that the etching rate of the etching gas in the horizontal direction X when etching the second dielectric layer 32 is less than the etching rate of the etching gas in the horizontal direction X when etching the first dielectric layer 28. This results in the trench 46 having a shape that is larger at the bottom and smaller at the top. As mentioned above, because the second shortest distance D2 is smaller than the first shortest distance D1, the shape of the trench 46 must also match the size of the second shortest distance D2 and the first shortest distance D1. The width of the trench 46 can be increased or decreased according to the product design, but the limit of its increase is that the first metal layer 38, the second metal layer 40, the first plug 34 and the second plug 36 cannot be exposed from the sidewall of the trench 46. Otherwise, the first metal layer 38, the second metal layer 40, the first plug 34 and the second plug 36 will be damaged by the etching gas and affect their conductivity. That is to say, when performing dry etching, the width of the trench 46 must comply with the limitation that the width W5 of the trench in the second dielectric layer 32 must be smaller than the second shortest distance D2, and the width W6 of the trench 46 located in the first dielectric layer 28 must be smaller than the first shortest distance D1.

[0055] For example, when etching the second dielectric layer 32 using a dry etching process, a mixture of O2, C5F8, CO, and Ar can be used as the etching gas. Similarly, when etching the first dielectric layer 28 using a dry etching process, O2, C5F8, CO, and Ar can also be used as the etching gas. However, the O2 flow rate is slower when etching the first dielectric layer 28, meaning the O2 concentration in the etching gas used for etching the first dielectric layer 28 is lower than the O2 concentration in the etching gas used for etching the second dielectric layer 32. Furthermore, when etching the first dielectric layer 28 to the etch stop layer 26, an over-etch is added to enhance etching in the horizontal X direction, thereby widening the trench 26 within the first dielectric layer 28.

[0056] like Figure 4 As shown, after removing the photoresist 44 and completing the trench 46, a selective cleaning process can be performed to remove etching residues. During the cleaning process, the second dielectric layer 32 and the first dielectric layer 28 are partially removed by the cleaning solution, and the removal rate of the second dielectric layer 32 is less than that of the first dielectric layer 28. A cleaning solution specifically designed to remove both the second and first dielectric layers 32 is chosen for the cleaning process, allowing for a more pronounced width difference between the trench 46 in the first and second dielectric layers 28 while removing etching residues. A mixture of HF, NH4F, and water can be used as the cleaning solution. After the cleaning process, the width of the trench 46 in the second dielectric layer 32 is increased from width W5 to width W7, and the width of the trench 46 in the first dielectric layer 28 is increased from width W6 to width W8. However, the principle that the width W7 in the second dielectric layer 32 is smaller than the width W8 in the first dielectric layer 26 is still maintained. Furthermore, the width W7 is smaller than the second shortest distance D2, and the width W8 is smaller than the first shortest distance D1.

[0057] like Figure 5As shown, a filler layer 48 is formed to cover the trench 46 and seal the opening of the trench 46 to form an air gap 50 in the filler layer 48. When forming the filler layer 48, a fabrication process is specifically used where the deposition rate at the bottom 46a of the trench 46 is lower than the deposition rate at the corner 46b of the trench 46. The corner 46b of the trench 46 is formed by the sidewalls of the trench 46 and the upper surface of the second dielectric layer 32. According to a preferred embodiment of the present invention, the filler layer 48 can be formed using a plasma-enhanced chemical vapor deposition (PECVD) process or a high-density plasma chemical vapor deposition (HDPCVD) process, but is not limited to these. Any fabrication process that meets the requirement that the deposition rate at the bottom 46a of the trench 46 is lower than the deposition rate at the corner 46b of the trench 46 can be used to form the filler layer 48.

[0058] Please continue reading. Figure 5 In the bottom 46a of trench 46, there may be no contact with the filler layer 48, meaning that part of the etch stop layer 26 above the gate structure 12 is not contacted by the filler layer 48. However, after adjusting the deposition conditions, such as Figure 7 The bottom 46a of the trench 46 shown can be completely covered by the filling layer 48. Furthermore, the shape of the air gap 50 can be changed by adjusting the deposition conditions, for example, in... Figure 5 The air gap 50 is bell-shaped. Figure 6 The air gap 50 is teardrop-shaped, or like... Figure 7 The air gap 50 is triangular.

[0059] Figures 8 to 9 A method for fabricating an air gap on a transistor is illustrated according to another preferred embodiment of the present invention, wherein components having the same function will be used with... Figures 1 to 5 The same component symbols. As explained above. Figures 2 to 3 The dry etching process forms trenches 46 with inclined sidewalls, but according to another preferred embodiment of the present invention, such as... Figure 8 As shown, after etching the second dielectric layer 32, dielectric layer 30, and first dielectric layer 28 using a dry etching process, the resulting trench 46 can have vertical sidewalls. Furthermore, by controlling the etching gas, the width W5 of the trench 46 in the second dielectric layer 32 is made smaller than the width W6 of the trench 46 in the first dielectric layer 28. This results in the trench 46 having an inverted T-shaped profile. Then, as... Figure 9As shown, a filling layer 48 is formed to cover the trench 46 and close the opening of the trench 46 to form an air gap 50 in the filling layer 46. Similarly, the air gap 50 can be bell-shaped or as shown in the figure. Figure 6 The image depicts a teardrop shape or something similar. Figure 7 The diagram depicts a triangle. Furthermore, the fill layer 48 may partially cover the etch stop layer 26 on the gate structure 14, or... Figure 7 The example shown is an etch stop layer 26 that completely covers the gate structure 14.

[0060] According to a preferred embodiment of the present invention, such as Figure 5 As shown, a transistor structure with an air gap includes a substrate 10, with a horizontal direction X parallel to the upper surface of the substrate 10. The substrate 10 includes a silicon substrate, a germanium substrate, a gallium arsenide substrate, a silicon-germanium substrate, an indium phosphide substrate, a gallium nitride substrate, a silicon carbide substrate, or a silicon-coated insulating substrate. A transistor 12 is disposed on the substrate, wherein the transistor 12 includes a gate structure 14 disposed on the substrate 10. A source doped region 22 and a drain doped region 24 are respectively buried in the substrate 10 on both sides of the gate structure 14. A spacer 20 surrounds the gate structure 14. An etch stop layer 26 conformally covers and contacts the transistor 12 and the substrate 10. A first dielectric layer 28 conformally covers and contacts the etch stop layer 26. A dielectric layer 30 conformally covers and contacts the first dielectric layer 28. A second dielectric layer 32 conformally covers and contacts the dielectric layer 30. The first dielectric layer 28 and the second dielectric layer 32 are made of different materials. According to a preferred embodiment of the present invention, the first dielectric layer 28 can be undoped silicon dioxide deposited using tetraethyl orthosilicate (TEOS) as the reactive gas, while the second dielectric layer 32 is fluorinated silicon glass (FSG), the dielectric layer 30 is silicon oxynitride, and the etch stop layer is silicon nitride. However, the first dielectric layer 28, the second dielectric layer 32, the dielectric layer 30, and the etch stop layer 26 are not limited to the above materials. The first dielectric layer 28, the second dielectric layer 32, the dielectric layer 30, and the etch stop layer 26 can each contain insulating materials such as silicon oxide, silicon nitride, silicon carbide nitride, silicon oxynitride, or silicon carbide nitride.

[0061] A first plug 34 is disposed in the first dielectric layer 28 and contacts the source doped region 22; a second plug 36 is disposed in the first dielectric layer 28 and contacts the drain doped region 24; a first metal layer 38 is disposed in the second dielectric layer 32 and contacts the first plug 34; a second metal layer 40 is disposed in the second dielectric layer 32 and contacts the second plug 36. The first plug 34 and the second plug 36 have a first shortest distance D1 in the horizontal direction X; the first metal layer 38 and the second metal layer 40 have a second shortest distance D2 in the horizontal direction X. The second shortest distance D2 is less than the first shortest distance D1. The first plug 34, the second plug 36, the first metal layer 37, and the second metal layer 40 may each contain aluminum, titanium, tantalum, tungsten, copper, titanium nitride, titanium carbide, tantalum nitride, titanium and titanium nitride (Ti / TiN), or other conductive materials.

[0062] A trench 46 is located above and overlaps with the gate structure 14 and is within the first dielectric layer 28 and the second dielectric layer 32. Specifically, the trench 46 is located between the first plug 34 and the second plug 36 and is directly above the gate structure 14. The width W7 of the trench 46 located within the second dielectric layer 32 is smaller than the width W8 of the trench 46 located within the first dielectric layer 28. (See also...) Figure 4 The positions of widths W7 / W8 are obtained, both of which are parallel to the horizontal direction X. The bottom 46a of the trench 46 is formed by the etch stop layer 26. Furthermore, the width W7 of the trench 46 within the second dielectric layer 32 is less than the second shortest distance D2, and the width W8 of the trench 46 within the first dielectric layer 28 is less than the first shortest distance D1. Additionally, a fill layer 48 is disposed in the trench 46 and covers the upper surface of the second dielectric layer 32, and an air gap 50 is disposed in the fill layer. The fill layer 48 comprises insulating materials such as silicon oxide, silicon nitride, silicon carbide nitride, silicon oxynitride, or silicon carbide nitride. It is noteworthy that the width of the air gap 50 closer to the gate structure 14 is greater than the width of the air gap farther from the gate structure 14. Similarly, the width of the air gap 50 is parallel to the horizontal direction X. Figure 5 The air gap 50 in the example is bell-shaped, but not limited to this. However, according to another preferred embodiment of the invention, such as... Figure 6 As shown, the width of the air gap 50 can also be adjusted according to different product requirements, such that the width of the air gap 50 closer to the gate structure 14 is smaller than the width of the air gap 50 farther from the gate structure 14. Figure 6 The air gap 50 shown in the example is teardrop-shaped, but is not limited to this.

[0063] Please refer to it again. Figure 5The sidewalls of trench 46 and the upper surface of the second dielectric layer 32 form a corner 46b. The thickness of the filling layer 48 at the bottom 46a of trench 46 is less than the thickness of the filling layer 48 at corner 46b. Furthermore, the air gap 50 is located between the first plug 34 and the second plug 36 and directly above the gate structure 14. According to a preferred embodiment of the invention, the corner 46b is less than 90 degrees because trench 46 has a narrower top and wider bottom, meaning the width W7 of trench 46 within the second dielectric layer 32 is less than the width W8 of trench 46 within the first dielectric layer 28 (see [link to previous text]). Figure 4 (Obtain the position of width W7 / W8).

[0064] Figure 10 A transistor structure with an air gap is illustrated as an example of the present invention, wherein elements having the same function will use the same... Figure 5 The same component symbol in the text. For example... Figure 10 As shown, the air gap 50 is formed at a distance from the gate structure 14, that is, with the first dielectric layer 28 as the bottom of the trench 146. Therefore, it does not help much in preventing parasitic capacitance between the gate structure 14 and the first plug 34, or between the gate structure 14 and the second plug 36.

[0065] Compared to the exemplary example, this invention specifically uses the etch stop layer 26 that contacts the gate structure 14 as a stop layer when etching the trench 46. This allows the subsequently formed air gap 50 to be positioned very close to the gate structure 14, thereby reducing the parasitic capacitance between the gate structure 14 and the first plug 34, as well as between the gate structure 14 and the second plug 36, and also reducing the parasitic capacitance between the gate structure 14 and the first metal layer 38, as well as between the gate structure 14 and the second metal layer 40. Furthermore, the air gap 50 in the second dielectric layer 32 can reduce the parasitic capacitance between the first metal layer 38 and the second metal layer 40. In addition, this invention also specifically increases the width of the trench 46 within the first dielectric layer 28, resulting in a larger width for the air gap 50 closer to the gate structure 14, further reducing the parasitic capacitance between the gate structure 14 and the plug.

[0066] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A transistor structure with an air gap, characterized in that, Include: Base; A transistor is disposed on the substrate, wherein the transistor includes: a gate structure disposed on the substrate, and a source doped region and a drain doped region respectively buried in the substrate on both sides of the gate structure; Etch a stop layer to cover and contact the transistor and the substrate; The first dielectric layer covers and contacts the etch stop layer; A second dielectric layer covers the first dielectric layer; A first plug is disposed in the first dielectric layer and contacts the source doped region; The second plug is disposed in the first dielectric layer and contacts the drain doped region; A first metal layer is disposed in the second dielectric layer and contacts the first plug; A second metal layer is disposed in the second dielectric layer and contacts the second plug; A trench is located above the gate structure and within the first dielectric layer and the second dielectric layer, wherein the width of the trench within the second dielectric layer is smaller than the width of the trench within the first dielectric layer, and the first metal layer, the second metal layer, the first plug, and the second plug are not exposed from the sidewalls of the trench, wherein the sidewalls of the trench satisfy one of the following two conditions (a) and (b): (a) The sidewall of the trench includes a first flat sidewall near the first plug and the first metal layer and a second flat sidewall near the second plug and the second metal layer, the first flat sidewall and the second flat sidewall each extending continuously from the upper surface of the etch stop layer to the upper surface of the second dielectric layer, the first flat sidewall not being parallel to the sidewalls of the first plug and the first metal layer near the trench, and the second flat sidewall not being parallel to the sidewalls of the second plug and the second metal layer near the trench; (b) The sidewall of the trench includes a first sub-sidewall defined by the first dielectric layer and a second sub-sidewall defined by the second dielectric layer, the first sub-sidewall and the second sub-sidewall being misaligned with each other; A filling layer is disposed in the trench and covers the upper surface of the second dielectric layer; and An air gap is provided in this filling layer.

2. The transistor structure with an air gap as claimed in claim 1, wherein the width of the air gap closer to the gate structure is greater than the width of the air gap farther from the gate structure.

3. The transistor structure with an air gap as described in claim 1, wherein the air gap is bell-shaped, teardrop-shaped, or triangular.

4. The transistor structure with an air gap as claimed in claim 1, wherein the first plug and the second plug have a first shortest distance in the horizontal direction, the first metal layer and the second metal layer have a second shortest distance in the horizontal direction, the second shortest distance being less than the first shortest distance, and the horizontal direction being parallel to the upper surface of the substrate.

5. The transistor structure with an air gap as claimed in claim 4, wherein the width of the trench located in the second dielectric layer is less than the second shortest distance, and the width of the trench located in the first dielectric layer is less than the first shortest distance.

6. The transistor structure with an air gap as claimed in claim 1, wherein the bottom of the trench is the etch stop layer.

7. The transistor structure with an air gap as claimed in claim 1, wherein the sidewall of the trench and the second dielectric layer form a corner, and the thickness of the filling layer at the bottom of the trench is less than the thickness of the filling layer at the corner.

8. The transistor structure with an air gap as claimed in claim 1, wherein the first dielectric layer and the second dielectric layer are made of different materials.

9. The transistor structure with an air gap as claimed in claim 1, wherein the air gap is located between the first plug and the second plug and is directly above the gate structure.

10. A method for fabricating a transistor structure with an air gap, comprising: Provide a base, wherein: A transistor is disposed on the substrate, the transistor includes a gate structure disposed on the substrate, a source doped region and a drain doped region are respectively buried in the substrate on both sides of the gate structure, an etch stop layer covers and contacts the transistor and the substrate, a first dielectric layer covers and contacts the etch stop layer, a second dielectric layer covers the first dielectric layer, a first plug and a second plug are disposed in the first dielectric layer, a first metal layer and a second metal layer are disposed in the second dielectric layer, the first metal layer contacts the first plug, and the second metal layer contacts the second plug; A dry etching process is performed, using the etch stop layer above the gate structure as the stop layer, to etch the second dielectric layer and the first dielectric layer to form a trench. The width of the trench located in the second dielectric layer is smaller than the width of the trench located in the first dielectric layer, and the first metal layer, the second metal layer, the first plug, and the second plug are not exposed from the sidewalls of the trench. The sidewalls of the trench satisfy one of the following two conditions (a) and (b): (a) The sidewall of the trench includes a first flat sidewall near the first plug and the first metal layer and a second flat sidewall near the second plug and the second metal layer, the first flat sidewall and the second flat sidewall each extending continuously from the upper surface of the etch stop layer to the upper surface of the second dielectric layer, the first flat sidewall not being parallel to the sidewalls of the first plug and the first metal layer near the trench, and the second flat sidewall not being parallel to the sidewalls of the second plug and the second metal layer near the trench; (b) The sidewalls of the trench include a first sub-sidewall defined by the first dielectric layer and a second sub-sidewall defined by the second dielectric layer, the first sub-sidewall and the second sub-sidewall being misaligned with each other; and A filling layer is formed to cover the trench and seal the opening of the trench to create an air gap in the filling layer.

11. The method for fabricating a transistor structure with an air gap as described in claim 10, wherein the dry etching process adjusts the etching gas flow rate so that the width of the trench in the second dielectric layer is smaller than the width of the trench in the first dielectric layer.

12. The method of fabricating a transistor structure with an air gap as claimed in claim 10, further comprising performing a cleaning process after the etching process and before the formation of the fill layer, wherein during the cleaning process, the second dielectric layer and the first dielectric layer are partially removed by a cleaning solution, and the rate at which the second dielectric layer is removed is less than the rate at which the first dielectric layer is removed.

13. The method of fabricating a transistor structure with an air gap as described in claim 10, wherein the first plug contacts the source doped region and the second plug contacts the drain doped region.

14. The method of fabricating a transistor structure with an air gap as claimed in claim 13, wherein the trench is located between the first plug and the second plug and is directly above the gate structure.

15. The method for fabricating a transistor structure with an air gap as claimed in claim 13, wherein the first plug and the second plug have a first shortest distance in the horizontal direction, and the first metal layer and the second metal layer have a second shortest distance in the horizontal direction, the second shortest distance being less than the first shortest distance.

16. The method of fabricating a transistor structure with an air gap as claimed in claim 15, wherein the width of the trench located in the second dielectric layer is less than the second shortest distance, and the width of the trench located in the first dielectric layer is less than the first shortest distance.

17. The method of fabricating a transistor structure with an air gap as claimed in claim 10, wherein the sidewall of the trench and the upper surface of the second dielectric layer form an angle, and the formation rate of the filling layer at the bottom of the trench is less than the formation rate at the angle.

18. The method for fabricating a transistor structure with an air gap as described in claim 10, wherein the filling layer is fabricated using a plasma-assisted chemical vapor deposition process or a high-density plasma deposition process.

19. The method for fabricating a transistor structure with an air gap as described in claim 10, wherein the air gap is bell-shaped, teardrop-shaped, or triangular.

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