Memory structure and method of forming a memory structure

Abstract

The present invention relates to a memory structure and a method for forming the memory structure. A memory structure is provided, comprising: a substrate; a first well region, a second well region and a third well region arranged in the substrate, wherein the first well region and the third well region may have a first conductivity type, the second well region may have a second conductivity type different from the first conductivity type, and wherein the second well region may be arranged laterally between the first well region and the third well region. The memory structure also includes a first gate structure and a second gate structure arranged above the second well region. The first gate structure may extend above the third well region, and the second gate structure may extend above the first well region.

Description

Technical Field

[0001] The present disclosure relates generally to memory structures and methods of forming memory structures. Background Art

[0002] Non-volatile memory devices are often used in various consumer electronic products, such as smartphones and tablet computers. One type of non-volatile memory device may be a two-transistor single capacitor (2T1C) memory device, which typically includes a floating gate, a select transistor, and a coupling capacitor. This memory device is a one-bit memory device and is typically large in size. To form a two-bit memory device, two such memory devices may be coupled together, but the size of the resulting memory device is even larger.

[0003] It would therefore be desirable to provide improved two-bit memory devices having smaller sizes. Summary of the invention

[0004] According to various non-limiting embodiments, a memory structure may be provided, comprising: a substrate; a first well region, a second well region, and a third well region arranged within the substrate, wherein the first well region and the third well region may have a first conductivity type, the second well region may have a second conductivity type different from the first conductivity type, and wherein the second well region may be laterally arranged between the first well region and the third well region; a first gate structure arranged above the second well region, wherein the first gate structure may extend above the third well region; and a second gate structure arranged above the second well region, wherein the second gate structure may extend above the first well region.

[0005] According to various non-limiting embodiments, a method for forming a memory structure may be provided, the method comprising: providing a substrate; forming a first well region, a second well region, and a third well region in the substrate, wherein the first well region and the third well region may have a first conductivity type, the second well region may have a second conductivity type different from the first conductivity type, and wherein the second well region may be laterally arranged between the first well region and the third well region; forming a first gate structure above the second well region, wherein the first gate structure may extend above the third well region; and forming a second gate structure above the second well region, wherein the second gate structure may extend above the first well region. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In the accompanying drawings, like reference numerals generally refer to the same parts throughout the different views. Also, the drawings are not necessarily drawn to scale, but emphasis is generally placed on illustrating the principles of the invention. Now, for purposes of example only, non-limiting embodiments of the present invention will be described with reference to the following drawings, in which:

[0007] Figure 1A shows a simplified top view of a memory structure according to various non-limiting embodiments, Figure 1B , Figure 1C and Figure 1D They are shown respectively Figure 1A A first simplified cross-sectional view, a second simplified cross-sectional view, and a third simplified cross-sectional view of a memory structure of FIG.

[0008] Figure 2 Shows the description of the formation Figure 1A A flowchart of a method for configuring a memory structure. DETAILED DESCRIPTION

[0009] Embodiments generally relate to memory structures. More specifically, some embodiments relate to non-volatile memory structures. The non-volatile memory structures can be used in various consumer electronic products, such as smartphones and tablets, and microcontroller units (MCUs).

[0010] Various aspects of the present invention and certain features, advantages and details thereof are explained more fully below with reference to the non-limiting examples shown in the accompanying drawings. Descriptions of known materials, manufacturing tools, processing techniques, etc. are omitted so as not to unnecessarily obscure the present invention with details. However, it should be understood that the detailed description and specific examples, although indicating aspects of the present invention, are given only by way of example and not by way of limitation. Various substitutions, modifications, additions and / or arrangements within the spirit and / or scope of the basic inventive concept will be apparent to those skilled in the art through this disclosure.

[0011] As used throughout the specification and claims, approximate language may be used to modify any quantitative representation that is permissible to vary without causing a change in the basic function associated therewith. Therefore, a value modified by one or more terms such as "approximately" or "about" is not limited to the exact value specified. In some cases, approximate language may correspond to the accuracy of the instrument used to measure the value. In addition, a direction modified by one or more terms such as "substantially" means that the direction is applied within the normal tolerance range of the semiconductor industry. For example, "substantially parallel" means extending approximately in the same direction within the normal tolerance range of the semiconductor industry, while "substantially perpendicular" means an angle of ninety degrees plus or minus the normal tolerance of the semiconductor industry.

[0012] The terms used herein are only for the purpose of describing specific examples and are not intended to limit the present invention. As used herein, the singular forms "a", "an" and "the" are also intended to include plural forms, unless the context clearly indicates otherwise. It will also be understood that the terms "comprise" (and any form of including, such as "comprises" and "comprising"), "have" (and any form of having, such as "has" and "having"), "include" (and any form of including, such as "includes" and "including"), and "contain" (and any form of containing, such as "contains" and "containing") are open linking verbs. Therefore, a method or device that "includes", "has", "includes" or "contains" one or more steps or elements has these one or more steps or elements, but is not limited to having only these one or more steps or elements. Similarly, a method step or device element that "includes", "has", "includes" or "contains" one or more features has these one or more features, but is not limited to having only these one or more features. In addition, a device or structure configured in a certain way is configured at least in this way, but can also be configured in an unlisted way.

[0013] As used herein, when used to refer to two physical elements, the term "connected" indicates a direct connection between the two physical elements. However, the term "coupled" may indicate a direct connection or a connection through one or more intermediate elements.

[0014] As used herein, the terms "may" and "may be" indicate: the possibility of occurring under a set of circumstances; possessing a specified quality, characteristic, or function; and / or qualifying another verb by expressing one or more of the ability, function, or possibility associated with the qualifying verb. Thus, the use of "may" and "may be" indicates that the modifier is clearly suitable, permitted, or appropriate for the specified ability, function, or use, while taking into account that in certain circumstances the modifier is sometimes not suitable, permitted, or appropriate. For example, in certain circumstances, an event or ability can be expected, while in other circumstances, the event or ability cannot occur - this distinction is captured by the terms "may" and "may be".

[0015] Figure 1A A simplified top view of a memory structure 100 is shown in accordance with various non-limiting embodiments. Figure 1B , 1C1D and 1D illustrate simplified cross-sectional views of the memory structure 100 taken along lines AA', BB', and CC', respectively. The memory structure 100 may be a nonvolatile memory structure, such as a multi-time programmable (MTP) nonvolatile memory structure.

[0016] refer to Figure 1A , the memory structure 100 may include a substrate 102. The substrate 102 may be a semiconductor substrate. For example, the substrate 102 may include a semiconductor material such as, but not limited to, silicon (Si), germanium (Ge), silicon carbide (SiC), or a combination thereof.

[0017] The memory structure 100 may further include a plurality of well regions, including first, second, third, fourth, fifth, sixth, and seventh well regions 104 disposed within the substrate 102. 1 -104 7 . The first to seventh well regions 104 1 -104 7 The above-mentioned order may be arranged laterally adjacent to each other along the first direction X. Figure 1A As shown, the first set of well regions 104 1 , 104 3 , 104 5 , 104 7 The length L1 of the second set of well regions 104 may be approximately equal. 2 , 104 4 , 104 6 The length L2 of the first well region 104 may be approximately equal, wherein L2 may be greater than L1. 1 , 104 3 , 104 5 , 104 7 The width W1 of the second set of well regions 104 may be approximately equal. 2 , 104 4 , 104 6 The widths W2 can be approximately equal, where W1 can be greater than W2.

[0018] Each well region 104 1 -104 7 One or more dopants may be included. The first set of well regions 104 1 , 104 3 , 104 5 , 104 7 may have a first conductivity type (in other words, may include a dopant having the first conductivity type); and the second set of well regions 104 2 , 104 4 , 104 6The second group of well regions 104 having the second conductivity type may have a second conductivity type (in other words, may include a dopant having the second conductivity type). The second conductivity type may be different from the first conductivity type. In other words, the second group of well regions 104 having the second conductivity type 2 , 104 4 , 104 6 Each well region in the first group of well regions 104 having a first conductivity type may be arranged laterally. 1 , 104 3 , 104 5 , 104 7 For example, the second well region 104 2 The first well region 1041 and the third well region 104 may be arranged laterally. 3 Fourth well region 104 4 can be arranged laterally in the third well region 104 3 and the fifth well region 104 5 The sixth well region 104 6 can be arranged laterally in the fifth well region 104 5 and the seventh well region 104 7 In an exemplary non-limiting embodiment, the first conductivity type may be N-type and the second conductivity type may be P-type. However, the first conductivity type may alternatively be P-type and the second conductivity type may alternatively be N-type. P-type dopants include, but are not limited to, boron (B), indium (In), or a combination thereof, and N-type dopants include, but are not limited to, phosphorus (P), arsenic (As), antimony (Sb), or a combination thereof. Well region 104 1 -104 7 The doping concentration of each of the two may be approximately equal and may be between about 1×10 15 / cm 3 About 1×10 17 / cm 3 between.

[0019] The memory structure 100 may further include a plurality of isolation elements, wherein each isolation element may be arranged between two adjacent well regions 104. 1 -104 7 For example, refer to Figure 1C and Figure 1D , the first isolation element 106 1 The first well region 104 may be arranged 1 and the second well region 104 2 and the second isolation element 106 2 The second well region 104 may be arranged 2 and the third well region 104 3 Each isolation element (e.g. 106 1 , 1062 ) may include an isolation / electrical insulating material, such as, but not limited to, a dielectric material, such as silicon oxide. In a non-limiting embodiment, each isolation element (e.g., 106 1 , 106 2 ) can be a shallow trench isolation element. Note that for clarity of illustration, the isolation element is not shown in FIG. Figure 1A Shown in.

[0020] like Figure 1B As shown, the memory structure 100 may further include a second well region 104 disposed 2 The plurality of conductive regions (including the first, second and third conductive regions 108) within 1 , 108 2 , 108 3 ). For example, the first, second and third conductive regions 108 1 , 108 2 , 108 3 The second conductive regions 108 may be arranged laterally adjacent to each other along a second direction Y substantially perpendicular to the first direction X. 2 can be arranged in the first conductive region 108 1 and the third conductive region 108 3 Conductive region 108 1 , 108 2 , 108 3 Therefore, the second well region 104 2 A portion of the first and second conductive regions 108 may be arranged 1 , 108 2 and the second well region 104 2 Another part may be arranged in the second and third conductive regions 108 2 , 108 3 The second well region 104 2 These portions may form a channel region. Conductive region 108 1 , 108 2 , 108 3 One or more dopants may be included and may have a first conductivity type. The first, second, and third conductive regions 108 1 , 108 2 , 108 3 The doping concentration of each of the two well regions may be approximately equal and may be higher than that of the second well region 104. 2 For example, the first, second and third conductive regions 108 1 , 108 2 , 108 3 The doping concentration of each of the 19 / cm3 About 1×10 20 / cm 3 Between. Figure 1B As shown, the silicide layer 110 1 -110 3 The second well region 104 may be arranged 2 The first, second and third conductive regions 108 within 1 -108 3 Note that although Figure 1B Each silicide layer 110 1 -110 3 Depicted with corresponding conductive regions 108 1 -108 3 Completely overlapped, but each silicide layer 110 1 -110 3 may alternatively be connected to the corresponding conductive area 108 1 -108 3 Each silicide layer 110 1 -110 3 The first, second and third conductive regions 108 may include silicide materials such as, but not limited to, cobalt silicide, nickel silicide, titanium silicide, tantalum silicide or a combination thereof. 1 , 108 2 , 108 3 Similar conductive regions may be arranged in a similar manner in the fourth and sixth well regions 104. 4 , 104 6 In each of the , a silicide layer may also be disposed over each of these conductive regions.

[0021] refer to Figure 1A and 1B , the memory structure 100 may include a second well region 104 disposed 2 , the fourth well region 104 4 and the sixth well region 104 6 The upper plurality of bit line connectors (the first to ninth bit line connectors 112 1 -112 9 ). Bit line connector 112 1 -112 9 Each bit line connector 112 may include a conductive material such as, but not limited to, aluminum, copper, tungsten, alloys thereof, or combinations thereof. 1 -112 9 The second, fourth and sixth well regions 104 may be 2 , 104 4 , 104 6 For example, Figure 1BAs shown, the first bit line connector 112 1 The second well region 104 may be arranged 2 The first conductive region 108 1 The second bit line connector 1122 may be arranged in the second well region 104 2 The third conductive region 108 3 The first and second bit line connectors 112 are electrically coupled to the first and second bit line connectors 112. 1 , 112 2 can be configured to respectively connect the first and third conductive regions 108 1 , 108 3 On the other hand, the second conductive region 108 2 It may be a floating junction region that may not be electrically coupled to any external voltage. 2 There may be no connector above.

[0022] The memory structure 100 may include a first well region 104 disposed 1 The first additional conductive region 114 1 ( Figure 1D ) and arranged in the third well region 104 3 The second additional conductive region 114 within 2 ( Figure 1C ). For example, each additional conductive region 114 1 , 114 2 may include along the corresponding well region 104 1 , 104 3 The side surface 104 1 s, 104 3 s arrangement, wherein these side surfaces 104 1 s, 104 3 s may be away from the second well region 104 2 Additional conductive area 114 1 , 114 2 One or more dopants may be included and may have a first conductivity type. The first and second additional conductive regions 114 1 , 114 2 The doping concentration of each of the well regions 104 may be approximately equal and may be higher than that of the first and third well regions 104. 1 , 104 3 For example, the first and second additional conductive regions 114 1 , 114 2 The doping concentration of each of the 19 / cm 3 About 1×10 20 / cm3 Between. Figure 1C and 1D As shown, the silicide layer 116 1 , 116 2 can be arranged in the corresponding well region 104 1 , 104 3 The first and second additional conductive regions 114 within 1 , 114 2 Similarly, although Figure 1C and 1D Each silicide layer 116 1 , 116 2 Depicted with corresponding additional conductive regions 114 1 , 114 2 completely overlapped, but each silicide layer 116 1 , 116 2 may alternatively be connected with a corresponding additional conductive region 114 1 , 114 2 Each silicide layer 116 1 , 116 2 The silicide material may include, for example, but not limited to, cobalt silicide, nickel silicide, titanium silicide, tantalum silicide, or a combination thereof. 5 and the seventh well region 104 7 Similar additional conductive regions are arranged within the PCB, and a silicide layer may also be arranged over each of these additional conductive regions.

[0023] refer to Figure 1A The memory structure 100 may include a first group of well regions 104 respectively arranged 1 , 104 3 , 104 5 , 104 7 The first to fourth control gate connectors 118 above 1 -118 4 . Control grid connector 118 1 -118 4 Each may include a conductive material such as, but not limited to, aluminum, copper, tungsten, alloys thereof, or combinations thereof. Control gate connector 118 1 -118 4 Each of the above can be connected to the connector 118 1 -118 4 The corresponding well region 104 1 , 104 3 , 104 5 , 104 7 For example, the first control gate connector 1181 The first additional conductive region 114 may be arranged 1 and the second control gate connector 1182 may be arranged on the second additional conductive region 114 2 Each control gate connector 118 1 -118 4 Can be configured to electrically couple the additional conductive region to an external voltage.

[0024] like Figure 1A As shown, the memory structure 100 may further include a well region 104 disposed above the substrate 102 (eg, 1 -104 7 A plurality of gate structures (including first to twelfth gate structures 120) 1 , 120 2 , 120 3 , 120 4 , 120 5 , 120 6 , 120 7 , 120 8 , 120 9 , 120 10 , 120 11 , 120 12 ). For example, the first gate structure 120 1 The second well region 104 may be arranged 2 above and in the third well region 104 3 The second gate structure 120 extends upward; 2 The second well region 104 may be arranged 2 above and may be in the first well region 104 1 The first gate structure 120 extends upward. 1 and the second gate structure 120 2 The second well region 104 may be 2 The upper portions are arranged laterally adjacent to each other along the second direction Y.

[0025] refer to Figure 1B , the first gate structure 120 1 The first conductive region 108 may be arranged laterally 1 and the second conductive region 108 2 Between these areas 108 1 , 108 2 The second well region 104 between 2 The first gate structure 120 is above a portion of 1 The conductive area 108 may 1 , 108 2Similarly, the second gate structure 120 2 The second conductive region 108 may be arranged laterally 2 and the third conductive region 108 3 Between these areas 108 2 , 108 3 The second well region 104 between 2 The second gate structure 120 2 It can also be connected with the conductive area 108 2 , 108 3 Each of the overlaps vertically.

[0026] Furthermore, if Figure 1C As shown, the first gate structure 120 1 The third well region 104 may be 3 The third well region 104 extends upwardly 2 The second additional conductive region 114 within 2 The first gate structure 120 may be at least partially disposed 1 Below. Similarly, Figure 1D As shown, the second gate structure 120 2 The first well region 104 may be 1 The first well region 104 extends upwardly, so that 1 The first additional conductive region 114 1 The second gate structure 120 may be at least partially disposed 2 Herein, “a region is at least partially disposed below a structure” means that at least 1% of the area of ​​the top surface of the region can be disposed below the structure. 1 The first isolation element 106 may be partially arranged 1 and the second gate structure 120 2 The second isolation element 106 may be partially arranged 2 The first and second gate structures 120 1 , 120 2 The first and second isolation elements 106 can be used to 1 , 106 2 The first and third well regions 104 1 , 104 3 Electrical isolation.

[0027] like Figure 1B-1D As shown, the first and second gate structures 120 1 , 120 2 Each of the gate electrodes 120 may include 1 a. 120 2a and located at the gate electrode 120 1 a. 120 2 a The gate dielectric layer 120 below 1 b. 120 2 b. Each gate electrode 120 1 a. 120 2 a may include a gate electrode material, such as but not limited to polysilicon; and each gate dielectric layer 120 1 b. 120 2 b may include a dielectric material, such as but not limited to an oxide material, such as silicon oxide. The third to twelfth gate structures 120 3 -120 12 Each of may also include similar Figure 1B-1D The gate electrode and gate dielectric layer are shown.

[0028] The memory structure 100 may also include a bit line connector 112 connected to the 1 -112 9 The plurality of bit lines (BL) 1202, 1204, 1206 and the control gate connector 118 are connected to the 1 -118 4 A plurality of control gate lines (CGL) 1208, 1210, 1212, 1214. For example, Figure 1A As shown, the bit line connectors 112 along the same row 1 , 112 4 , 112 7 / 112 2 , 112 5 , 112 8 / 112 3 , 112 6 , 112 9 can be connected to the same BL 1202 / 1204 / 1206; and each control gate connector 118 1 / 118 2 / 118 3 / 118 4 The BLs 1202, 1204, 1206 may be electrically coupled to the well region 104 of the second conductivity type. 2 , 104 4 , 104 6 ; and CGL 1208, 1210, 1212, 1214 can be electrically coupled to the well region 104 of the first conductivity type 1 , 104 3 , 104 5 , 104 7BLs 1202 and 1206 may be top BLs disposed above substrate 102, and BL 1204 may be bottom BLs disposed below substrate 102. For clarity of illustration, BLs 1202-1206 and CGLs 1208-1214 are not shown in FIG. Figure 1B-1D Shown in.

[0029] like Figure 1A As shown, the memory structure 100 can be considered to include a plurality of memory devices / memory cells (e.g., first, second, third, fourth, fifth and sixth memory devices / memory cells 100a, 100b, 100c, 100d, 100e, 100f), wherein each memory device 100a-100f can be a two-transistor two-capacitor (2T2C) memory device. It should be noted that although the memory structure 100 is Figure 1A 100a-100f, but it should be understood that the memory structure 100 may include fewer (eg, one) or more memory devices, and the well region 104 1 -104 7 and gate structure 120 1 -120 12 The number can vary accordingly.

[0030] The memory devices 100a-100f may be similar to each other and may be arranged laterally adjacent to each other in a matrix. Each memory device 100a-100f may include three well regions 104. 1 -104 3 / 104 3 -104 5 / 104 5 -104 7 and two gate structures 120 1 , 120 2 / 120 3 , 120 4 / 120 5 , 120 6 / 120 7 , 120 8 / 120 9 , 120 10 / 120 11 , 120 12 For example, Figure 1A As shown, the first memory device 100a may include first, second and third well regions 104. 1 , 104 2 , 104 3 and first and second gate structures 120 1 , 120 2The second memory device 100b may include third, fourth and fifth well regions 104 3 , 104 4 , 104 5 and the third and fourth gate structures 120 3 , 120 4 The third and fourth gate structures 120 3 , 120 4 With respect to the well region 104 3 , 104 4 , 104 5 The arrangement may be similar to the first and second gate structures 120 1 , 120 2 With respect to the well region 104 1 , 104 2 , 104 3 For example, the third gate structure 120 3 can be arranged in the fourth well region 104 4 above and in the fifth well region 104 5 The fourth gate structure 120 extends upward; 4 can be arranged in the fourth well region 104 4 above and in the third well region 104 3 The third and fourth gate structures 120 3 , 120 4 With respect to the well region 104 3 , 104 4 , 104 5 The arrangement of the isolation elements, conductive regions, and additional conductive regions within the gate structure 120 may also be similar to the above arrangement for the first and second gate structures 120. 1 , 120 2 Arrangement as described.

[0031] like Figure 1A As shown, adjacent memory devices 100a, 100b / 100b, 100c in the same row may share a common well region 104. 3 , 104 5 For example, the first memory device 100a and the second memory device 100b in the same row may share the third well region 104. 3 The first gate structure 120 (of the first memory device 100a) 1 and the fourth gate structure 120 (of the second memory device 100b) 4 The third well region 104 may be 3The memory devices 100a, 100d / 100b, 100e / 100c, 100f in the same column may share the same well region 104. 1 -104 3 / 104 3 -104 5 / 104 5 -104 7 , and can also share the bit line connector 112 2 , 112 5 , 112 8 One of the bit line connectors (eg, 112 2 ) below the conductive area (e.g. 108 3 ). For example, Figure 1A As shown, the first memory device 100a and the fourth memory device 100d in the same column may share the first, second and third well regions 104. 1 , 104 2 , 104 3 , bit line connector 112 2 and conductive region 108 3 .like Figure 1A As shown, the fifth and sixth gate structures 120 (of the fourth memory device 100d) 5 , 120 6 The second well region 104 may be arranged 2 The first and second gate structures 120 (of the first memory device 100a) are 1 , 120 2 and the fifth and sixth gate structures 120 (of the fourth memory device 100d) 5 , 120 6 The second well region 104 may be 2 The upper portions are arranged laterally adjacent to each other along the second direction Y.

[0032] Each memory device 100a-100f of the memory structure 100 may be considered as a two-bit / dual-bit device, where the first bit (bit 1) may correspond to its gate structure 120. 1 -120 12 The state of one of the bits, and the second bit (bit 2) may correspond to its gate structure 120 1 -120 12 For example, the first bit (bit 1) of the first memory device 100a may correspond to the first gate structure 120. 1 The second bit (bit 2) of the first memory device 100a may correspond to the second gate structure 120 2 status.

[0033] In order to perform an operation on a selected memory device 100a-100f, a well region 104 of the memory device 100a-100f may be connected to the well region 104 of the memory device 100a-100f. 1 -104 7 Appropriate voltages are applied to the electrically coupled BLs 1202-1206 and CGLs 1208-1214. For example, the voltages may be applied to the electrically coupled second well region 104. 2 The top BL 1202 and the bottom BL 1204 are electrically coupled to the first well region 104. 1 CGL1208, and electrically coupled to the third well region 104 3 The CGL 1210 of the memory device 100a is applied with appropriate voltages to perform operations on the first memory device 100a. The CGL 1208 and the CGL 1210 may be referred to as the first selected CGL (selected CGL1) and the second selected CGL (selected CGL2) of the memory device 100a, respectively; and the BL 1202 may be referred to as the selected top BL of the memory device 100a. The remaining top BL 1206 and CGLs 1212 and 1214 may be referred to as unselected top BLs and unselected CGLs, respectively.

[0034] Table 1 below shows voltages that may be applied to a selected BL (e.g., 1202 for the first memory device 100a), a bottom BL 1204, and a selected CGL (e.g., 1208, 1210 for the first memory device 100a) to perform various operations on a selected memory device (e.g., the first memory device 100a) in a non-limiting embodiment.

[0035]

[0036] Table 1

[0037] As shown in Table 1, to program the first bit (PGM (bit 1)) of the first memory device 100a, a voltage ranging from 2.5V to 5V may be applied to the selected CGL1 1208, a voltage of 9V may be applied to the selected CGL2 1210, and a voltage connected to the first bit line connector 112 may be applied to the selected CGL2 1210. 1 The selected top BL 1202 applies a voltage of 9V and can be connected to the second bit line connector 112 2 A voltage ranging from 2V to 4V is applied to the bottom BL 1204 of the selected bit line. The unselected CGLs 1212, 1214 and BL 1206, and SUB (substrate 102) can be grounded. Due to the voltage difference between the selected top BL 1202 and the bottom BL 1204, electrons can be sent from the second bit line connector 112. 2The third conductive region 108 below 3 Flows to the second conductive region 108 2 , can then be implanted into the first gate structure 120 1 This can therefore program the first bit (bit 1) of the first memory device 100a.

[0038] To program the second bit of the first memory device 100a (PGM (bit 2)), a voltage of 9V may be applied to the selected CGL1 1208, a voltage ranging from 2.5V to 5V may be applied to the selected CGL2 1210, a voltage of 2V to 4V may be applied to the selected top BL 1202, and a voltage of 9V may be applied to the bottom BL 1204. The unselected CGLs 1212, 1214 and BL 1206, and the SUB (substrate 102) may be grounded. Due to the voltage difference between the selected top BL 1202 and the bottom BL 1204, electrons may be transferred from the first bit line connector 112 to the bottom BL 1204. 1 The first conductive region 108 below 1 Flows to the second conductive region 108 2 , can then be implanted into the second gate structure 120 2 This can therefore program the second bit (bit 2) of the first memory device 100a.

[0039] To erase the memory device 100a, a voltage of 9V may be applied to the selected top BL 1202 and bottom BL 1204. The CGLs 1208, 1210, 1212, 1214, the unselected BLs 1206, and the SUB (substrate 102) may be grounded. Due to the voltage difference between the BLs 1202, 1204 and the CGLs 1208, 1210, the first and second well regions 104 may be grounded. 1 , 104 2 A first electric field is formed between the second and third well regions 104. 2 , 104 3 A second electric field is formed between the first and second gate structures. These electric fields can induce hot electron / hole pairs (forming gate induced leakage current (GIDL)). Hot holes can be injected into the first and second gate structures 120 1 , 120 2 In order to neutralize these gate structures 120 1 , 120 2 Therefore, the first and second bits can be erased.

[0040] To read the memory device 100a, a voltage of 2.5V may be applied to each of the selected CGL1 1208 and the selected CGL2 1210, and a voltage of 1V may be applied to the selected top BL 1202. The bottom BL 1204, the unselected CGLs 1212, 1214, and BL 1206, and the SUB (substrate 102) may be grounded. Due to the voltage difference between the selected top BL 1202 and the bottom BL 1204, current may flow through the first conductive region 108. 1 The third conductive region 108 3 The magnitude of the current may depend on the states of the first and second bits of the memory device 100a (or in other words, on the first and second gate structures 120). 1 , 120 2 For example, if both the first and second bits are programmed (in other words, electrons are present in the first and second gate structures 120 1 , 120 2 In both cases), the gate structure 120 1 , 120 2 The lower channel region may be turned off, so no or only minimal current (I1) flows through the memory device 100a. On the other hand, if both the first and second bits are erased (in other words, the first and second gate structures 120 1 , 120 2 There are no electrons in the gate structure 120. 1 , 120 2 The channel region below can be turned on, so a larger current (I2) can flow through the memory device 100a. If only one of the bits is programmed, the channel region below the gate structure with electrons can be turned off, and the channel region below the other gate structure without electrons can be turned on. Therefore, a current (I3) between I1 and I2 can flow through the memory device 100a. The size of the current (I3) may vary depending on which of the first and second bits is programmed.

[0041] By applying appropriate voltages to the BL 1202-1206 and CGL 1208-1214, similar operations as described above may be performed on each of the other memory devices 100b-100f. It should be noted that in alternative non-limiting embodiments, the voltages applied to the BL 1202-1206 and CGL 1208-1214 to perform various operations on the memory devices 100a-100f may be different than those shown in Table 1.

[0042] Figure 2 A flow chart illustrating a method of forming the memory structure 100 is shown, according to various non-limiting embodiments.

[0043] At 202 , the method may include providing a substrate 102 .

[0044] At 204, the method may include forming an isolation element (eg, 106) within the substrate 102. 1 , 106 2 ). Isolation element (e.g. 106 1 , 106) can be formed by etching the substrate 102 to form openings and depositing isolation materials in these openings.

[0045] At 206 , the method may include forming a well region 104 within the substrate 102 1 -104 7 Well region 104 1 -104 7 By placing an isolation element (e.g. 106 1 , 106) by doping the substrate 102 with appropriate dopants.

[0046] At 208 , the method may include forming a 1 -104 7 A gate structure 120 is formed on the top 1 -120 12 To form an intermediate structure. Gate structure 120 1 -120 12 The gate electrode material may be formed by depositing an oxide material over the substrate 102 , depositing a gate electrode material over the oxide material, and etching the oxide material and the gate electrode material.

[0047] At 210 , the method may include forming a plurality of layers in the well region 104 . 1 -104 7 A conductive region (eg, 108 1 -108 3 ) and additional conductive areas (eg 114 1 , 114 2 These areas (such as 108 1 -108 3 , 114 1 , 114 2 ) may be formed by implanting a dopant of the first conductivity type into the intermediate structure formed at 208. During this process, some dopants may be implanted into the gate structure 120 1 -120 12 The remaining dopants may be implanted into the substrate 102 to form a conductive region (eg, 108 1 -108 3 ) and additional conductive areas (eg 114 1, 114 2 ). Therefore, these areas (such as 108 1 -108 3 , 114 1 , 114 2 ) may be only along the exposed areas of the substrate 102 (in other words, not in the gate structure 120 1 -120 12 However, due to the diffusion of dopants in the substrate 102, the conductive region (e.g., 108 1 -108 3 ) and additional conductive area (114 1 , 114 2 A small portion of each of the gate structures 120 may be arranged on the corresponding gate structure 120 1 -120 12 Below.

[0048] At 212, the method may include providing a conductive region (eg, 108 1 -108 3 ) and additional conductive areas (eg 114 1 , 114 2 ) is formed on the silicide layer (eg, 110 1 -110 3 , 116 1 , 116 2 These silicide layers (e.g. 110 1 -110 3 , 116 1 , 116 2 ) can be formed by implanting a silicide material into the substrate 102.

[0049] At 214 , the method may include forming a plurality of layers in the well region 104 . 1 -104 7 A bit line connector 112 is formed on the top 1 -112 9 and control grid connector 118 1 -118 4 .

[0050] At 216, the method may include forming the bit lines 1202-1206 and the control gate lines 1208-1214 to connect to the corresponding bit line connectors 112 1 -112 9 and control grid connector 118 1 -118 4 .

[0051] The order of the above method is intended to be exemplary only, and unless otherwise specifically stated, the method is not limited to the order specifically described above.

[0052] By forming the well region 104 in the above manner 1 -104 7 The gate structure 120 is arranged on the top 1 -120 12 , each gate structure 120 1 -120 12 can be used as a selection transistor and a storage transistor of the memory devices 100a-100f. Therefore, each memory device 100a-100f of the memory structure 100 can be a 2T2C memory device and can have a more compact cell size than a typical 2T2C memory device. For example, referring to Figure 1A , the length L100 of each memory device 100a-100f may be between about 1um and about 1.5um, and the width W100 of each memory device 100a-100f may be between about 1.5um and about 2um. In a non-limiting embodiment, the length L100 may be about 1.29um and the width W100 may be about 1.57um. Therefore, the size of each memory device 100a-100f may be about 2.03um 2 Since each memory device 100a-100f may be a dual-bit device, the 1-bit cell size of each memory device 100a-100f may be approximately 1.01 um. 2 .

[0053] In addition, the well regions 104 between the plurality of memory devices 100a-100f within the memory structure 100 1 -104 7 , bit line connector 112 2 , 112 5 , 112 8 and conductive areas (eg 108 3 ) can allow the memory structure 100 to include a greater number of memory devices 100a-100f. Therefore, the cell density of the memory structure 100 can be higher than a typical memory structure including 2T2C memory devices.

[0054] In addition, by including a floating junction region (eg, second conductive region 108) in each memory device 100a-100f, 2 ), the breakdown voltage (BVDSS) of each memory device 100a-100f with a drain-to-source short circuit may be increased by the gate structure 120 1 -120 12 Therefore, the gate structure 120 can be reduced.1 -120 12 to further reduce the size of the memory structure 100.

[0055] The present invention may be embodied in other specific forms without departing from the spirit or essential characteristics of the present invention. Therefore, the foregoing embodiments are considered in all respects to be illustrative rather than limiting the invention described herein. Therefore, the scope of the present invention is indicated by the appended claims rather than by the foregoing description, and all changes falling within the meaning and scope of the equivalents of the claims are intended to be included therein.

Claims

1. A memory structure comprising: substrate; a first well region, a second well region, and a third well region arranged in the substrate, wherein the first well region and the third well region have a first conductivity type, the second well region has a second conductivity type different from the first conductivity type, and wherein the second well region is laterally arranged between the first well region and the third well region, wherein the first well region, the second well region, and the third well region are arranged laterally adjacent to each other along a first direction; a first gate structure disposed above the second well region, wherein the first gate structure extends above the third well region; a second gate structure disposed over the second well region, wherein the second gate structure extends over the first well region, wherein the first gate structure and the second gate structure are disposed laterally adjacent to each other over the second well region along a second direction substantially perpendicular to the first direction; as well as a first conductive region, a second conductive region, and a third conductive region arranged laterally adjacent to each other along the second direction in the second well region, wherein the second conductive region is arranged between the first conductive region and the third conductive region; and The first gate structure is laterally arranged between the first conductive region and the second conductive region, and the second gate structure is laterally arranged between the second conductive region and the third conductive region. 2 . The memory structure of claim 1 , wherein the first conductive region, the second conductive region, and the third conductive region have the first conductivity type. 3 . The memory structure of claim 1 , wherein a doping concentration of each of the first conductive region, the second conductive region, and the third conductive region is higher than a doping concentration of the second well region.

4. The memory structure according to claim 1, further comprising: a first connector disposed above and electrically coupled to the first conductive region; as well as A second connector is disposed over and electrically coupled to the third conductive region. 5 . The memory structure of claim 1 , further comprising a first additional conductive region disposed within the first well region and at least partially beneath the second gate structure. 6 . The memory structure of claim 5 , wherein the first additional conductive region has the first conductivity type, and a doping concentration of the first additional conductive region is higher than a doping concentration of the first well region. 7 . The memory structure of claim 5 , further comprising a second additional conductive region disposed within the third well region and at least partially beneath the first gate structure.

8. The memory structure according to claim 1, further comprising: a first isolation element disposed between the first well region and the second well region; as well as A second isolation element is disposed between the second well region and the third well region.

9. The memory structure of claim 8, wherein the first gate structure is disposed partially over the first isolation element.

10. The memory structure of claim 8, wherein the second gate structure is disposed partially over the second isolation element.

11. The memory structure according to claim 1 , further comprising: a fourth well region and a fifth well region disposed in the substrate, wherein the fifth well region has the first conductivity type, the fourth well region has the second conductivity type, and wherein the fourth well region is laterally disposed between the third well region and the fifth well region; a third gate structure disposed above the fourth well region, wherein the third gate structure extends above the fifth well region; as well as A fourth gate structure is disposed above the fourth well region, wherein the fourth gate structure extends above the third well region.

12. The memory structure of claim 11, wherein the first well region, the second well region, and the third well region are arranged laterally adjacent to each other along a first direction; and The first gate structure and the fourth gate structure are arranged laterally adjacent to each other above the third well region along a second direction substantially perpendicular to the first direction.

13. The memory structure according to claim 12 further includes a fifth gate structure and a sixth gate structure arranged above the second well region, wherein the first gate structure, the second gate structure, the fifth gate structure and the sixth gate structure are arranged laterally adjacent to each other along the second direction above the second well region.

14. The memory structure of claim 1, wherein the memory structure is a non-volatile memory structure.

15. A method of forming a memory structure, the method comprising: providing a substrate; forming a first well region, a second well region, and a third well region in the substrate, wherein the first well region and the third well region have a first conductivity type, the second well region has a second conductivity type different from the first conductivity type, and wherein the second well region is laterally arranged between the first well region and the third well region, wherein the first well region, the second well region, and the third well region are laterally arranged adjacent to each other along a first direction; forming a first gate structure over the second well region, wherein the first gate structure extends over the third well region; forming a second gate structure over the second well region, wherein the second gate structure extends over the first well region, wherein the first gate structure and the second gate structure are arranged laterally adjacent to each other over the second well region along a second direction substantially perpendicular to the first direction; as well as forming a first conductive region, a second conductive region, and a third conductive region that are laterally arranged adjacent to each other along the second direction in the second well region, wherein the second conductive region is arranged between the first conductive region and the third conductive region; and The first gate structure is laterally arranged between the first conductive region and the second conductive region, and the second gate structure is laterally arranged between the second conductive region and the third conductive region.

16. The method of claim 15, wherein the first conductive region, the second conductive region, and the third conductive region have the first conductivity type; and The doping concentration of each of the first conductive region, the second conductive region and the third conductive region is higher than the doping concentration of the second well region.

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