Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method of forming the same. The method includes providing a substrate including a first region and a second region adjacent to each other and a separation region between the first region and the second region, and a dielectric layer on the substrate; forming an initial separation film on the separation region; after forming the initial separation film, forming a gate opening in the dielectric layer, and the gate opening crossing the first region, the separation region and the second region; forming an initial first work function layer in the gate opening and on the first region, and an initial second work function layer in the gate opening and on the second region, respectively. The semiconductor structure formed by the method has better performance.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] With the development of integrated circuit manufacturing technology, the integration of integrated circuits is increasing, and the feature size of integrated circuits is also decreasing. And with the development of semiconductor devices to high density and small size, metal oxide semiconductor (MOS) becomes the main driving force in integrated circuits, and the performance of MOS transistors directly affects the overall performance of integrated circuits, and among the various parameters of the MOS structure, the threshold voltage (Vt) is an important control parameter of the MOS transistor.

[0003] In order to adjust the threshold voltage of the transistor, the semiconductor technology introduces a work function layer between the gate dielectric layer and the gate electrode in the process of forming the transistor, which can adjust the work function of the transistor and thus adjust the threshold voltage of the transistor. In the prior art, different threshold voltages are required for different MOS transistors.

[0004] However, the performance of the semiconductor structure formed by the existing method is poor. SUMMARY

[0005] The technical problem solved by the present application is to provide a semiconductor structure and a forming method thereof to improve the performance of the formed semiconductor structure.

[0006] To solve the above technical problems, the technical scheme of the present application provides a semiconductor structure, comprising: a substrate, the substrate comprising adjacent first and second regions and an isolation region between the first and second regions, the substrate having a dielectric layer thereon, the dielectric layer having a gate opening therein, and the gate opening spanning the first region, the isolation region and the second region; a first isolation layer located in the gate opening and on the isolation region; a first work function layer located in the gate opening and on the first region, and a second work function layer located in the gate opening and on the second region.

[0007] Optionally, the material of the first isolation layer comprises amorphous silicon, polycrystalline silicon, amorphous germanium or polycrystalline germanium, and is doped with boron ions, phosphorus ions, gallium ions or arsenic ions.

[0008] Optionally, the material of the first isolation layer comprises a dielectric material, and the dielectric material comprises a combination of one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride and silicon carbon oxynitride.

[0009] Optionally, the first isolation layer has a size ranging from 4nm to 15nm in a direction perpendicular to the sidewall surface of the first isolation layer.

[0010] Optionally, the semiconductor structure further comprises a gate dielectric layer located in the gate opening and on the first region and the second region, and a gate layer located on the surface of the first work function layer and the second work function layer.

[0011] Optionally, the sidewall of the first isolation layer comprises opposite first sidewall and second sidewall, and the gate dielectric layer is further located on the surface of the first sidewall and the second sidewall.

[0012] Optionally, the first work function layer is further located on the surface of the gate dielectric layer on the first sidewall, the second work function layer is further located on the surface of the gate dielectric layer on the second sidewall, and the top surface of the first work function layer on the first sidewall is flush with the top surface of the second work function layer on the second sidewall.

[0013] Optionally, the substrate comprises a substrate and a plurality of mutually separated fins and a second isolation layer located on the surface of the substrate, the fins extend in a first direction, and the second isolation layer covers part of the sidewall surface of the fins; the gate opening extends in a second direction, and the first direction is perpendicular to the second direction.

[0014] Optionally, the substrate comprises a substrate and a plurality of nanostructures and a second isolation layer located on the surface of the substrate, the nanostructure comprises a plurality of mutually separated nanowires stacked along the normal direction of the surface of the substrate, the nanostructure extends in a first direction, and the second isolation layer covers the sidewall surface of the bottommost nanowire; the gate opening extends in a second direction, and the first direction is perpendicular to the second direction.

[0015] Correspondingly, the present application also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprises adjacent first region and second region and an isolation region between the first region and the second region, and the substrate has a dielectric layer thereon; forming an initial isolation film on the isolation region; after forming the initial isolation film, forming a gate opening in the dielectric layer, and the gate opening spans the first region, the isolation region and the second region; forming an initial first work function layer on the first region and an initial second work function layer on the second region in the gate opening.

[0016] Optionally, the method further comprises: forming an initial dummy gate layer on the isolation region, the first region and the second region before forming the initial isolation film, and the dielectric layer exposes a top surface of the initial dummy gate layer; forming a dummy gate layer during forming the initial isolation film; and the forming method of the initial isolation film and the dummy gate layer comprises: performing ion implantation on the initial dummy gate layer on the isolation region to form the initial isolation film on the isolation region and the dummy gate layer on the first region and the second region; and removing the dummy gate layer on the first region and the second region to form the gate opening in the dielectric layer.

[0017] Optionally, the ion implantation method comprises: forming a first mask layer on the initial dummy gate layer and the dielectric layer, and the first mask layer exposes the initial dummy gate layer on the isolation region; and performing ion implantation on the initial dummy gate layer with the first mask layer as a mask.

[0018] Optionally, the etching selectivity ratio of the process for removing the dummy gate layer to the dummy gate layer and the initial isolation film ranges from 20:1 to 5:1; and the process parameters for removing the dummy gate layer comprise: the etching solution is a mixed solution of two or more than two of ammonia, tetramethylammonium hydroxide solution and hydrogen peroxide.

[0019] Optionally, the ion implantation process parameters comprise: the implanted ions comprise boron ions, phosphorus ions, gallium ions or arsenic ions, the implanted dose ranges from 1.0E14 atom / cm 3 to 1.0E20 atom / cm 3 , and the implanted energy ranges from 10KeV to 200KeV.

[0020] Optionally, the dielectric layer is formed after forming the initial dummy gate layer; and the forming method of the dielectric layer comprises: forming a dielectric material film on the substrate and the surface of the initial dummy gate layer; and planarizing the dielectric material film until the top surface of the initial dummy gate layer is exposed to form the dielectric layer on the substrate.

[0021] Optionally, further comprising: forming an initial gate dielectric layer on the surface of the first region, the surface of the second region, the surface of the initial isolation film exposed, and the surface of the dielectric layer after forming the gate opening and before forming the initial first work function layer and the initial second work function layer; forming an initial gate layer on the surface of the initial first work function layer and the initial second work function layer after forming the initial first work function layer and the initial second work function layer, and the initial gate layer fills the gate opening; planarizing the initial gate dielectric layer, the initial first work function layer, the initial second work function layer, the dielectric layer, and the initial gate layer until the second initial work function layer on the first region is removed, so that the initial gate dielectric layer forms the gate dielectric layer, the initial first work function layer forms the first work function layer, the initial second work function layer forms the second work function layer, the initial gate layer forms the gate layer, the first gate structure is formed on the first region, and the second gate structure is formed on the second region.

[0022] Optionally, the first work function layer and the second work function layer are of different conductive types, the conductive type of the first work function layer is P-type or N-type, and the conductive type of the second work function layer is P-type or N-type; the P-type work function material includes one or more of Ta, TiN, TaN, TaSiN, or TiSiN; and the N-type work function material includes one or more of TiAl, TiAlC, TaAlN, TiAlN, TaCN, and AlN.

[0023] Optionally, the initial second work function layer is formed after the initial first work function layer is formed.

[0024] Optionally, the method for forming the initial first work function layer includes: forming a first work function material film on the surface of the initial gate dielectric layer and the surface of the dielectric layer; forming a first sacrificial layer on the surface of the first work function material film, and the first sacrificial layer fills the gate opening; forming a second mask layer on the surface of the first sacrificial layer, and the second mask layer exposes the surface of the first sacrificial layer on the second region; etching the first sacrificial layer and the first work function material film with the second mask layer as a mask until the surface of the initial gate dielectric layer on the second region is exposed, so that the first work function material film forms the initial first work function layer; and removing the second mask layer and the first sacrificial layer after the initial first work function layer is formed.

[0025] Optionally, after the second mask layer and the first sacrificial layer are removed, the initial second work function layer is formed; the forming method of the initial second work function layer comprises: forming a second work function material film on the surface of the initial first work function layer in the first region and the surface of the initial gate dielectric layer and the surface of the dielectric layer in the second region; forming a second sacrificial layer on the surface of the second work function material film, and the second sacrificial layer fills the gate opening; forming a third mask layer on the surface of the second sacrificial layer, and the third mask layer exposes the surface of the second sacrificial layer in the first region; taking the third mask layer as a mask, etching the second sacrificial layer and the second work function material film until the surface of the initial first work function layer in the first region is exposed, so that the second work function material film forms the initial second work function layer; after the initial second work function layer is formed, the second sacrificial layer is removed.

[0026] Optionally, after the initial first work function layer is formed, before the first sacrificial layer is removed, the initial second work function layer is formed; the forming method of the initial second work function layer comprises: forming a second work function material film on the surface of the first sacrificial layer in the first region and the surface of the initial gate dielectric layer and the surface of the dielectric layer in the second region; removing the first sacrificial layer and the second work function material film located on the surface of the first sacrificial layer, so that the second work function material film forms the initial second work function layer.

[0027] Optionally, the sidewall of the initial isolation film comprises a first sidewall and a second sidewall; the initial first work function layer is also located on part of the surface of the first sidewall, and the initial second work function layer is also located on the top surface of the initial isolation film and the surface of the second sidewall and part of the surface of the first sidewall; the planarization process also makes the initial isolation film form a first isolation film until the second initial work function layer located in the first region is removed.

[0028] Optionally, it further comprises: removing the first isolation film to form an isolation opening in the isolation region; forming a first isolation layer in the isolation opening, and the material of the first isolation layer is a dielectric material.

[0029] Optionally, the material of the first isolation layer comprises: one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride and silicon carbon oxynitride.

[0030] Optionally, it further comprises: after the gate opening is formed and before the initial first work function layer and the initial second work function layer are formed, the initial isolation film is subjected to a modification treatment to reduce the size of the initial isolation film in the direction perpendicular to the sidewall of the initial isolation film.

[0031] Optionally, the modification treatment comprises isotropic etching or anisotropic etching.

[0032] Optionally, the modification treatment is an isotropic etching process, and parameters of the isotropic etching process include: a main etching gas used including NH3, H2 and NF3, a secondary etching gas used including Ar or He, a pressure of 2 Torr to 10 Torr, and a source power range of 10 W to 200 W.

[0033] Optionally, after the modification treatment, the initial isolation film has a size range of 4 nm to 15 nm.

[0034] Optionally, the substrate includes a substrate and a plurality of mutually separated fins and a second isolation layer located on a surface of the substrate, the fins extend along a first direction, and the second isolation layer covers part of a sidewall surface of the fins; the gate opening extends along a second direction, and the first direction is perpendicular to the second direction.

[0035] Optionally, the substrate includes a substrate and a plurality of nanostructures and a second isolation layer located on a surface of the substrate, the nanostructure includes a plurality of mutually separated nanowires stacked along a normal direction of the surface of the substrate, the nanostructure extends along a first direction, and the second isolation layer covers a sidewall surface of a bottom layer of the nanowires; the gate opening extends along a second direction, and the first direction is perpendicular to the second direction.

[0036] Compared with the prior art, the technical scheme of the present application has the following beneficial effects:

[0037] In the semiconductor structure provided by the technical scheme, the first isolation layer located on the isolation region can isolate the first work function layer on the first region and the second work function layer on the second region. Since the position of the first isolation layer is accurate, the first work function layer formed on the first region and the second work function layer formed on the second region can be accurately isolated. Moreover, the first work function layer affects the threshold voltage of the device on the first region, and the second work function layer affects the threshold voltage of the device on the second region. The accurate position of the initial isolation film is conducive to isolating the devices on the first region and the second region, respectively, so that the threshold voltage of the device on the first region and the threshold voltage of the device on the second region meet the process requirements.

[0038] The forming method of the semiconductor structure provided by the technical scheme comprises the following steps: forming an initial isolation film on the isolation region; forming a first work function layer on the first region and a second work function layer on the second region; and performing ion implantation on the initial pseudo gate layer on the isolation region to form the initial isolation film.

[0039] Further, the initial isolation film is formed by performing ion implantation on the initial pseudo gate layer on the isolation region, and the position and size of the initial isolation film are determined by the position and size of the first mask layer, so that the position and size of the initial isolation film can be better controlled, and the initial isolation film can better isolate the first work function layer and the second work function layer formed subsequently, and the threshold voltage of the device on the first region and the threshold voltage of the device on the second region meet the process requirements.

[0040] Further, the forming method of the semiconductor structure further comprises: performing modification treatment on the initial isolation film to reduce the size of the initial isolation film in the direction perpendicular to the sidewall of the initial isolation film, so that the initial isolation film can more accurately isolate the first work function layer and the second work function layer located on both sides of the initial isolation film, and the space for forming the device on the first region and the space for forming the device on the second region can be increased, thereby facilitating the increasing integration requirement.

[0041] Further, when the modification treatment adopts the isotropic etching process, the sidewall of the initial isolation film can be better perpendicular to the surface of the substrate, so that the morphology of the initial isolation film after the modification treatment is better, and the initial isolation film can better isolate the first work function layer and the second work function layer formed subsequently, and the threshold voltage of the device on the first region and the threshold voltage of the device on the second region meet the process requirements.

[0042] Further, the planarization process forms the initial isolation film into a first isolation film, and makes the top surface of the first work function layer located on the first sidewall surface flush with the top surface of the second work function layer located on the second sidewall surface, so that the first work function layer and the second work function layer located on the sidewall surface of the first isolation film have similar influence on the threshold voltage, and the threshold voltage of the device on the first region and the threshold voltage of the device on the second region meet the process requirements. BRIEF DESCRIPTION OF DRAWINGS

[0043] Figures 1 to 6 A schematic diagram of a semiconductor structure in an embodiment of the present application.

[0044] Figures 7 to 19 A schematic diagram of a semiconductor structure in an embodiment of the present application. DETAILED DESCRIPTION

[0045] As described in the background, the performance of the semiconductor structure is poor.

[0046] The reasons for the poor performance of the semiconductor structure are described in detail below with reference to the accompanying drawings, Figure 1 A schematic diagram of a semiconductor structure.

[0047] It should be noted that the terms "surface", "top" in the present specification are used to describe the relative position in space and do not necessarily mean direct contact.

[0048] First, the reasons for the poor performance of the existing semiconductor structure are described in detail with reference to the accompanying drawings, Figures 1 to 6 A schematic diagram of a semiconductor structure in an embodiment of the present application.

[0049] Please refer to Figure 1 and Figure 2 , Figure 1 for Figure 2 A schematic diagram of a cross-section along the AA cutting direction, a substrate is provided, the substrate includes: a substrate 101 and a plurality of mutually separated fin portions 102 and isolation layers 103 on the surface of the substrate 101, and the isolation layers 103 cover part of the side surface of the fin portions 102, the substrate includes adjacent first region I and second region II; A pseudo gate structure 110 is formed on the first region I and the second region II, which spans the fin portions 102, and the pseudo gate structure 110 covers part of the top surface and the side wall surface of the fin portions 102.

[0050] Please refer to Figure 3 , a dielectric layer (not shown in the figure) is formed on the first region I and the second region II, and the dielectric layer is located on the side wall surface of the pseudo gate structure 110; The pseudo gate structure 110 is removed, and a pseudo gate opening 120 is formed in the dielectric layer; The interface layer 131 is formed on the exposed surface of the fin portions 102 in the first region I and the second region II in the pseudo gate opening 120; The gate dielectric film 132 is formed on the surface of the interface layer 131 and the dielectric layer; The first work function material film 133 is formed on the surface of the gate dielectric film 132.

[0051] Please refer to Figure 4A sacrificial layer 140 is formed on the surface of the first work function material film 133, and the sacrificial layer 140 fills the pseudo-gate opening 120; a mask layer 141 is formed on the surface of the sacrificial layer, and the mask layer 141 exposes the surface of the sacrificial layer 140 on the second region II; the sacrificial layer 140 and the first work function material film 133 are etched with the mask layer 141 as a mask until the surface of the gate dielectric film 132 is exposed.

[0052] Please refer to Figure 5 The first work function layer 150 is formed on the first region I after the etching process.

[0053] Please refer to Figure 6 After the formation of the first work function layer 150, the sacrificial layer 140 and the mask layer 141 are removed; and the second work function layer 160 is formed on the surface of the gate dielectric film 132 on the second region II.

[0054] In the above method, the mask layer 141 covers the sacrificial layer 140 on the first region I and exposes the sacrificial layer 140 on the second region II. By etching the first work function material film 133 with the mask layer 141 as a mask, the position of the mask layer 141 determines the position of the first work function layer 150, so that the first work function layer 150 is formed on the surface of the fin 102 on the first region I.

[0055] However, in the process of etching the first work function material film 133 with the mask layer 141 as a mask, on the one hand, the thickness uniformity of the first work function material film 133 is poor, and the corner where the fin 102 and the substrate 101 meet is prone to have residual by-products. When most of the first work function material film on the second region II is removed to expose the surface of the gate dielectric film 132, there are still residual by-products a on the second region II (as shown in Figure 4 At this time, through the over-etching process, the residual by-products on the second region II can be basically removed. At the same time, the sacrificial layer 140 on the first region I and the first work function material film 133 covered by the sacrificial layer 140 are also prone to be over-etched, resulting in that part of the first work function material film 133 on the first region I is removed, so that the first work function layer 150 deviates from the predetermined position, that is, the first work function layer 150 also exposes part of the second region II, and further the threshold voltage of the device on the first region I and the threshold voltage stability of the device on the second region II are poor, which cannot meet the process requirements.

[0056] To solve the technical problem, the embodiment of the present application provides a semiconductor structure and a forming method thereof.

[0057] In order to make the above objects, features and advantages of the present application more obvious and understandable, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0058] Figures 7 to 19 is a structural schematic diagram of each step of the forming method of the semiconductor structure in the embodiment of the present application.

[0059] Please refer to Figure 7 and Figure 8 , Figure 7 for Figure 8 a sectional view along the direction of BB cutting line, Figure 8 is Figure 7 a top view, a substrate is provided, the substrate comprises adjacent first region I and second region II and isolation region III between the first region I and the second region II.

[0060] In the embodiment, the substrate comprises a substrate 201 and a plurality of mutually separated fin portions 202 and a second isolation layer 203 on the surface of the substrate 201, the fin portion 201 extends along the first direction X, and the second isolation layer 203 covers part of the sidewall surface of the fin portion 202.

[0061] In the embodiment, the material of the substrate 201 is silicon; the material of the fin portion 202 is silicon.

[0062] In other embodiments, the material of the substrate comprises silicon carbide, silicon germanium, multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI) or germanium-on-insulator (GOI). Among them, the multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP. The material of the fin portion includes silicon carbide, silicon germanium, multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI) or germanium-on-insulator (GOI). Among them, the multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0063] In other embodiments, the substrate comprises: a substrate and a plurality of nanostructures and a second isolation layer on the substrate surface, the nanostructures comprise a plurality of nanowires stacked along the normal direction of the substrate surface and separated from each other, the nanostructures extend along a first direction, and the second isolation layer covers the sidewall surface of the bottommost nanowire.

[0064] The second isolation layer 203 is used to form electrical isolation between different devices.

[0065] Please continue to refer to Figure 7 and Figure 8 An initial dummy gate layer 210 is formed on the isolation region III, the first region I and the second region II.

[0066] The initial dummy gate layer 210 has two functions: on the one hand, it occupies space for the subsequent formation of a gate structure by a gate-last process; on the other hand, it provides a material layer for forming an initial isolation film on the isolation region II.

[0067] The material of the initial dummy gate layer 210 comprises: amorphous silicon, polycrystalline silicon, amorphous germanium or polycrystalline germanium. In the present embodiment, the material of the initial dummy gate layer 210 is polycrystalline silicon.

[0068] In the present embodiment, the method for forming the semiconductor structure further comprises: forming a dummy gate dielectric layer (not shown in the figure) on the exposed surface of the fin 202.

[0069] The dummy gate dielectric layer is used to protect the surface of the fin 202 from damage by subsequent processes.

[0070] The material of the dummy gate dielectric layer comprises: silicon oxide.

[0071] Please continue to refer to Figure 7 and Figure 8 A dielectric layer 220 is formed on the substrate, and the dielectric layer 220 exposes the top surface of the initial dummy gate layer 210.

[0072] The method for forming the dielectric layer 220 comprises: forming a dielectric material film (not shown in the figure) on the substrate and the surface of the initial dummy gate layer 210; planarizing the dielectric material film until the top surface of the initial dummy gate layer 210 is exposed, thereby forming the dielectric layer 220 on the substrate.

[0073] The material of the dielectric layer 220 comprises a dielectric material, which comprises one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride and silicon carbon oxynitride. In the present embodiment, the material of the dielectric layer 220 comprises silicon oxide.

[0074] Then, an initial isolation film is formed on the isolation region III.

[0075] In this embodiment, the initial isolation film is formed in a process of forming the initial dummy gate layer.

[0076] Please refer to Figure 9 , Figure 9 to form the initial isolation film 230 on the isolation region III and the dummy gate layer 211 on the first region I and the second region II. Figure 7 The ion implantation method comprises: forming a first mask layer 221 on the initial dummy gate layer 210 (as shown in the figure) and the surface of the dielectric layer 220, the first mask layer 221 exposing the initial dummy gate layer 210 on the isolation region III; and implanting ions into the initial dummy gate layer 210 with the first mask layer 221 as a mask.

[0077] Figure 7 Through the ion implantation, the initial dummy gate layer 210 on the isolation region III forms the initial isolation film 230, and the initial dummy gate layer 210 on the first region I and the second region II forms the dummy gate layer 211.

[0078] Specifically, the sidewall of the initial isolation film 230 comprises a first sidewall 2301 and a second sidewall 2302.

[0079] The ion implantation process parameters comprise: the implanted ions comprise boron ions, phosphorus ions, gallium ions or arsenic ions, the implanted dose ranges from 1.0E14 atom / cm 3 to 1.0E20 atom / cm 3 , and the implanted energy ranges from 10 KeV to 200 KeV.

[0080] In this embodiment, the implanted ions are boron ions, and since the material of the initial dummy gate layer 210 is polysilicon, the material of the initial isolation film 230 formed through the ion implantation process is boron-doped polysilicon, so that the material of the initial isolation film 230 is different from that of the dummy gate layer 211, thereby removing the dummy gate layer 211 through a subsequent appropriate etching process.

[0081]

[0082] ​​The initial isolation film 230 is formed by ion implantation on the initial dummy gate layer 210 on the isolation region III. Since the initial isolation film 230 is formed by ion implantation on the initial dummy gate layer 210 with the first mask layer 221 as a mask, the position and size of the initial isolation film 230 are determined by the position and size of the first mask layer 221, so that the position and size of the initial isolation film 230 can be better controlled, and the initial isolation film 230 can better isolate the first work function layer and the second work function layer formed subsequently, so that the device threshold voltage on the first region I and the device threshold voltage on the second region II meet the process requirements.

[0083] Please refer to Figure 10 After the initial isolation film 230 is formed, the gate opening 240 is formed in the dielectric layer 220, and the gate opening 240 spans the first region I, the isolation region III and the second region II.

[0084] Specifically, the gate opening 240 extends along the second direction, and the first direction X is perpendicular to the second direction.

[0085] The forming method of the gate opening 240 includes: removing the dummy gate layer 211 on the first region I and the second region II, and forming the gate opening 240 in the dielectric layer 220.

[0086] The etching selectivity ratio range of the process for removing the dummy gate layer 211 to the initial isolation film 230 is 20:1 to 5:1. The process parameters for removing the dummy gate layer 211 include: the etching solution is two or more than two mixed solutions selected from the group consisting of ammonia, tetramethylammonium hydroxide solution and hydrogen peroxide.

[0087] The process for removing the dummy gate layer 211 can remove the dummy gate layer 211 completely while causing less etching damage to the initial isolation film 230, so that the initial isolation film 230 can better isolate.

[0088] Please refer to Figure 11 After the gate opening 240 is formed, the initial isolation film 230 is modified and processed, and the size of the initial isolation film 230 is reduced along the direction perpendicular to the sidewall of the initial isolation film 230.

[0089] After the gate opening 240 is formed, the sidewall surface of the initial isolation film 230 is exposed, and the first sidewall 2301 and the second sidewall 2302 of the initial isolation film 230 are etched, so that the size of the sidewall on both sides of the initial isolation film 230 is uniformly reduced, that is, the central axis of the initial isolation film 230 does not deviate from the position set according to the requirement, so that the initial isolation film 230 can accurately isolate the first work function layer on the subsequent first region I and the second work function layer on the second region II, and then the threshold voltage of the device on the first region I and the threshold voltage of the device on the second region II meet the process requirement.

[0090] The modification processing includes isotropic etching or anisotropic etching.

[0091] In the embodiment, the modification processing is an isotropic etching process, and parameters of the isotropic etching process include that the main etching gas used includes NH3, H2 and NF3, the auxiliary etching gas used includes Ar or He, the pressure is 2 Torr to 10 Torr, and the source power ranges from 10 W to 200 W.

[0092] When the modification processing uses the isotropic etching process, the sidewall of the initial isolation film 230 can be better perpendicular to the substrate surface, so that the morphology of the initial isolation film 230 after the modification processing is better, and then the initial isolation film 230 can better isolate the first work function layer and the second work function layer formed subsequently, and then the threshold voltage of the device on the first region I and the threshold voltage of the device on the second region II meet the process requirement.

[0093] After the modification processing, the size of the initial isolation film 230 ranges from 4 nm to 15 nm.

[0094] In other embodiments, the initial isolation film can also not be subjected to the modification processing.

[0095] The range is selected in that if the size is less than 4 nm, the size of the initial isolation film 230 is too small, the mechanical support between the initial isolation film 230 and the second isolation layer 203 attached thereto is too small, the initial isolation film 230 is prone to tilt or even collapse, and the performance of the semiconductor structure formed is not good; if the size of the initial isolation film 230 is greater than 15 nm, the space of the initial isolation film 230 is large, which increases the difficulty of filling the material for forming the gate structure subsequently, and the morphology of the film layer formed is not good, so that the performance of the semiconductor structure formed is poor.

[0096] The modification processing is performed on the initial isolation film 230, so that the size of the initial isolation film 230 in the direction perpendicular to the sidewall of the initial isolation film 230 is reduced, and the initial isolation film 230 can more accurately isolate the first work function layer and the second work function layer located on both sides of the initial isolation film 230, and the space for forming the device on the first region I and the space for forming the device on the second region II are increased, so as to meet the requirement of higher integration.

[0097] Please refer to Figure 12 The initial gate dielectric layer 241 is formed on the surface of the first region I, the surface of the second region II, the surface of the initial isolation film 230 exposed after the modification processing, and the surface of the dielectric layer 220.

[0098] In this embodiment, the initial gate dielectric layer 241 is formed after the modification processing.

[0099] In this embodiment, the initial gate dielectric layer 241 is formed after the modification processing.

[0100] The method for forming the semiconductor structure further comprises: forming an interface layer (not shown in the figure) on the surface of the fin 202 before forming the initial gate dielectric layer 241, and the interface layer is located between the fin 202 and the initial gate dielectric layer 241. The interface layer can effectively reduce the interface defects between the fin 202 and the initial gate dielectric layer 241, and is beneficial to improve the performance of the formed semiconductor structure.

[0101] Then, the initial first work function layer is formed on the first region I and the initial second work function layer is formed on the second region II in the gate opening 240.

[0102] In this embodiment, the initial second work function layer is formed after the initial first work function layer is formed. The process of forming the initial first work function layer and the initial second work function layer is described in detail in Figures 13 to 17 .

[0103] In other embodiments, the second work function layer can be formed before the initial first work function layer is formed.

[0104] Please refer to Figure 13 The first work function material film 250 is formed on the surface of the initial gate dielectric layer 241 and the surface of the dielectric layer 220.

[0105] The first work function material film 250 provides a material layer for the subsequent formation of the first work function layer, so as to adjust the threshold voltage of the device formed on the first region I.

[0106] In the embodiment, the first region I is used to form a P-type device, and the material of the first work function material film 250 is P-type.

[0107] Please continue to refer to Figure 13 A first sacrificial layer 251 is formed on the surface of the first work function material film 250, and the first sacrificial layer 251 fills the gate opening 240; a second mask layer 222 is formed on the surface of the first sacrificial layer 251, and the second mask layer 222 exposes the surface of the first sacrificial layer 251 on the second region II.

[0108] The material of the first sacrificial layer 251 includes an amorphous material, and in the embodiment, the material of the first sacrificial layer 251 is an organic material containing carbon and oxygen.

[0109] The second mask layer 222 includes: an anti-reflection material layer (not shown in the figure) on the surface of the first sacrificial layer 251; and a photoresist layer (not shown in the figure) on the surface of the anti-reflection material layer.

[0110] Please refer to Figure 14 The first sacrificial layer 251 and the first work function material film 250 are etched with the second mask layer 222 as a mask until the surface of the initial gate dielectric layer 241 on the second region II is exposed, so that the first work function material film 250 forms the initial first work function layer 2501.

[0111] The process of etching the first sacrificial layer 251 and the first work function material film 250 includes a main etching process and an over-etching process.

[0112] The stop position of the main etching process is to expose most of the initial gate dielectric layer 241 on the second region II; through the over-etching process, the etching by-products that are easily left in the corner of the intersection of the fin 202 and the substrate 201 after the main etching process, and the first work function material film 250 that still exists on the second region II are removed, so that the first work function material film 250 on the second region II is removed, and it is ensured that the first work function material film 250 does not exist on the second region II.

[0113] In the embodiment, the initial first work function layer 2501 also exists on part of the surface of the first sidewall 2301, and the surface of the second sidewall 2302 does not have the initial first work function layer 2501.

[0114] Please refer to Figure 15 After the initial first work function layer 2501 is formed, the second mask layer 222 and the first sacrificial layer 251 are removed.

[0115] The process for removing the second mask layer 222 and the first sacrificial layer 251 includes a wet etching process, a dry etching process or an ashing process.

[0116] It should be noted that in the present embodiment, the second mask layer 222 is completely consumed and part of the first sacrificial layer 251 is consumed in the process of forming the initial first work function layer 2501, and therefore, the remaining part of the first sacrificial layer 251 is removed after the initial first work function layer 2501 is formed.

[0117] In other embodiments, the second mask layer and the first sacrificial layer can also not be removed.

[0118] Please refer to Figure 16 The second work function material film 260 is formed on the surface of the initial first work function layer 2501 on the first region I and on the surface of the initial gate dielectric layer 241 and the surface of the dielectric layer 220 on the second region II; the second sacrificial layer 252 is formed on the surface of the second work function material film 260, and the second sacrificial layer 252 fills the gate opening 240; and the third mask layer 223 is formed on the surface of the second sacrificial layer 252, and the third mask layer 223 exposes the surface of the second sacrificial layer 252 on the first region I.

[0119] The second work function material film 260 provides a material layer for the subsequent formation of a second work function layer, thereby being able to adjust the threshold voltage of the device formed on the second region II.

[0120] In the present embodiment, the second region II is used for forming an N-type device, and the material of the second work function material film 260 is of an N-type conductive type.

[0121] The material of the second sacrificial layer 252 is the same as the material of the first sacrificial layer 251 in the above embodiment, and will not be described here again.

[0122] The material of the third mask layer 223 is the same as the material of the second mask layer 222 in the above embodiment, and will not be described here again.

[0123] In other embodiments, the first sacrificial layer is not removed after the initial first work function layer is formed; the forming method of the initial second work function layer includes: forming a second work function material film on the surface of the first sacrificial layer on the first region and on the surface of the initial gate dielectric layer and the surface of the dielectric layer on the second region; removing the first sacrificial layer and the second work function material film located on the surface of the first sacrificial layer, so that the second work function material film forms the initial second work function layer, thereby being beneficial to reducing the process steps and saving materials.

[0124] Please refer to Figure 17The second sacrificial layer 252 and the second work function material film 260 are etched by taking the third mask layer 223 as a mask until the surface of the initial first work function layer 2501 on the first region I is exposed, so that the second work function material film 260 forms the initial second work function layer 2601.

[0125] In the embodiment, the initial second work function layer 2601 is also located on the top surface of the initial isolation film 230 and the surface of the second sidewall 2302 and part of the surface of the first sidewall 2301.

[0126] In other embodiments, the initial second work function layer is only located on the surface of the second sidewall of the initial isolation film.

[0127] In the embodiment, after the initial second work function layer 2601 is formed, the second sacrificial layer 252 and the third mask layer 223 are removed.

[0128] Please continue to refer to Figure 17 The initial gate layer 270 is formed on the surfaces of the initial first work function layer 2501 and the initial second work function layer 2601, and the initial gate layer 270 fills the gate opening 240.

[0129] The initial gate layer 270 spans the first region I and the second region II and the isolation region III.

[0130] Specifically, the top surface of the initial gate layer 270 is higher than the top surface of the initial isolation film 230,

[0131] Please refer to Figure 18 The initial gate dielectric layer 241, the initial first work function layer 2501, the initial second work function layer 2601, the dielectric layer 220 and the initial gate layer 270 are planarized until the second initial work function layer 2601 on the first region I is removed, so that the initial gate dielectric layer 241 forms the gate dielectric layer 242, the initial first work function layer 2501 forms the first work function layer 2502, the initial second work function layer 2601 forms the second work function layer 2602, and the initial gate layer 270 forms the gate layer 271. The first gate structure is formed on the first region I, and the second gate structure is formed on the second region II.

[0132] The first gate structure includes: the gate dielectric layer 242 on the first region I; the first work function layer 2502 on the surface of the gate dielectric layer 242; and the gate layer 271 on the surface of the first work function layer 2502 on the first region I.

[0133] The second gate structure comprises: a gate dielectric layer 242 on the second region II; a second work function layer 2602 on the surface of the gate dielectric layer 242; and a gate layer 271 on the surface of the second work function layer 2602 on the second region II.

[0134] The planarization process also forms a first isolation film 231 from the initial isolation film 230 until the initial second work function layer 2601 on the first region I is removed.

[0135] Through the planarization process until the initial second work function layer 2601 on the first region I is removed, the first work function layer 2502 is only on the surface of the first sidewall 2301 of the first isolation film 231, the second work function layer 2602 is only on the surface of the second sidewall 2302 of the first isolation film 231, and the top surface of the first work function layer 2502 on the surface of the first sidewall 2301 is flush with the top surface of the second work function layer 2602 on the surface of the second sidewall 2302, so that the first work function layer 2502 and the second work function layer 2602 on the surface of the sidewall of the first isolation film 231 have a similar influence on the threshold voltage, and thus the threshold voltage of the device on the first region I and the threshold voltage of the device on the second region II meet the process requirements.

[0136] The first work function layer 2502 and the second work function layer 2602 have different conductive types, the conductive type of the first work function layer 2502 is P-type or N-type, and the conductive type of the second work function layer 2602 is P-type or N-type.

[0137] The P-type work function material comprises one or more of Ta, TiN, TaN, TaSiN, or TiSiN, and the N-type work function material comprises one or more of TiAl, TiAlC, TaAlN, TiAlN, TaCN, and AlN.

[0138] In this embodiment, the first region I is used to form a P-type device, the material of the first work function layer 2502 is TiN, the second region is used to form an N-type device, and the material of the second work function layer 2602 is TiAl.

[0139] Please refer to Figure 19 , the first isolation film 231 is removed to form an isolation opening (not shown) in the isolation region II, a first isolation layer 280 is formed in the isolation opening, and the material of the first isolation layer 280 is a dielectric material.

[0140] The material of the first isolation layer 280 comprises one or more of a combination of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride, and silicon carbon oxynitride.

[0141] By forming the initial isolation film 230 on the isolation region III first, and then forming the first work function layer 2502 on the first region I and the second work function layer 2602 on the second region II respectively, since the initial isolation film 230 is formed in a more accurate position, the first work function layer 2502 formed on the first region I and the second work function layer 2602 formed on the second region II can be accurately isolated. Moreover, the first work function layer 2502 affects the threshold voltage of the device on the first region I, and the second work function layer 2602 affects the threshold voltage of the device on the second region II, so that the initial isolation film 230 in the accurate position is beneficial to isolate the devices on the first region I and the second region II respectively, and further makes the threshold voltage of the device on the first region I and the threshold voltage of the device on the second region II meet the process requirements.

[0142] Correspondingly, the embodiment of the present application also provides a semiconductor structure, please continue to refer to Figure 18 , comprising: a substrate, the substrate comprising adjacent first region I and second region II and isolation region III between the first region I and the second region II, the substrate having a dielectric layer 220, the dielectric layer 220 having a gate opening 240, and the gate opening 240 across the first region I, isolation region III and second region II; the first isolation layer 231 located in the gate opening 240 and on the isolation region III; the first work function layer 2502 located in the gate opening 240 and on the first region I and the second work function layer 2602 located in the gate opening 240 and on the second region II respectively.

[0143] The first isolation layer 231 located on the isolation region III can isolate the first work function layer 2502 on the first region I and the second work function layer 2602 on the second region II, and can accurately isolate the first work function layer 2502 formed on the first region I and the second work function layer 2602 formed on the second region II. Moreover, the first work function layer 2502 affects the threshold voltage of the device on the first region I, and the second work function layer 2602 affects the threshold voltage of the device on the second region II, so that the initial isolation film 230 in the accurate position is beneficial to isolate the devices on the first region I and the second region II respectively, and further makes the threshold voltage of the device on the first region I and the threshold voltage of the device on the second region II meet the process requirements.

[0144] The following will be described in detail in conjunction with the accompanying drawings.

[0145] In the embodiment, the material of the first isolation layer 231 comprises: amorphous silicon, polycrystalline silicon, amorphous germanium or polycrystalline germanium, and is doped with boron ions, phosphorus ions, gallium ions or arsenic ions.

[0146] In other embodiments, the material of the first isolation layer comprises a dielectric material comprising one or more of a combination of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon aluminum nitride, and silicon aluminum oxynitride.

[0147] The first isolation layer 231 has a size ranging from 4 nm to 15 nm in a direction perpendicular to the sidewall surface of the first isolation layer 231.

[0148] The semiconductor structure further comprises a gate dielectric layer 242 located in the gate opening 240 and on the first region I and the second region II, and a gate layer 271 located on the surface of the first work function layer 2502 and the second work function layer 2602.

[0149] The sidewall of the first isolation layer 231 comprises opposite first and second sidewalls 2301 and 2302, and the gate dielectric layer 242 is further located on the surface of the first and second sidewalls 2301 and 2302.

[0150] The first work function layer 2502 is further located on the surface of the gate dielectric layer 242 on the first sidewall 2301, the second work function layer 2602 is further located on the surface of the gate dielectric layer 242 on the second sidewall 2302, and the top surface of the first work function layer 2502 on the first sidewall 2301 is flush with the top surface of the second work function layer 2602 on the second sidewall 2302.

[0151] The substrate comprises a substrate 201 and a plurality of mutually separated fins 202 and a second isolation layer 203 located on the surface of the substrate 201, the fins 201 extend along a first direction X, and the second isolation layer 203 covers part of the sidewall surface of the fins 202; the gate opening 240 extends along a second direction, and the first direction X is perpendicular to the second direction.

[0152] In other embodiments, the substrate comprises a substrate and a plurality of nanostructures and a second isolation layer located on the surface of the substrate, the nanostructure comprises a plurality of mutually separated nanowires stacked along the normal direction of the surface of the substrate, the nanostructure extends along a first direction, and the second isolation layer covers the sidewall surface of the bottommost nanowire; the gate opening extends along a second direction, and the first direction is perpendicular to the second direction.

[0153] Although the present application has been disclosed as above, the present application is not limited to this. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and the protection scope of the present application should be defined by the scope of the claims.

Claims

1. A method of forming a semiconductor structure, characterized by, The method comprises the following steps: providing a substrate, which comprises adjacent first and second regions and an isolation region between the first and second regions, and a dielectric layer on the substrate; forming an initial isolation film on the isolation region; after forming the initial isolation film, forming a gate opening in the dielectric layer, which extends across the first, isolation and second regions; after forming the gate opening and before forming an initial first work function layer and an initial second work function layer, modifying the initial isolation film to reduce the size of the initial isolation film by reducing the side walls of the initial isolation film in a direction perpendicular to the side walls of the initial isolation film; forming an initial gate dielectric layer on the surfaces of the first region, the second region, the surface of the initial isolation film exposed by the modification and the surface of the dielectric layer; forming an initial first work function layer on the first region and an initial second work function layer on the second region in the gate opening; planarizing the initial gate dielectric layer, the initial first work function layer and the initial second work function layer until the second initial work function layer on the first region is removed, so that the initial isolation film becomes a first isolation film, the initial gate dielectric layer becomes a gate dielectric layer, the initial first work function layer becomes a first work function layer and the initial second work function layer becomes a second work function layer; removing the first isolation film to form a separation opening in the isolation region; forming a first isolation layer in the separation opening, which is made of a dielectric material.

2. The method of forming a semiconductor structure of claim 1, wherein The method further comprises the following steps: before forming the initial isolation film, forming an initial dummy gate layer on the isolation region, the first region and the second region, and exposing the top surface of the initial dummy gate layer by the dielectric layer; forming a dummy gate layer during the formation of the initial isolation film; the method of forming the initial isolation film and the dummy gate layer comprises the following steps: ion implanting the initial dummy gate layer on the isolation region to form the initial isolation film on the isolation region and the dummy gate layer on the first and second regions; removing the dummy gate layer on the first and second regions to form the gate opening in the dielectric layer.

3. The method of forming a semiconductor structure of claim 2, wherein, The method of ion implantation comprises the following steps: forming a first mask layer on the initial dummy gate layer and the surface of the dielectric layer, which exposes the initial dummy gate layer on the isolation region; and ion implanting the initial dummy gate layer with the first mask layer as a mask.

4. The method of forming a semiconductor structure of claim 2, wherein The etching selectivity ratio of the process of removing the dummy gate layer to the dummy gate layer and the initial isolation film ranges from 20:1 to 5:1; the process parameters of removing the dummy gate layer include that the etching solution is a mixture of two or more of ammonia, tetramethylammonium hydroxide solution and hydrogen peroxide.

5. The method of forming a semiconductor structure of claim 2, wherein, The parameters of the ion implantation include: the implanted ions include boron ions, phosphorus ions, gallium ions or arsenic ions, the implanted dose ranges from 1.0E14 atom / cm 3 to 1.0E20 atom / cm 3 , and the implanted energy ranges from 10 KeV to 200 KeV.

6. The method of forming a semiconductor structure of claim 2, wherein, forming the dielectric layer after forming the initial dummy gate layer; the method of forming the dielectric layer comprises the following steps: forming a dielectric material film on the substrate and the surface of the initial dummy gate layer; and planarizing the dielectric material film until the top surface of the initial dummy gate layer is exposed to form the dielectric layer on the substrate.

7. The method of forming a semiconductor structure of claim 2, wherein The method further comprises the following steps: After forming the gate opening, before forming the initial first work function layer and the initial second work function layer, an initial gate dielectric layer is formed on the surfaces of the first region, the second region, the initial isolation film and the dielectric layer; after forming the initial first work function layer and the initial second work function layer, an initial gate electrode layer is formed on the surfaces of the initial first work function layer and the initial second work function layer, and the initial gate electrode layer fills the gate opening; the initial gate dielectric layer, the initial first work function layer, the initial second work function layer, the dielectric layer and the initial gate electrode layer are planarized until the second initial work function layer on the first region is removed, so that the initial gate dielectric layer forms a gate dielectric layer, the initial first work function layer forms a first work function layer, the initial second work function layer forms a second work function layer, the initial gate electrode layer forms a gate electrode layer, a first gate structure is formed on the first region, and a second gate structure is formed on the second region.

8. The method of forming a semiconductor structure of claim 7, wherein, The first work function layer and the second work function layer are of different conductive types, the first work function layer is of P-type or N-type, and the second work function layer is of P-type or N-type. The P-type work function material includes one or more of Ta, TiN, TaN, TaSiN or TiSiN; and the N-type work function material includes one or more of TiAl, TiAlC, TaAlN, TiAlN, TaCN and AlN.

9. The method of forming a semiconductor structure of claim 7, wherein, The initial first work function layer is formed before the initial second work function layer.

10. The method of forming a semiconductor structure of claim 9, wherein, The method for forming the initial first work function layer includes: forming a first work function material film on the surface of the initial gate dielectric layer and the surface of the dielectric layer; forming a first sacrificial layer on the surface of the first work function material film, and the first sacrificial layer fills the gate opening; forming a second mask layer on the surface of the first sacrificial layer, and the second mask layer exposes the surface of the first sacrificial layer on the second region; etching the first sacrificial layer and the first work function material film with the second mask layer as a mask until the surface of the initial gate dielectric layer on the second region is exposed, so that the first work function material film forms the initial first work function layer; and after forming the initial first work function layer, the second mask layer and the first sacrificial layer are removed.

11. The method of forming a semiconductor structure of claim 10, wherein, After removing the second mask layer and the first sacrificial layer, the initial second work function layer is formed; the method for forming the initial second work function layer includes: forming a second work function material film on the surface of the initial first work function layer on the first region, the surface of the initial gate dielectric layer on the second region and the surface of the dielectric layer; forming a second sacrificial layer on the surface of the second work function material film, and the second sacrificial layer fills the gate opening; forming a third mask layer on the surface of the second sacrificial layer, and the third mask layer exposes the surface of the second sacrificial layer on the first region; etching the second sacrificial layer and the second work function material film with the third mask layer as a mask until the surface of the initial first work function layer on the first region is exposed, so that the second work function material film forms the initial second work function layer; and after forming the initial second work function layer, the second sacrificial layer is removed.

12. The method of forming a semiconductor structure of claim 10, wherein forming the initial second work function layer after forming the initial first work function layer and before removing the first sacrificial layer; the method of forming the initial second work function layer comprises: forming a second work function material film on the first sacrificial layer surface of the first region and the initial gate dielectric layer surface and the dielectric layer surface of the second region; removing the first sacrificial layer and the second work function material film on the first sacrificial layer surface to form the initial second work function layer from the second work function material film.

13. The method of forming a semiconductor structure of claim 7, wherein, the sidewall of the initial isolation film comprises opposite first sidewall and second sidewall; the initial first work function layer is also on part of the first sidewall surface; the initial second work function layer is also on the top surface of the initial isolation film and the second sidewall surface and part of the first sidewall surface; the process of planarizing the initial gate dielectric layer, the initial first work function layer and the initial second work function layer also forms the initial isolation film into the first isolation film until the second initial work function layer on the first region is removed.

14. The method of forming a semiconductor structure of claim 1, wherein, the material of the first isolation layer comprises one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride and silicon carbon oxynitride.

15. The method of forming a semiconductor structure of claim 1, wherein, the modification process comprises isotropic etching or anisotropic etching.

16. The method of forming a semiconductor structure of claim 15, wherein, the modification process is an isotropic etching process; the parameters of the isotropic etching process comprise: the main etching gas used comprises NH3, H2 and NF3; the auxiliary etching gas used comprises Ar or He; the pressure is 2 Torr to 10 Torr; the source power ranges from 10 W to 200 W.

17. The method of forming a semiconductor structure of claim 15, wherein, after the modification process, the size of the initial isolation film ranges from 4 nm to 15 nm.

18. The method of forming a semiconductor structure of claim 1, wherein, the substrate comprises a substrate and a plurality of mutually separated fins and a second isolation layer on the substrate surface, the fins extend along a first direction, and the second isolation layer covers part of the sidewall surface of the fins; the gate opening extends along a second direction, and the first direction is perpendicular to the second direction.

19. The method of forming a semiconductor structure of claim 1, wherein, the substrate comprises a substrate and a plurality of nanostructures and a second isolation layer on the substrate surface, the nanostructure comprises a plurality of mutually separated nanowires stacked along the normal direction of the substrate surface, the nanostructure extends along a first direction, and the second isolation layer covers the sidewall surface of the bottommost nanowire; the gate opening extends along a second direction, and the first direction is perpendicular to the second direction.

20. A semiconductor structure, comprising: formed by the method of forming a semiconductor structure according to any one of claims 1 to 19; the semiconductor structure comprises: a substrate comprising adjacent first and second regions and an isolation region between the first and second regions, the substrate having a dielectric layer thereon, the dielectric layer having a gate opening therein, and the gate opening extending across the first region, the isolation region and the second region; a gate dielectric layer in the gate opening and on the first and second regions; a first isolation layer in the gate opening and on the isolation region, the sidewall of the first isolation layer comprising opposite first and second sidewalls; the gate dielectric layer is also on the first and second sidewall surfaces; a first work function layer and a second work function layer located in the gate opening and on a first region and a second region, respectively; wherein the first work function layer is located on the first sidewall and on a surface of the gate dielectric layer on the first region, the second work function layer is located on the second sidewall and on a surface of the gate dielectric layer on the second region, and a top surface of the first work function layer on the first sidewall is flush with a top surface of the second work function layer on the second sidewall.

21. The semiconductor structure of claim 20, wherein, a dimension of the first spacer layer in a direction perpendicular to the sidewall surface of the first spacer layer ranges from 4 nm to 15 nm.

22. The semiconductor structure of claim 20, wherein, further comprising: a gate layer located on surfaces of the first work function layer and the second work function layer.

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