Control circuit and corresponding method

Abstract

Embodiments of the present disclosure relate to control circuits and corresponding methods. A circuit receives an input signal having a first level and a second level. The logic circuit includes a finite state machine circuit, an edge detection circuit, and a timer circuit. The finite state machine circuit is configured to set an operating mode of the circuit. The edge detection circuit is configured to detect a transition between the first level and the second level. The timer circuit is configured to determine whether the first level or the second level is maintained for a period of time, the period starting from the transition detected by the edge detection circuit. The finite state machine circuit is configured to change the operating mode based on the timer circuit determining that the first level or the second level has been maintained for a period of time.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Italian Application No. 102020000026530 filed on November 6, 2020, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to control logic for electronic circuits and, in particular embodiments, to dynamically managing two different operating modes for a device and an external clock via a single pin. Background Art

[0004] Some types of electronic devices may support two different modes of operation. Synchronization with a clock signal generated by an external master clock may be desirable for one or both of these modes.

[0005] For example, a switching DC-DC converter can function in a low consumption mode (e.g., burst switching) and a low noise mode (e.g., constant switching). For the latter mode, a synchronization signal can be provided by an external clock signal applied to a pin in the device, which can recognize the signal frequency.

[0006] In packages with a limited number of pins, any of the possible operating modes may be selected by a different "part number" defined for each mode, or a "pin shorting" function may be provided which sets the operating mode at device startup so that the same pins can be used for other functions in the stable state.

[0007] Furthermore, if the selected mode provides possible synchronization with an external clock (eg, this may be the case with low noise mode), the clock may be supplied via a dedicated pin.

[0008] This may lead to a limitation of the possible fields of application of the device, since dynamic switching from one mode to another (as may be desired) is not supported.

[0009] What is desired is a scheme that provides greater flexibility in these situations, where a single pin of a device is configured to facilitate dynamic (eg, on-the-fly) transitions between different operating modes, as well as managing an external synchronous clock via the same pin. Summary of the invention

[0010] According to one or more embodiments, a circuit and method are provided herein.

[0011] As discussed, the flexibility of those devices having different operating modes adapted to be selected from the outside can be disadvantageous in applications where it is desired to change the mode of operation on the fly. As described, static selection between two different operating modes via pin shorting or by assigning different part numbers to each of the two modes does not adequately address this problem.

[0012] At least in principle, dynamic mode changes could be implemented by programming of internal registers, which would involve continued accessibility of standard programming interfaces.

[0013] One or more embodiments may develop a single pin of a device with reduced area increase to facilitate possible dynamic management of two different operating modes while also providing an external synchronous clock via the same pin.

[0014] In one or more embodiments, for a device configured to dynamically switch between two different operating modes, using a single pin provides the advantage of avoiding the use of multiple pins, wherein one of the two modes involves an external clock for synchronization. In this embodiment, for an operating mode that does not involve an external clock, no additional pins will be used.

[0015] In one or more embodiments, the operating mode may be determined by temporal evaluation of a level present on, for example, an input pin (eg, a single tx_t). This configuration may be used for mode selection as well as for applying an external clock.

[0016] In one or more embodiments, an external control level is associated with each mode, wherein the logic circuit is configured to check the level change of the signal by detecting, for example, a falling edge associated with a level change. In these embodiments, a low level is associated with a first operating mode (MODE1), and a high level is associated with a second operating mode (MODE2). For example, if the level signal is driven low at startup, the device "knows" that the current configuration is in MODE1, and the relevant configuration is implemented in the device. If a level change that may involve a configuration change occurs, the logic circuit can process the relevant information of the evaluation duration. A (lower) time threshold can be selected for each specific application. If the signal on the (single) pin discussed previously is maintained at a constant level above the threshold for a duration, the change of configuration is verified.

[0017] The presence of a clock signal on the pin can be detected as continuous level changes.

[0018] One or more embodiments may include a finite state machine (FSM) circuit that handles changes between two operating modes and external clocks and enable and control signals. An edge detector may be provided to detect a rising or falling edge of a signal at an input pin corresponding to a level change. A level filter may be provided to evaluate a level change signal to, for example, check whether this is maintained for longer than a time threshold before modifying the operating mode or state. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] For a more complete understanding of the present disclosure and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0020] Figure 1 and Figure 2 A diagram showing the operation mode conversion of an embodiment;

[0021] Figure 3 is a block diagram of an embodiment;

[0022] Figure 4 A flowchart of the operation of the embodiment;

[0023] Figure 5 A diagram of the operational mode transitions to maintain a valid embodiment;

[0024] Figure 6 A diagram for maintaining a non-valid embodiment operating mode transition;

[0025] Figure 7 A diagram of an embodiment of external clock verification; and

[0026] Figure 8 A diagram showing an embodiment with external clock removed. DETAILED DESCRIPTION

[0027] The present disclosure provides many applicable inventive concepts that can be implemented in a wide variety of specific situations. Specific embodiments only illustrate specific configurations and do not limit the scope of the claimed embodiments. Features from different embodiments can be combined to form other embodiments, unless otherwise stated.

[0028] The changes or modifications described in one embodiment of the embodiment may also be applied to other embodiments. In addition, it should be understood that various changes, substitutions and modifications can be made herein without departing from the spirit and scope of the present disclosure as defined in the appended claims.

[0029] In the following description, one or more specific details are explained to provide a deeper understanding of the examples of the embodiments described herein. The embodiments can be obtained without one or more of the specific details or with other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not explained or described in detail so that some aspects of the embodiments will not be difficult to understand.

[0030] Reference to "an embodiment" or "one embodiment" in the framework of the description of the present invention is intended to indicate that a particular configuration, structure, or characteristic described with respect to the embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in an embodiment" that may be presented in one or more points in the description of the present invention do not necessarily refer to one or the same embodiment.

[0031] Furthermore, in one or more embodiments, particular configurations, structures, or characteristics may be combined in any suitable manner.

[0032] The headings / references used herein are provided for convenience only, and therefore do not limit the scope of protection or the scope of the embodiments.

[0033] One or more embodiments may be applicable, for example, to circuits such as the L7983 synchronous buck switching regulator device, currently available from STMicroelectronics.

[0034] This circuit can be seen as an example of a circuit enabling (at least) two different operating modes, namely a low consumption mode (LCM) and a low noise mode (LNM); with the possibility of managing these two modes, for example, via a single pin and with the switching action of the low noise mode being synchronized with an external clock. Reference to this circuit is by way of example only and does not limit the embodiments.

[0035] One or more embodiments facilitate selection between different operating modes through a single pin of a device (e.g., through dynamic management of transitions from one mode to another). In addition, one or more embodiments provide logic circuitry capable of checking whether an external synchronous clock signal is present on the pin.

[0036] As discussed, certain devices that fix the operating mode at startup (eg, via a pull-up to VCC or a pull-down to GND on a select pin) do not account for the possibility of dynamically changing the operating mode as desired by various applications.

[0037] For example, in some devices, the configuration is fixed via trim bits, which can limit flexibility. In addition, if synchronization with an external clock is considered for one of the operating modes, the pin used to provide the clock can be left floating when the device is configured for a mode or application where synchronization is not desired.

[0038] One or more embodiments may involve a temporal evaluation mechanism for signal values ​​at input pins of device configuration, thereby providing greater flexibility in device usage.

[0039] Figure 1 and Figure 2 By way of example, a possible switchover between two operating modes, namely MODE1 and MODE2, is indicated. Figure 1 This is an example of switching from MODE1 to MODE2. Figure 2 is an example of a transition from MODE 2 to MODE 1. It will be further appreciated that one or more embodiments are very "transparent" to the nature of these two modes of operation.

[0040] The example shown refers to pin 10 in the electronic circuit ( Figure 1 and Figure 2 Pin 10 may be configured to receive a signal MODSEL_CLKEXT for selecting between two operation modes, namely MODE1 and MODE2.

[0041] Throughout this description, for simplicity and ease of understanding, pin 10 will also be referred to as the MODSEL_CLKEXT pin.

[0042] In the example shown, this MODSEL_CLKEXT pin may also be used to provide associated devices with a (eg, external) synchronous clock CLKEXT, as desired in either (or both) of the two aforementioned operating modes.

[0043] For example, an operating mode (MODE1 or MODE2) may be selected on the MODSEL_CLKEXT pin by maintaining the pin at a constant level (e.g., high or low, where each level is associated with one of the modes) for a time Tmin. The time Tmin used to maintain the signal level may be set to vary (possibly through its settings) depending on the application in which the device is intended to be used.

[0044] For example, in Figure 1 In the example, when MODE1 is enabled, the rising edge of the signal at the MODSEL_CLKTEXT pin can be “filtered” within Tmin to detect a stable high level before the internal mode signal is set to MODE2.

[0045] In addition, Figure 2 In the example, when MODE2 is enabled, the falling edge of the signal at the MODSEL_CLKTEXT pin can be “filtered” within Tmin to detect a stable low level before the internal mode signal is set to MODE1.

[0046] Those skilled in the art will readily appreciate that specific references to rising / falling edges and high / low levels are merely exemplary, as the same type of operation can be obtained where the roles of rising / falling edges and / or high / low levels are reversed.

[0047] In one or more embodiments, the time Tmin may be used to determine the current operating mode (ie, MODE1 or MODE2) and to facilitate dynamic switching between the two modes when a change in operating mode is desired.

[0048] One or more embodiments may involve detection logic that continuously detects rising and falling edges of the signal at the MODSEL_CLKEXT input pin, with the ability to detect level changes and determine the operating mode based on the following mechanism.

[0049] For example, if at device startup, the high level or the low level of the signal at MODSEL_CLKEXT remains stable for a minimum time T at least equal to Tmin, then the device is configured in the corresponding operating mode.

[0050] Furthermore, if a (falling or rising) edge of the signal is subsequently detected causing a level change (e.g., from high to low or vice versa) and the new level is maintained for a time T at least equal to Tmin, then the logic interprets this level change as expected to produce a change in the operating mode of the device.

[0051] Furthermore, if a pulse train (eg continuous level changes or toggling) is detected at the pin, a check is made for the possible presence of an external synchronization clock - either a spike affecting the signal value or continuous transitions between operating modes.

[0052] For example, if detecting that the signal level at the MODSEL_CLKEXT pin switches at a time period T shorter than time Tmin is considered an indication of a stable level, then the time between consecutive rising edges of the signal can be analyzed (e.g., based on information received from a circuit block that can filter the external clock).

[0053] Furthermore, if at least N rising edges of the signal are detected for a period less than or equal to the lower threshold Tckmin, then it is assumed that a CLKEXT clock signal with a frequency greater than or equal to 1 / Tckmin is present at the pin.

[0054] The time Tckmin may be selected as the longest period considered by the external clock (ie its maximum value) - an indication of the lowest (ie minimum) frequency within the frequency range considered by the external clock. A summary of the selection mechanism discussed above is reproduced in Table I below.

[0055] Table I – Operation mode selection based on signal level

[0056]

[0057]

[0058] Those skilled in the art will again appreciate that specific references to low / high levels and MODE1 / MODE2 are exemplary only, as the roles of levels and modes may be reversed to implement the same type of operation.

[0059] In an embodiment, a circuit such as an integrated device is considered to have (at least) two different operating modes (e.g., MODE1 and MODE2), which can be selected based on two different levels of a signal applied to an input pin (MODSEL_CLKEXT), where the same pin can also provide an external clock for synchronization.

[0060] In this embodiment, the pin is driven externally via, for example, a microprocessor or other logic circuit to facilitate switching from MODE1 to MODE2 (see Figure 1 ) or to MODE1 when MODE2 is enabled (see Figure 2 ) of the device switching operating mode during operation.

[0061] For instance, in the illustrated example, the operating mode may be enabled upon device startup as a default mode, which may be selected in response to a low signal ("0") at the MODSEL_CLKEXT input pin.

[0062] The control logic processes the corresponding signal of the value "0" and indicates the value MODE1 of the internal mode signal.

[0063] The mode MODE2 may be selected in response to a high level present at the input pin MODSEL_CLKEXT corresponding to a value “1” of the internal mode signal.

[0064] Figure 3 is a block diagram illustration of an embodiment circuit 100 in accordance with an embodiment described herein including control logic and some support blocks.

[0065] like Figure 3 As shown in FIG. 1 , the circuit 100 includes a logic circuit 120 built around a finite state machine (FSM) circuit 12, which is configured to manage transitions between two operating modes (i.e., MODE1, MODE2) and selection of an external clock based on signals from various blocks in the logic circuit and supporting blocks.

[0066] For example, Figure 3As illustrated in , circuit 12A may be configured to generate a mode signal (mode=MODE1 or MODE2) in accordance with signals old_mode, new_mode, and update_mode of finite state machine circuit 12, as discussed below.

[0067] As similarly discussed below, the finite state machine circuit 12 may also be configured to generate signals CLK_EXT_GOOD and CLK_EXT_FILT associated with the selection of an external clock, as discussed below.

[0068] like Figure 3 As illustrated in FIG. 1 , the logic circuit 120 includes an edge detection circuit 14 that is sensitive to the signal MODSEL_CLKEXT at the pin 10. The edge detection circuit 14 is configured to detect a rising edge or a falling edge of the input signal received at the pin, which corresponds to a level change of the signal MODSEL_CLKEXT and generates a corresponding signal mode_clkext_edge applied to the finite state machine circuit 12.

[0069] like Figure 3 As shown in FIG. 1 , the logic circuit 120 further includes a timer circuit 16. The timer circuit 16 may include a counter configured to evaluate (i.e. enabled by the signal mode_cnt_en from the finite state machine circuit 12) whether the level change of the signal MODSEL_CLKEXT at the pin 10 is maintained for a minimum time (Tmin) before validating the new operating mode. Due to the count signal mode_cnt (see also FIG. 1 ) reaching the upper threshold value (Thmin), the count signal mode_cnt (see also FIG. 1 ) is automatically reset to the default state. Figure 4 and Figure 5 ), and thus may involve generating an overflow signal applied to the active state machine circuit 12, the upper threshold being based on the time Tmin discussed previously.

[0070] like Figure 3 As illustrated in , logic circuit 120 also receives information from check circuit 18 and counter circuit 20 to verify the presence of an external clock signal applied to pin 10, possibly as the MODSEL_CLKEXT signal.

[0071] like Figure 3 As illustrated in the figure, the check circuit 18 includes a counter that is configured to evaluate whether the frequency of the incoming pulse train received at the pin 10 corresponds to (i.e., complies with) the lowest (i.e., minimum frequency) frequency allowed by the external clock by generating a corresponding signal (i.e., designated TCLK_GOOD in the figure) applied to the finite state machine circuit 12.

[0072] like Figure 3As illustrated in the figure, the counter circuit 20 includes another counter that is configured to count N number of rising edges of the incoming pulse train received as MODSEL_CLKEXT, which is beneficial for determining the presence of an external clock by generating a corresponding signal (i.e., designated NPulse_OK in the figure) applied to the finite state machine circuit 12.

[0073] like Figure 3 As described in FIG. 1 , the circuit 100 also includes a clock circuit 22 (of any type known to those skilled in the art) that generates an internal clock signal CLK_INT that is supplied to the control logic 120, as described below in conjunction with Figure 5 and Figure 6 discussed.

[0074] Even though illustrated as separate components for ease of explanation, the clock circuit 22 may be included in Figure 3 In the circuit 140.

[0075] like Figure 3 , logic circuit 120 is configured to pass the signal modes, CLK_EXT_GOOD and CLK_EXT, to another circuit 140 in circuit 100. These circuit stages may include, for example, one or more analog blocks and oscillators.

[0076] One or more embodiments are very "transparent" to the nature of the circuit 140, which also motivates the embodiments to be very transparent to the nature of the modes (ie, MODE1, MODE2).

[0077] Figure 4 is a flow chart of an exemplary embodiment of possible operation of the control logic as previously discussed.

[0078] Step 1000 corresponds to the start (start-up mode).

[0079] At step 1002 , the device is configured to operate in a default mode selected from MODE1 and MODE2 , the default mode depending on the current value (eg, low or high) of the signal MODSEL_CLKEXT (ie, mode=MODSEL_CLKEXT).

[0080] At step 1004, a check is made for the occurrence of a rising / falling edge in the signal MODSEL_CLKEXT as indicated by the signal modsel_clkext_edge from the edge detection circuit 14. If the check yields a negative result (no=no edge detected), then a return is made to step 1002.

[0081] At step 1006 , if the check at step 1004 yields a positive result (ie, yes=edge detected), then signal mode_new is made equal to MODSEL_CLKEXT.

[0082] At step 1008 , the duration of the level transition caused by the edge is measured by setting mode_cnt_en=“1”, the count CNT=CNT+1 is increased, and the mode is set to the current mode, ie, mode=mode_curr.

[0083] At step 1010, the current (cumulative) count value is checked against a threshold value corresponding to Tmin for overflow. At each increment, the value is compared to the threshold value, and an overflow signal is generated in response to the count reaching the count value.

[0084] At step 1012, if the check at step 1010 yields a negative result (i.e., no = the threshold duration is not exceeded), then another check is performed as to whether modsel_clkext_edge from edge detection circuit 14 indicates a (further) edge. If the check at step 1012 yields a negative result (i.e., no = another edge is not detected), then a return is made to step 1008.

[0085] At step 1014 , if the result of the check at step 1010 is positive (ie, yes=count overflow occurs, indicating that the level change of MODSEL_CLKEXT continues for more than Tmin), then mode_cnt_en=“0” and update_mode=mode_new.

[0086] At step 1016, the operating mode is set to the new mode (caused by the change) mode=update_mode.

[0087] At step 1018, when the counter has exceeded the threshold, in response to the result of the check at step 1012 being positive (ie, yes = another edge detected), CNT is set to "0", indicating a spike in the input signal as expected.

[0088] At step 1020, check whether CLK_EXT_GOOD from check circuit 18 indicates that the frequency of the received incoming pulse train is consistent with the lowest (minimum) frequency allowed by the external clock. If the check result at step 1020 is negative (i.e., a spike in the input signal is confirmed), then return to step 1006.

[0089] At step 1022, in response to the check at step 1020 being positive (ie, the frequency of the received incoming pulse train is consistent with the minimum frequency allowed by the external clock), then proceed to step 1016 as previously discussed.

[0090] At step 1024, regardless of the path subsequently taken to step 1016 (e.g., from step 1014 or step 1022), another check is performed to see if CLK_EXT_GOOD from the check circuit 18 indicates that the frequency of the received incoming pulse train is consistent with the minimum frequency allowed by the external clock. If the check result at step 1024 is positive, then return to step 1016.

[0091] At step 1026, in response to the result of the check at step 1024 being negative (i.e., no), another check is performed whether modsel_clkext_edge from the edge detection circuit 14 indicates a (further) edge. If the result of the check at step 1026 is negative (i.e., no = another edge is not detected), then return to step 1016. If the result of the check at step 1026 is positive (i.e., yes = another edge is detected), then return to step 1006.

[0092] It should be noted that the check of CLK_EXT_GOOD at steps 1016 - 1024 reached from step 1014 in response to a count overflow corresponding to a mode change will be negative, and the current mode will be maintained until a new signal edge occurs.

[0093] Furthermore, in response to identifying that the external clock arrives at step 1016 - step 1024 , the check for CLK_EXT_GOOD will be positive from step 1022 , and the pattern corresponding to the presence of the external clock will be maintained until the check becomes negative.

[0094] In addition, the signal CLK_EXT_GOOD generated by the finite state machine circuit 12 depends on the signals TCLK_GOOD (e.g., the distance between two consecutive rising edges corresponding to the minimum expected frequency) and Npulse_OK (e.g., the count of at least N>1 rising edges on the MODSEL_CLKEXT pin) from the check circuit 18 and the counter circuit 20, respectively, where these blocks are enabled at the rising edge of the signal at the MODSEL_CLKEXT pin.

[0095] As previously discussed, operations can be further performed by referring to Figure 5 and Figure 6 These diagrams depict the possible timing behavior of the following signals (from top to bottom) on a common time scale t (scale on the abscissa): Figure 3) internal clock signal CLK_INT; signal MODSEL_CLKEXT received at pin 10; signal new_mode from finite state machine circuit 12; signal mode_clkext_edge from edge detection circuit 14; enable signal mode_cnt_en provided by finite state machine circuit 12 to timer circuit 16; level filter signal mode_cnt; signal mode_cnt provided by timer circuit 16 in response to signal mode_cnt reaching upper threshold value th min an overflow signal provided to the finite state machine circuit 12 (which varies according to the threshold time Tmin); and a mode signal for switching (for example, from MODE1 to MODE2).

[0096] In short, when the signal on the MODSEL_CLKEXT pin (i.e., pin 10) undergoes a level shift (e.g., Figure 5 When mode_clkext_edge changes from low to high in the signal processing, the edge detection circuit 14 detects the change (which is the signal edge) and generates a corresponding mode_clkext_edge pulse.

[0097] This pulse is processed in the finite state machine circuit 12, which thereby performs various actions, as previously described in connection with Figure 4 As discussed in the flowchart: a mode_cnt_en signal is generated, the timer circuit 16 is enabled, the mode signal is maintained at the current level (e.g., low level = MODE1) until the new level is verified (e.g., high level = MODE2), and the change in the new level is stored via the internal signal new_mode (e.g., high level = MODE2).

[0098] The timer circuit 16, enabled by the mode_cnt_en signal from the finite state machine circuit 12, increments the mode_cnt counter at each cycle of the internal clock CLK_INT until a threshold count value th is reached. min until.

[0099] As discussed, this threshold may be defined as a minimum time value Tmin established upon verification of the operating mode for the device.

[0100] When the mode_cnt counter reaches a threshold (eg, has no further changes in detected signal levels), the timer circuit 16 generates an overflow signal (eg, a flag) that resets the count.

[0101] In response to detecting the overflow flag, finite state machine circuit 12 updates the internal mode signal to the logic value previously stored at “new_mode” (eg, high level=MODE2), which is evaluated as stable by timer circuit 16 within time Tmin.

[0102] Then the device operation mode is updated to a new operation mode (eg, MODE2).

[0103] Similarly, if a subsequent falling edge is detected on the input pin (ie, MODSEL_CLKEXT at pin 10), and the signal level remains low for greater than Tmin after this edge, the finite state machine circuit 12 will again change the operating mode (eg, to MODE1).

[0104] If the signal present at the input pin changes level again and then the counter (signal mode_cnt) reaches the threshold th min If the input signal returns to the previous level before, the logic circuit 120 will not change the value of the mode signal, thereby treating the change as a spike in the input signal.

[0105] exist Figure 6 This possible mode of operation is illustrated in FIG.

[0106] As stated, Figure 5 is an example of a mode transition causing a change from MODE1 to MODE2 in response to a rising edge in signal MODSEL_CLKEXT, which results in assertion of the overflow signal.

[0107] By comparison, Figure 6 The right hand side of FIG. 1 is an example of an "invalid" mode transition, where MODE1 is maintained (regardless of the falling edge in signal MODSEL_CLKEXT) for not reaching the threshold corresponding to Th. min The threshold value of the counting signal mode_cnt is the result.

[0108] If a pulse train appears on the MODSEL_CLKEXT pin (ie, pin 10), logic circuit 120 can investigate whether this corresponds to an external clock or is caused by a continuous change in the operating mode.

[0109] This operation type is Figure 7 (External Clock Verification) and Figure 8 (External Clock Removal) is exemplified.

[0110] These figures again depict a common time scale t (abscissa scale), possible timing behavior of the following signals (from top to bottom): signal MODSEL_CLKEXT received at pin 10; signal CLK_EXT_GOOD from finite state machine circuit 12; signal CLK_EXT_FILT from finite state machine circuit 12; and switching (e.g. at Figure 7 From MODE1 to MODE2, and in Figure 8 MODE signal from MODE2 to MODE1).

[0111] As illustrated herein, counter circuit 20 detects each rising edge of the signal on the MODSEL_CLKEXT pin (ie, pin 10 ) and generates an Npulse_OK signal in response to having counted N number of rising edges.

[0112] At the same time, filtering of the frequency of the clock signal received at the MODSEL_CLKEXT pin (i.e., pin 10) is performed in the check circuit 18. The check circuit 18 is enabled at each rising edge of the signal on the MODSEL_CLKEXT pin and is configured to evaluate the distance between two consecutive rising edges and undergo a reset when the distance between the edges exceeds the value of the minimum expected frequency of the (expected) external clock signal.

[0113] If the detected edges are separated by a time Tck shorter than Tckmin, the check circuit 18 generates a TCLK_GOOD signal. Therefore, the logic circuit 120 will generate an internal signal CLK_EXT_GOOD to verify the presence of the external clock CLK_EXT on pin 10 (MODSEL_CLKEXT). The clock will therefore have a period defined by the switching time Tck of the pulse train.

[0114] The mode signal will be adapted to mode MODE2 which in the example shown provides for the supply of / synchronization with an external clock.

[0115] For example, if MODE1 was enabled before receiving the burst, then the mode is changed from MODE1 to MODE2. On the other hand, if MODE2 was the enabled mode before the burst, then MODE2 will be asserted. In both cases, logic circuit 120 will pass the external clock to circuit 140 via the CLK_EXT_FILT output of finite state machine circuit 12 (see Figure 3 ).

[0116] That is, Figure 7 : If at least N rising edges are detected separated by a distance Tck below Tckmin (CLK_EXT_GOOD asserted), then the logic circuit 120 filters the value on the pin MODSEL_CLKEXT (pin 10) to check for a valid external clock and validates the clock. Once validated, the clock is forwarded to the circuit 140 (CLK_EXT_FILT asserted) inside the finite state machine circuit 12, and the internal signal mode is set to MODE2 or confirmed at MODE2.

[0117] If, on the contrary (see Figure 8), the verification signal CLK_EXT_GOOD is reset during the time Tck when no rising edge is detected, and the logic circuit 120 enables the counter in the timer circuit 16 to check whether the signal level on the MODSEL_CLKEXT pin remains stable during the time T>Tmin.

[0118] If the signal on the MODSEL_CLKEXT pin remains stable (e.g. high) until the threshold set by Tmin, the internal mode signal remains at MODE2. On the other hand, if it is stable low for Tmin, the internal signal will switch to MODE1.

[0119] The logic circuit 120 thus continuously monitors changes in the signal on the input pin (MODSEL_CLKEXT—pin 10 ) to facilitate dynamic switching between the operating modes provided by the device (MODE1 to MODE2 and vice versa) and the management of a possible external clock.

[0120] That is, Figure 8 As illustrated in FIG. 1 : the logic circuit 120 continuously checks if the distance between two consecutive rising edges is shorter (lower) than Tck, and if the distance is longer (higher) than Tck, then the signal CLK_EXT_GOOD is reset. The logic circuit 120 starts counting T>Tmin to detect whether a stable level (high or low) exists on the input pin and changes the internal mode signal accordingly.

[0121] The example explained herein refers to a case where an external synchronization clock is considered for only one of the two modes (here, the mode indicated as MODE2).

[0122] Those skilled in the art will further appreciate that the present invention will also apply mutatis mutandis to the more general case of an external synchronization clock recognized by both MODE1 and MODE2.

[0123] In this case, the user may set a first desired mode with a first action, keeping the signal level stable for a time T>Tmin, and then providing a synchronized clock as described.

[0124] As repeatedly stated above, those skilled in the art will readily appreciate that specific references to certain signal edges being rising and falling edges, respectively, and certain signal levels being high and low levels, respectively, are merely exemplary, since the same type of operation can be obtained, for example, where the roles of the rising / falling edges and / or high / low levels are reversed.

[0125] As illustrated herein, a circuit (e.g., 100) may include a logic circuit (e.g., 120) coupled to an input node (e.g., 10) configured to receive an input signal (e.g., MODSEL_CLKEXT) exhibiting a transition between a first level and a second level. The logic circuit may include a state machine (e.g., 12) coupled to the input node. The state machine is configured to set the circuit (e.g., 100—including stage 140) to any one of a first operating mode (e.g., MODE1) and a second operating mode (e.g., MODE2) in response to an input signal having a first level or a second level, respectively (e.g., via a signal mode).

[0126] In addition, an edge detector block (eg, 14) is coupled to the input node. The edge detector block is configured to detect transitions (eg, rising and falling edges) between a first level and a second level in the input signal and send a corresponding transition signal (eg, mode_clkext_edge) to the state machine (12).

[0127] In addition, a timer block (e.g., 16) is coupled (e.g., enabled via signal mode_cnt_en) to the state machine and is configured to check whether the first level or the second level in the input signal is maintained for more than a threshold period (e.g., Tmin) starting from the transition detected by the edge detector block.

[0128] The state machine is configured to change an operating mode of the circuit from one of a first operating mode and a second operating mode to another operating mode in response to a check in the timer block indicating that a first level or a second level in the input signal has been maintained within a threshold period from a transition detected by the edge detector block.

[0129] The circuit as illustrated herein may include a processing circuit (e.g., a check circuit 18 and a counter circuit 20) coupled to an input node and a state machine. The processing circuit is configured to apply a signal received at the input node as a verification clock signal to the circuit in response to an input signal exhibiting a number N of transitions from one of a first level and a second level to the other level and a frequency of transitions between the first level and the second level exceeding a lower threshold.

[0130] One or more embodiments may therefore utilize edges that occur within Tmin and above a lower (eg, minimum) limit on the frequency of the edge in order to assert that the real clock is applied to the pin.

[0131] If the pin level changes where the frequency is below a threshold of the frequency of the external signal being identified as a clock signal (which threshold frequency can be selected and set to vary depending on the intended application or use case), the signal considered to be a clock will be erroneous because the signal will only correspond to the user in the process of selecting one mode over another.

[0132] In one or more embodiments, to evaluate the presence of an external clock, the time TCKmin elapsed between two consecutive rising edges of the signal is checked to be less than the time Tmin during which the signal remains stable after a level change causing a mode change.

[0133] Furthermore, even in the presence of an "acceptable" frequency value, checking the presence of a number N of transitions from one of the first level and the second level to the other level can provide a safety limit for asserting the presence of the clock signal over a (e.g., minimum) expected number of clock cycles N (where N=1 represents a limiting case of this masking) via masking.

[0134] The circuit as illustrated herein may be configured to apply the signal received at the input node as a verification clock signal to the circuit for only one of the first and second operation modes (eg, only for MODE2 and not for MODE1).

[0135] That is, the clock signal may (but does not necessarily have to) be passed to circuits for only one of the two modes, which in turn means that the clock signal identified at MODSEL_CLKEXT does not imply a change between MODE1 and MODE2.

[0136] In a circuit as illustrated, the state machine can therefore be configured to apply a signal received at an input node as a verification clock signal to the circuit, in combination with setting the circuit to or maintaining the circuit in only one of the first operating mode and the second operating mode.

[0137] That is, the state machine may be configured to change the operating mode of the circuit only if one of the two levels at MODSEL_CLKEXT is maintained for more than the threshold period Tmin from the transition detected by the edge detection circuit 14 .

[0138] For example, if the signal at MODSEL_CLKEXT remains high until the threshold indicated by Tmin, the internal mode signal is maintained at MODE2. If, on the contrary, the signal at MODSEL_CLKEXT is stable low within Tmin, the internal mode signal switches to MODE1, as shown in FIG. Figure 8 exemplified in .

[0139] That is, the state machine can be configured to change the operating mode of the circuit from one of the first operating mode and the second operating mode to another operating mode (e.g., from MODE1 to MODE2) only in response to a check in the timer block (e.g., 16) indicating that a first level (e.g., low) in the input signal has been maintained within a threshold period starting from a transition detected by the edge detector block.

[0140] Conversely, the state machine can be configured to maintain the operating mode of the circuit at one of the first operating mode and the second operating mode (e.g., maintain MODE2) in response to a check in the timer block indicating that the second level (e.g., high) in the input signal has been maintained within the threshold period starting from the transition detected by the edge detector block.

[0141] As illustrated herein, a method of operating a circuit (e.g., 100) having an output node (e.g., 10) may include setting the circuit to either a first operating mode (e.g., MODE1) or a second operating mode (e.g., MODE2) in response to an input signal having a first level or a second level, respectively (e.g., via a signal mode), the input node being configured to receive an input signal (e.g., MODSEL_CLKEXT) exhibiting a transition (e.g., a rising / falling edge) between the first level and the second level.

[0142] The method may also include detecting a transition between a first level and a second level in the input signal (e.g., at an edge detection circuit 14), and checking (e.g., at a timer circuit 16) whether the first level or the second level in the input signal is maintained for more than a threshold period (e.g., Tmin) starting from the transition detected (by the edge detection circuit 14).

[0143] The method may also include changing an operating mode of the circuit from one of the first operating mode and the second operating mode to another operating mode in response to the first level or the second level in the input signal being maintained for more than a threshold period from a transition detected by the edge detector block.

[0144] A method as illustrated herein may include applying a signal received at an input node as a verification clock signal to a circuit in response to an input signal exhibiting N number of transitions from one of a first level and a second level to the other level and a frequency of transitions between the first level and the second level exceeding a lower threshold.

[0145] Although the specification has been described in detail, it should be understood that various changes, substitutions and modifications can be made without departing from the spirit and scope of the present disclosure as defined in the appended claims. The same elements are represented by the same figure numbers in each figure. In addition, the scope of the present disclosure is not intended to be limited to the specific embodiments described herein, as those skilled in the art will easily understand according to the present disclosure that the processes, machines, manufactures, material compositions, components, methods or steps currently existing or subsequently generated can perform substantially the same functions as the corresponding embodiments described herein or achieve substantially the same results. Therefore, the appended claims are intended to include such processes, machines, manufactures, material compositions, components, methods or steps within their scope.

[0146] Accordingly, the specification and drawings are to be considered illustrative only of the present disclosure as defined by the appended claims, and any and all modifications, variations, combinations or equivalents falling within the scope of the present disclosure are contemplated to cover.

Claims

1. A circuit comprising: An input node configured to receive an input signal having a first level value and a second level value; as well as a logic circuit coupled to the input node and configured to receive the input signal, the logic circuit comprising: a finite state machine circuit configured to configure the operation mode of the circuit to a first operation mode or a second operation mode based on the input signal being at the first level value or the second level value, respectively; an edge detection circuit configured to detect a transition between the first level value and the second level value and to transmit a corresponding transition signal to the finite state machine circuit based on the transition, and A timer circuit is configured to determine whether the first level value or the second level value is maintained for more than a threshold period, the threshold period starting from the transition detected by the edge detection circuit, and wherein the finite state machine circuit is configured to change the operating mode of the circuit based on the timer circuit determining that the first level value or the second level value has been maintained for more than the threshold period.

2. The circuit of claim 1 , further comprising a processing circuit, wherein the finite state machine circuit is configured to associate the input signal as a verification clock signal based on: determining, by the processing circuit, that the input signal includes a number N of transitions between the first level value and the second level value, and determining, by the processing circuit, that a frequency of transitions between the first level value and the second level value is greater than a lower threshold.

3. The circuit of claim 2, wherein the finite state machine circuit is configured to: associating the input signal as a verification clock signal, and The operation mode of the circuit is set to only one of the first operation mode or the second operation mode, or the circuit is maintained at only one of the first operation mode or the second operation mode. 4 . The circuit of claim 2 , wherein the circuit is configured to associate the input signal as a validation clock signal for only one of the first operating mode or the second operating mode.

5. The circuit of claim 4 , wherein the finite state machine circuit is configured to: associating the input signal as a verification clock signal, and The operation mode is set to or maintained at only one of the first operation mode or the second operation mode.

6. The circuit of claim 1 , wherein the finite state machine circuit is configured to change the operation mode of the circuit based on the timer circuit determining that the first level value or the second level value has been maintained for more than the threshold period of time, comprising: changing the operating mode of the circuit based on the timer circuit determining that the first level value has been maintained for more than the threshold period; as well as The operating mode of the circuit is maintained based on the timer circuit determining that the second level value has been maintained for more than the threshold period of time.

7. The circuit according to claim 1, further comprising: a counter circuit configured to determine that the input signal includes a number N of transitions between the first level value and the second level value; as well as A checking circuit is configured to determine that a frequency of transitions between the first level value and the second level value is greater than a lower threshold.

8. A method of operating a circuit, the method comprising: The input node is configured to receive an input signal having a first level value and a second level value; setting the operation mode of the circuit to a first operation mode or a second operation mode based on the input signal being at the first level value or the second level value, respectively; detecting a transition between the first level value and the second level value; determining whether the first level value or the second level value is maintained for more than a threshold period; as well as The operating mode is changed based on determining that the first level value or the second level value has been maintained for more than the threshold period of time.

9. The method according to claim 8, further comprising: The input signal is associated as a validation clock signal based on determining that the input signal includes a number N of transitions between the first level value and the second level value and determining that a frequency of transitions between the first level value and the second level value is greater than a lower threshold. 10 . The method of claim 9 , further comprising setting the operation mode to or maintaining the operation mode at only one of the first operation mode or the second operation mode.

11. The method of claim 9, further comprising associating the input signal as a validation clock signal for only one of the first operating mode or the second operating mode.

12. The method according to claim 11, further comprising: determining a time difference between two consecutive rising edges of the input signal; as well as The verification clock signal is reset to be associated with the input signal based on determining that the time difference is greater than a threshold.

13. The method of claim 11, further comprising setting the operation mode to or maintaining the operation mode at only one of the first operation mode or the second operation mode.

14. The method of claim 8, changing the operation mode based on determining that the first level value or the second level value has been maintained for more than the threshold period comprises: changing the operating mode based on determining that the first level value has been maintained for more than the threshold period of time; as well as The operating mode is maintained based on determining that the second level value has been maintained for more than the threshold period of time.

15. A system comprising: A clock circuit configured to generate a signal having a first level value and a second level value; as well as A circuit coupled to the clock circuit and configured to receive the signal at an input of the circuit, the circuit comprising a logic circuit configured to receive the signal, the logic circuit comprising: a finite state machine circuit configured to configure the operation mode of the circuit to a first operation mode or a second operation mode based on the signal being at the first level value or the second level value, respectively; an edge detection circuit configured to detect a transition between the first level value and the second level value and to transmit a corresponding transition signal to the finite state machine circuit based on the transition, and A timer circuit is configured to determine whether the first level value or the second level value is maintained for more than a threshold period, the threshold period starting from the transition detected by the edge detection circuit, and wherein the finite state machine circuit is configured to change the operating mode of the circuit based on the timer circuit determining that the first level value or the second level value has been maintained for more than the threshold period.

16. The system of claim 15 , wherein the logic circuit further comprises a processing circuit, wherein the finite state machine circuit is configured to associate the signal as a verification clock signal based on: determining by the processing circuit that the signal includes a number N of transitions between the first level value and the second level value, and determining by the processing circuit that a frequency of transitions between the first level value and the second level value is greater than a lower threshold.

17. The system of claim 16, wherein the finite state machine circuit is configured to: associating the signal as a verification clock signal, and The operation mode of the circuit is set to only one of the first operation mode or the second operation mode, or the circuit is maintained at only one of the first operation mode or the second operation mode.

18. The system of claim 16, wherein the circuit is configured to associate the signal as a validation clock signal for only one of the first operating mode or the second operating mode.

19. The system of claim 15, wherein the finite state machine circuit is configured to change the operation mode of the circuit based on the timer circuit determining that the first level value or the second level value has been maintained for more than the threshold period of time comprises: changing the operating mode of the circuit based on the timer circuit determining that the first level value has been maintained for a period exceeding the threshold; as well as The operating mode of the circuit is maintained based on the timer circuit determining that the second level value has been maintained for more than the threshold period of time.

20. The system of claim 15, wherein the logic circuit further comprises: a counter circuit configured to determine that the signal includes a number N of transitions between the first level value and the second level value; as well as A checking circuit is configured to determine that a frequency of transitions between the first level value and the second level value is greater than a lower threshold.

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