Output circuit with multiple level output and its comparator circuit

Abstract

The application discloses an output circuit with multi-level output and a comparison circuit thereof. The output circuit includes a comparison circuit, a voltage conversion circuit and a signal output circuit. The comparison circuit detects a working mode based on a first power voltage and a second power voltage and generates a first control signal. The voltage conversion circuit adjusts a level of an output voltage from a low dropout regulator according to the first control signal to generate a first voltage, and generates a second voltage according to the first control signal and the first voltage. The signal output circuit adjusts a level of a digital signal according to the first voltage, the second voltage and the first power voltage to generate a digital output signal corresponding to the working mode.

Description

Technical Field

[0001] This application relates to the field of output circuit technology, and more specifically to a comparison circuit for an output circuit capable of generating outputs at different levels and its detection operating mode. Background Technology

[0002] In some transmission interfaces, different power supply voltage levels are required to generate signal levels for different operating modes, enabling signal exchange with different devices or circuits. In existing technologies, the operating mode of the circuitry in the transmission interface is configured via input commands, rather than automatically switching operating modes based on different power supply voltage levels. Furthermore, to ensure reliability and operational stability, strict limitations are placed on the control signals used to configure the operating mode and the switching sequence of multiple power supply voltages in these technologies. Summary of the Invention

[0003] In some embodiments, one of the objectives of this application is to provide an output circuit with multi-bit quasi-output and a comparison circuit that can detect operating modes based on power supply voltage, in order to improve the shortcomings of the prior art.

[0004] In some embodiments, the output circuit includes a comparator circuit, a voltage conversion circuit, and a signal output circuit. The comparator circuit detects an operating mode based on a first supply voltage and a second supply voltage and generates a first control signal. The voltage conversion circuit adjusts the level of an output voltage from a low-dropout regulator according to the first control signal to generate a first voltage, and generates a second voltage according to the first control signal and the first voltage. The signal output circuit adjusts the level of a digital signal according to the first voltage, the second voltage, and the first supply voltage to generate a digital output signal corresponding to the operating mode.

[0005] In some embodiments, a comparator circuit is used to detect a first power supply voltage and a second power supply voltage to detect an operating mode, and the comparator circuit includes a first transistor, a pull-down resistor, a comparator, a filter circuit, and a second transistor. The first transistor generates a first control signal based on a first signal, wherein the first control signal is used to indicate the operating mode. The pull-down resistor is coupled between the first transistor and ground. The comparator compares a level of a first node with a preset voltage to generate the first signal, wherein the preset voltage is generated by dividing the first power supply voltage. The second transistor receives the second power supply voltage via the filter circuit and selectively turns on according to a level of a control node to transmit the second power supply voltage to the first node.

[0006] In some embodiments, the output circuit includes a voltage conversion circuit, a level adjustment circuit, and multiple control circuits. The voltage conversion circuit adjusts the level of an output voltage from a low-dropout regulator according to a first control signal to generate a first voltage, and generates a second voltage according to the first control signal and the first voltage. The level adjustment circuit adjusts the level of a digital signal according to the first voltage, the second voltage, the first bias voltage, the second bias voltage, and the first power supply voltage to generate a digital output signal corresponding to the operating mode. The multiple control circuits output the digital output signal and the second voltage, whichever has the lower level, as the second bias voltage, and output the digital output signal and the first voltage, whichever has the higher level, as the first bias voltage.

[0007] In some embodiments, the output circuit and the comparator circuit can detect the current operating mode based on the change of power supply voltage and improve the operational reliability of the system during power-up. Furthermore, an isolation signal mechanism can be added to the signal output circuit to reduce the impact of signal switching.

[0008] The features, implementation, and effects of this application are described in detail below with reference to the accompanying drawings, using preferred embodiments. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 A schematic diagram of an output circuit is shown according to some embodiments of this application;

[0011] Figure 2A Drawings based on some embodiments of this application Figure 1 A schematic diagram of the comparator circuit in the diagram;

[0012] Figure 2B Drawings based on some embodiments of this application Figure 1 A schematic diagram of the comparator circuit in the diagram;

[0013] Figure 3 Drawings based on some embodiments of this application Figure 1 A schematic diagram of the voltage conversion circuit in the diagram;

[0014] Figure 4A Drawings based on some embodiments of this application Figure 1 A schematic diagram of the signal output circuit; and

[0015] Figure 4BDrawings based on some embodiments of this application Figure 1 A schematic diagram of the signal output circuit. Detailed Implementation

[0016] All terms used herein have their common meanings. The definitions of the terms used in commonly used dictionaries, and any examples of the use of any term discussed herein, are merely illustrative and should not be construed as limiting the scope or meaning of this application. Similarly, this application is not limited to the various embodiments shown in this specification.

[0017] As used herein, “coupled” or “connected” can refer to two or more components making direct physical or electrical contact with each other, or indirectly making direct physical or electrical contact with each other, or to two or more components operating or acting on each other. As used herein, the term “circuit” can be a device consisting of at least one transistor and / or at least one active or passive component connected in a certain manner to process signals.

[0018] Figure 1 A schematic diagram of an output circuit 100 is shown according to some embodiments of this application. In some embodiments, the output circuit 100 can be applied to a general purpose input / output (GPIO) interface to switch operating modes according to different power supply voltages and generate digital signals with appropriate bit levels.

[0019] Output circuit 100 includes comparator circuit 120, voltage conversion circuit 140, and signal output circuit 160. Comparator circuit 120 can detect the operating mode of output circuit 100 based on power supply voltages VDD1 and VDD2 and generate control signal SC1. In some embodiments, the level of power supply voltage VDD1 can be a first level (e.g., 1.8 volts) or a second level (e.g., 3.3 volts) in different operating modes. Comparator circuit 120 can compare preset voltage VP with power supply voltage VDD2 to generate control signal SC1, wherein preset voltage VP is the voltage generated by dividing power supply voltage VDD1 by voltage divider circuit 100A. For example, preset voltage VP can be (but is not limited to) half of power supply voltage VDD1, i.e., VP = 0.5 × VDD1.

[0020] The voltage conversion circuit 140 adjusts the level of the output voltage VO from the low-dropout regulator (LDO) 100B according to the control signal SC1 to generate voltage V1, and generates voltage V2 according to the control signal SC1 and voltage V1. In some embodiments, the output voltage VO may be (but is not limited to) half of the power supply voltage VDD1, i.e., VO = 0.5 × VDD1. In some embodiments, the voltage conversion circuit 140 can generate a control signal SC2 according to the control signal SC1, wherein the control signals SC1 and SC2 are logically complementary, i.e., when the control signal SC1 is a logic value of 1, the control signal SC2 is a logic value of 0, and vice versa. In some embodiments, the voltage divider circuit 100A and the low-dropout regulator 100B may be integrated into the output circuit 100. In other embodiments, the voltage divider circuit 100A and the low-dropout regulator 100B may be existing circuits in the system.

[0021] The signal output circuit 160 adjusts the level of the digital signal SD based on voltages V1, V2, and the power supply voltage VDD1 to generate a digital output signal SDO corresponding to the current operating mode. In some embodiments, the digital signal SD is a signal from other digital circuits in the system, while the digital output signal SDO is equivalent to a signal transmitted via a GPIO interface. In some embodiments, the signal output circuit 160 may further generate the digital output signal SDO based on multiple bias voltages to reduce the interference of switching of the digital output signal SDO on voltage V1. The operation described here will be described later. Figure 4B Detailed explanation.

[0022] Figure 2A Drawings based on some embodiments of this application Figure 1 A schematic diagram of the comparator circuit 120 is shown. The comparator circuit 120 includes a transistor PM1, a pull-down resistor R1, a comparator 220, a filter circuit 240, and a transistor PM2. Transistor PM1 is selectively turned on according to signal S1 to output the power supply voltage VDD1 as a control signal SC1. The pull-down resistor R1 is coupled between transistor PM1 and ground. Specifically, the first terminal (e.g., the source) of transistor PM1 receives the power supply voltage VDD1, the second terminal (e.g., the drain) of transistor PM1 outputs the control signal SC1, and the control terminal (e.g., the gate) of transistor PM1 receives signal S1. The pull-down resistor R1 is coupled between the second terminal of transistor PM1 and ground.

[0023] Comparator 220 compares the level of node N1 with a preset voltage VP to generate signal S1. In some embodiments, comparator 220 includes transistor PM3 and transistor PM4. A first terminal of transistor PM3 is coupled to node N1, a second terminal of transistor PM3 generates signal S1, and a control terminal of transistor PM3 receives the preset voltage VP. A first terminal of transistor PM4 is coupled to the control terminal of transistor PM3 and receives the preset voltage VP, a second terminal of transistor PM4 is coupled to the second terminal of transistor PM3, and a control terminal of transistor PM4 is coupled to node N1 and the first terminal of transistor PM3. With this configuration, comparator 220 can output the higher of the level of node N1 and the preset voltage VP as signal S1. For example, if the level of node N1 is higher than the preset voltage VP, transistor PM3 is turned on and transistor PM4 is turned off to output the voltage on node N1 as signal S1. Alternatively, if the preset voltage VP is higher than the level of node N1, transistor PM3 is turned off and transistor PM4 is turned on to output the preset voltage VP as signal S1.

[0024] Transistor PM2 receives power supply voltage VDD2 via filter circuit 240 and selectively turns on according to the level of control node NC to transmit the received power supply voltage VDD2 to node N1. In other words, when transistor PM2 is on, the level of node N1 corresponds to the power supply voltage VDD2. In some embodiments, filter circuit 240 can filter out noise on power supply voltage VDD2. Specifically, a first terminal of transistor PM2 is coupled to filter circuit 240, a second terminal of transistor PM2 is coupled to node N1, and a control terminal of transistor PM2 is coupled to control node NC. In some embodiments, the preset state of transistor PM2 is on (i.e., when not powered on, control node NC is at a low level).

[0025] In some embodiments, the comparator circuit 120 can determine the current operating mode based on the power supply voltages VDD1 and VDD2. For example, the correspondence between power supply voltages VDD1 and VDD2, the operating mode, and the control signal SC1 can be shown in the following table:

[0026] Table 1. Correspondence between power supply voltage, operating mode, and control signal

[0027] Work mode VDD1 VDD2 SC1 First Mode 1.8 volts 1.8 volts 0 volts Second Mode 3.3 volts 1.8 volts 3.3 volts

[0028] As shown in the table above, in the first mode, both power supply voltages VDD1 and VDD2 are set to 1.8 volts. Since transistor PM2 is preset to be on, the level of node N1 is 1.8 volts. In response to the level of node N1, transistor PM3 is turned on to output the voltage at node N1 as signal S1. Because the level of signal S1 is close to the power supply voltage VDD1 (e.g., both are 1.8 volts), transistor PM1 is not turned on. Under this condition, pull-down resistor R1 pulls the level of the second terminal of transistor PM1 low to ground to generate a control signal SC1 with a low level (i.e., 0 volts). Alternatively, in the second mode, power supply voltage VDD1 is set to 3.3 volts and power supply voltage VDD2 is set to 1.8 volts. Under this condition, transistor PM3 is turned on to output the voltage at node N1 as signal S1. Since the level of signal S1 (e.g., 1.8 volts) is lower than the power supply voltage VDD1, transistor PM1 is turned on to output a control signal SC1 with a high level (i.e., 3.3 volts). In other words, comparator circuit 120 can detect the current operating mode based on the change in power supply voltage VDD1 and output a control signal SC1 with the corresponding level accordingly.

[0029] In some applications, the comparator circuit 120 may operate based on a configuration signal SP output by a register circuit (not shown) in the system to determine the current operating mode. For example, the configuration signal SP may be input to the control node NC after level conversion. Generally, the register circuit outputs the configuration signal SP only after the system core circuit is powered on. In these applications, the comparator circuit 120 can determine the current operating mode based on changes in the power supply voltage VDD1 before the core circuit is powered on, and the operation of the comparator circuit 120 will not conflict with the configuration signal SP. In some embodiments, the correspondence between the configuration signal SP, power supply voltage VDD1, power supply voltage VDD2, operating mode, and control signal SC1 may be shown in the following table:

[0030] Table 2. Correspondence between configuration signals, power supply voltage, operating mode, and control signals.

[0031] Work mode VDD1 VDD2 SC1 SP First Mode 1.8 volts 1.8 volts 0 volts Logical value 1 Second Mode 3.3 volts 1.8 volts 3.3 volts Logical value 0 Unexpected Mode 1 1.8 volts 1.8 volts 1.8 volts Logical value 0 Unexpected Mode 2 3.3 volts 1.8 volts 3.3 volts Logical value 1

[0032] Since transistor PM2 is preset to be on during power-up, the level of node N1 will rise to the power supply voltage VDD2 after power-on. Therefore, whether transistor PM2 is turned off upon receiving a configuration signal SP with a logic value of 1, or remains on upon receiving a configuration signal SP with a logic value of 0, the operation of comparator circuit 120 remains the same as before. Accordingly, it should be understood that the operation of comparator circuit 120 will not conflict with the existing mode configuration signal (i.e., configuration signal SP).

[0033] Furthermore, in some unexpected situations, the configuration signal SP may malfunction, but the comparator circuit 120 still ensures the reliability of the power-on process. For example, in unexpected mode 1 in the table above, both power supply voltages VDD1 and VDD2 are set to 1.8 volts, but the configuration signal SP is incorrectly set to the logic value 0. Under this condition, the level of the control signal SC1 is 1.8 volts. If in subsequent operations the power supply voltage VDD1 is corrected to 3.3 volts (which correctly corresponds to the level of the configuration signal SP with a logic value of 0), the level of the control signal SC1 can be restored to 3.3 volts. Alternatively, in unexpected mode 2, the power supply voltage VDD1 is set to 3.3 volts and the power supply voltage VDD2 is set to 1.8 volts, but the configuration signal SP is incorrectly set to the logic value 1. Under this condition, the level of the control signal SC1 is 3.3 volts. If the power supply voltage VDD1 is corrected to 1.8 volts in subsequent operations (which correctly corresponds to the level of the configuration signal SP with a logic value of 1), the level of the control signal SC1 can then be restored to 1.8 volts.

[0034] In some related technologies, the operating mode of a circuit is switched by a system configuration signal, and the order in which the configuration signal and the power supply voltage are powered on is subject to certain restrictions during the switching process. Compared to the aforementioned related technologies, the comparator circuit 120 can autonomously determine its operating mode by detecting changes in power supply voltages VDD1 and VDD2, and can operate in conjunction with the system's control signal (i.e., the configuration signal VP), with no particular restrictions on the changes in the configuration signal VP relative to power supply voltages VDD1 and VDD2. In some optional embodiments, the comparator circuit 120 may also include an inverter (not shown), which can be powered by power supply voltage VDD2 and generates a voltage according to control signal SC1. Figure 1 The control signal SC2 in the middle.

[0035] Figure 2B Drawings based on some embodiments of this application Figure 1 A schematic diagram of the comparator circuit 120 in the diagram. Compared to Figure 2A In this example, the comparator circuit 120 further includes a transistor NM1. A first terminal (e.g., a drain) of transistor NM1 is coupled to node N1, a second terminal (e.g., a source) of transistor NM1 is coupled to ground, and a control terminal (e.g., a gate) of transistor NM1 is coupled to control node NC and receives a power-on control signal SPC. Transistor NM1 can be selectively turned on according to the power-on control signal SPC, pulling the level of node N1 down to ground. In some embodiments, the power-on control signal SPC may be a signal used in a GPIO interface circuit to indicate that power supply voltages VDD1 and VDD2 are powered on.

[0036] By configuring transistor NM1, the stability of the power-on process can be further increased. For example, when the power supply voltage VDD1 instantly switches from 0 volts to 3.3 volts (or 1.8 volts), the power-on control signal SPC has a logic value of 1. Under this condition, transistor NM1 turns on, pulling the level of node N1 down to ground, and transistor PM4 turns on, outputting a preset voltage VP as signal S1 to turn on transistor PM1. Thus, during the instantaneous power-on process, the level of control signal SC1 can be maintained at the same level as the power supply voltage VDD1. After the levels of power supply voltages VDD1 and VDD2 stabilize, the power-on control signal SPC is deactivated and has a logic value of 0. At this time, the comparator circuit 120 can determine the operating mode based on the power supply voltages VDD1 and VDD2.

[0037] Figure 3 Drawings based on some embodiments of this application Figure 1 A schematic diagram of voltage conversion circuit 140 is shown. Voltage conversion circuit 140 includes transistor PM5, transmission circuit 320, and buffer circuit 340. A first terminal of transistor PM5 receives a power supply voltage VDD1, a second terminal of transistor PM5 is coupled to the output terminal of low dropout regulator 100B (which generates output voltage VO), and a control terminal of transistor PM5 receives a control signal SC1. Transistor PM5 is selectively turned on according to control signal SC1 to pull up the level of output voltage VO to the power supply voltage VDD1 to generate voltage V1. In some embodiments, transistor PM5 has a larger size to have a stronger pull-up capability. Transmission circuit 320 generates control signal SC2 according to control signal SC1. In some embodiments, transmission circuit 320 may be implemented by a transmission gate and an inverter coupled in series. Buffer circuit 340 is powered via voltage V1 and generates voltage V2 according to control signal SC2. For example, buffer circuit 340 includes an even number of inverters powered via voltage V1 to generate voltage V2 according to control signal SC2.

[0038] In some embodiments, the aforementioned first mode can be a bypass mode, in which transistor PM5 is turned on, such that voltage V1 is maintained at the same level as the power supply voltage VDD1 (e.g., 1.8 volts) and is also the same as voltage V2. In some embodiments, the aforementioned second mode can be a low-dropout regulator mode, in which transistor PM5 is not turned on, such that voltage V1 is the same as the output voltage VO and different from voltage V2 (e.g., 0 volts). This satisfies the multi-voltage level requirements of the GPIO interface circuit.

[0039] Figure 4A Drawings based on some embodiments of this application Figure 1A schematic diagram of the signal output circuit 160 is shown. The signal output circuit 160 includes a level conversion circuit 420, a level conversion circuit 440, multiple transistors PM6-PM7, and multiple transistors NM2-NM3. The level conversion circuit 420 adjusts the level of the digital signal SD to generate signal S11. The level conversion circuit 440 adjusts the level of the digital signal SD to generate signal S12. In some embodiments, in a second mode, the level conversion circuits 420 and 440 can adjust the high level of the digital signal SD to 1.8 volts, and further adjust the level from 1.8 volts to 3.3 volts in the second mode to generate signals S11 and S12, respectively. Transistor PM6 receives the power supply voltage VDD1 and is selectively turned on according to signal S11. Transistor PM7 is coupled between output node NO and transistor PM6 and biased via voltage V2 to output the digital output signal SDO via output node NO. Transistor NM2 is coupled to output node NO and biased via voltage V1. Transistor NM3 is coupled between transistor NM2 and ground, and is selectively turned on according to signal S12.

[0040] In detail, the first terminal of transistor PM6 receives the power supply voltage VDD1, the second terminal of transistor PM6 is coupled to the first terminal of transistor PM7, and the control terminal of transistor PM6 is coupled to the level conversion circuit 420 to receive signal S11. The second terminal of transistor PM7 is coupled to output node NO and generates a digital output signal SDO, and the control terminal of transistor PM7 receives voltage V2. The first terminal of transistor NM2 is coupled to output node NO, the second terminal of transistor NM2 is coupled to the first terminal of transistor NM3, and the control terminal of transistor NM2 receives voltage V1. The second terminal of transistor NM3 is coupled to ground, and the control terminal of transistor NM3 is coupled to the level conversion circuit 440 to receive signal S12. With the above configuration, multiple transistors PM6, PM7, NM2, and NM3, as well as multiple level conversion circuits 420 and 440, can operate as a level adjustment circuit, which can adjust the level of the digital signal SD to the level corresponding to the current operating mode, and thereby generate the digital output signal SDO.

[0041] Figure 4B Drawings based on some embodiments of this application Figure 1 A schematic diagram of the signal output circuit 160. Compared to Figure 4A In this example, the signal output circuit 160 is further used to generate bias voltages VB1 and VB2 according to the digital output signal SDO, and to use the bias voltages VB1 and VB2 to bias multiple transistors (e.g., transistor PM8 and transistor NM4) directly connected to the output node NO, so as to reduce the impact of the digital output signal SDO on the low dropout regulator 100B.

[0042] For example, compared to Figure 4A , Figure 4B The signal output circuit 160 also includes transistor PM8, transistor NM4, control circuit 460, and control circuit 480. Transistor PM8 is coupled between transistor PM7 and output node NO and is turned on according to bias voltage VB2. Transistor NM4 is coupled between output node NO and transistor NM2 and is turned on according to bias voltage VB1. Specifically, the first terminal of transistor PM8 is coupled to the second terminal of transistor PM7, the second terminal of transistor PM8 is coupled to output node NO, and the control terminal of transistor PM8 receives bias voltage VB2. The first terminal of transistor NM4 is coupled to output node NO, the second terminal of transistor NM4 is coupled to the first terminal of transistor NM2, and the control terminal of transistor NM4 receives bias voltage VB1.

[0043] Control circuit 460 outputs the lower of the digital output signal SDO and voltage V2 as a bias voltage VB2, and selectively adjusts the level of bias voltage VB2 to voltage V2 according to control signal SC2. Control circuit 460 includes multiple transistors NM5 to NM7. Transistors NM5 and NM6 operate as comparators (similar to...). Figure 2A The comparator 220 compares the digital output signal SDO with voltage V2 and outputs the lower of the two as the bias voltage VB2. Transistor NM7 is selectively turned on according to control signal SC2 to output voltage V2 as the bias voltage VB2. Similarly, control circuit 480 outputs the higher of the digital output signal SDO and voltage V1 as the bias voltage VB1, and selectively adjusts the level of bias voltage VB1 to voltage V1 according to control signal SC1. Control circuit 480 includes multiple transistors PM9 to PM11. Transistors PM9 and PM10 operate as comparators (similar to...). Figure 2A The comparator 220 compares the digital output signal SDO with the voltage V1 and outputs the one with the higher level as the bias voltage VB1. Transistor PM11 is selectively turned on according to the control signal SC1 to output the voltage V1 as the bias voltage VB1. In this example, multiple transistors PM6-PM8 and NM2-NM4, as well as multiple level conversion circuits 420 and 440, can operate as the aforementioned level adjustment circuit to generate the digital output signal SDO.

[0044] exist Figure 4AIn the example, transistors PM7 and NM2 are directly connected to the output node NO. If the switching frequency of the digital output signal SDO is high, the digital output signal SDO may be coupled to multiple control terminals of transistors PM7 and NM2 via parasitic capacitance, thereby affecting the output voltage VO generated by the low-dropout regulator 100B. To improve this problem, transistors PM8 and NM3 can be used to further isolate the coupling of the digital output signal SDO, making the output voltage VO more stable. Furthermore, in the first mode, transistor PM11 is turned on with the transmission voltage V1 as the bias voltage VB1. In the second mode, the bias voltage VB1 is the lower of the digital output signal SDO and voltage V1. This allows transistor PM8 to conduct more fully. Similarly, in the first mode, transistor NM7 is turned on with the transmission voltage V2 as the bias voltage VB2. In the second mode, the bias voltage VB2 is the higher of the digital output signal SDO and voltage V1, allowing transistor NM4 to conduct more fully.

[0045] In the above embodiments, transistors NM1 to NM7 are N-type transistors, and transistors PM1 to PM11 are P-type transistors. Each of these transistors can be implemented using a metal-oxide-semiconductor field-effect transistor (MOSFET), but this application is not limited thereto. Transistors of various types or conduction patterns capable of similar operation are all within the scope of this application. Furthermore, the voltage values ​​mentioned in the above embodiments are for illustrative purposes only, and this application is not limited to the voltage values ​​mentioned above.

[0046] In summary, the output circuit and comparator circuit in some embodiments of this application can detect the current operating mode based on the change of power supply voltage and improve the operational reliability of the system during power-on. Furthermore, an isolation signal mechanism can be added to the signal output circuit to reduce the impact of signal switching.

[0047] Although the embodiments of this application are described above, these embodiments are not intended to limit this application. Those skilled in the art can make changes to the technical features of this application based on the express or implied content of this application. All such changes may fall within the scope of patent protection sought by this application. In other words, the scope of patent protection of this application shall be determined by the scope of the patent application as defined in this specification.

[0048] Symbol explanation:

[0049] 100: Output circuit;

[0050] 100A: Voltage divider circuit;

[0051] 100B: Low dropout voltage regulator;

[0052] 120: Comparator circuit;

[0053] 140: Voltage conversion circuit;

[0054] 160: Signal output circuit;

[0055] 220: Comparator;

[0056] 240: Filtering circuit;

[0057] 320: Transmission circuit;

[0058] 340: Buffer circuit;

[0059] 420, 440: Level conversion circuit;

[0060] 460, 480: Control circuit;

[0061] N1: Node;

[0062] NC: Control Node;

[0063] NM1~NM7: Transistors;

[0064] NO: Output node;

[0065] PM1~PM11: Transistors;

[0066] R1: Pull-down resistor;

[0067] S1, S11, S12: Signals;

[0068] SC1, SC2: Control signals;

[0069] SD: Digital signal;

[0070] SDO: Digital Output Signal;

[0071] SP: Configuration signal;

[0072] SPC: Power-on control signal;

[0073] V1, V2: Voltage;

[0074] VB1, VB2: Bias voltages;

[0075] VDD1, VDD2: Power supply voltage;

[0076] VO: Output voltage;

[0077] VP: Preset voltage.

Claims

1. An output circuit, characterized in that, include: A comparator circuit detects an operating mode based on a first power supply voltage and a second power supply voltage and generates a first control signal; A voltage conversion circuit adjusts the level of an output voltage from a low-dropout regulator according to the first control signal to generate a first voltage, and generates a second voltage according to the first control signal and the first voltage. as well as A signal output circuit adjusts the level of a digital signal according to the first voltage, the second voltage, and the first power supply voltage to generate a digital output signal corresponding to the operating mode; the signal output circuit outputs the digital output signal via an output node, and further generates a first bias voltage and a second bias voltage according to the digital output signal, so as to bias a plurality of transistors directly connected to the output node in the signal output circuit using the first bias voltage and the second bias voltage.

2. The output circuit as described in claim 1, characterized in that, The comparison circuit includes: A filter circuit; A second transistor receives the second power supply voltage via the filter circuit and is selectively turned on according to the level of a control node to transmit the second power supply voltage to a first node. A comparator compares the level of the first node with a preset voltage to generate a first signal, wherein the preset voltage is generated by dividing the first power supply voltage. A first transistor, selectively turned on according to the first signal to output the first power supply voltage as the first control signal; and A pull-down resistor is connected between the first transistor and ground.

3. The output circuit as described in claim 2, characterized in that, The comparator outputs the first signal, whichever has the higher level between the first node's output level and the preset voltage.

4. The output circuit as described in claim 2, characterized in that, The comparator includes: A third transistor, wherein a first terminal of the third transistor is coupled to the first node, a second terminal of the third transistor generates the first signal, and a control terminal of the third transistor receives the preset voltage; and A fourth transistor, wherein a first terminal of the fourth transistor receives the preset voltage, a second terminal of the fourth transistor is coupled to a second terminal of the third transistor, and a control terminal of the fourth transistor is coupled to the first node.

5. The output circuit as described in claim 2, characterized in that, The comparison circuit further includes: A third transistor is selectively turned on according to a power-on control signal, pulling the level of the control node down to ground.

6. The output circuit as described in claim 1, characterized in that, The voltage conversion circuit includes: A transistor is selectively turned on according to the first control signal to pull up the level of the output voltage to the first power supply voltage to generate the first voltage; A transmission circuit generates a second control signal based on the first control signal, wherein the second control signal is logically complementary to the first control signal; and A buffer circuit is powered by the first voltage and generates the second voltage according to the second control signal.

7. The output circuit as described in claim 1, characterized in that, The signal output circuit includes: A first level conversion circuit adjusts the level of the digital signal to generate a first signal; A second level conversion circuit adjusts the level of the digital signal to generate a second signal; A first transistor receives the first power supply voltage and is selectively turned on according to the first signal; A second transistor, biased by the second voltage, has a first terminal coupled to the first transistor and a second terminal coupled to an output node to output the digital output signal; A third transistor, biased by the first voltage, and coupled to the output node; and A fourth transistor is selectively turned on according to the second signal, a first terminal of the fourth transistor is coupled to the third transistor, and a second terminal of the fourth transistor is coupled to ground.

8. The output circuit as described in claim 7, characterized in that, The signal output circuit also includes: A fifth transistor, coupled between the second transistor and the output node, and turned on via a first bias voltage; and A sixth transistor is coupled between the output node and the third transistor and is turned on via a second bias voltage.

9. The output circuit as described in claim 8, characterized in that, The voltage conversion circuit further generates a second control signal based on the first control signal, and the signal output circuit further includes: A first control circuit outputs the lower of the digital output signal and the second voltage as the first bias voltage, and selectively adjusts the level of the first bias voltage to the second voltage according to the second control signal; and A second control circuit outputs the digital output signal and the first voltage, whichever has the higher level, as the second bias voltage, and selectively adjusts the level of the second bias voltage to the first voltage according to the first control signal.

10. The output circuit as described in claim 9, characterized in that, The first control circuit includes: A comparator outputs the digital output signal and the second voltage having the lower level, which constitutes the first bias voltage; and A seventh transistor is selectively turned on according to the second control signal to transmit the second voltage as the first bias voltage.

11. A comparator circuit, characterized in that, The comparison circuit is used to detect an operating mode based on a first power supply voltage and a second power supply voltage, and the comparison circuit includes: A filter circuit; A second transistor receives the second power supply voltage via the filter circuit and is selectively turned on according to the level of a control node to transmit the second power supply voltage to a first node. A comparator compares the level of the first node with a preset voltage to generate a first signal, wherein the preset voltage is generated by dividing the first power supply voltage. A first transistor, selectively turned on according to the first signal to output the first power supply voltage as a first control signal; and A pull-down resistor is connected between the first transistor and ground; A third transistor is selectively turned on according to a power-on control signal, pulling the level of the control node down to ground.

12. An output circuit, characterized in that, include: A voltage conversion circuit adjusts the level of an output voltage from a low-dropout regulator according to a first control signal to generate a first voltage, and generates a second voltage according to the first control signal and the first voltage. A level adjustment circuit adjusts the level of a digital signal based on the first voltage, the second voltage, a first bias voltage, a second bias voltage, and a first power supply voltage to generate a digital output signal. as well as Multiple control circuits output the digital output signal and the second voltage, whichever has a lower level, as the second bias voltage, and output the digital output signal and the first voltage, which has a higher level, as the first bias voltage.

13. The output circuit as described in claim 12, characterized in that, The level adjustment circuit includes: A first level conversion circuit adjusts the level of the digital signal to generate a first signal; A second level conversion circuit adjusts the level of the digital signal to generate a second signal; A first transistor receives the first power supply voltage and is selectively turned on according to the first signal; A second transistor, biased by the second voltage, wherein a first terminal of one of the second transistors is coupled to the first transistor; A third transistor is coupled between the second transistor and an output node and is turned on via the first bias voltage, the output node being used to output the digital output signal; A fourth transistor is coupled between the output node and a fifth transistor and is turned on via a second bias voltage; The fifth transistor is biased via the first voltage; and A sixth transistor is coupled between the fifth transistor and ground, and is selectively turned on according to the second signal.

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