A cross-clock domain signal synchronization circuit

Abstract

The present invention discloses a cross-clock-domain signal synchronization circuit, which specifically includes: a high-level pulse synchronization module for outputting a single-pulse high-level synchronization signal that is synchronously converted from the first clock domain to the second clock domain; a low-level pulse synchronization module for outputting a single-pulse low-level synchronization signal that is synchronously converted from the first clock domain to the second clock domain; a pulse detection module for outputting a continuous pulse signal that is synchronously converted from the first clock domain to the second clock domain; wherein, the output end of the high-level pulse synchronization module is connected to the first input end of the pulse detection module, and the output end of the low-level pulse synchronization module is connected to the second input end of the pulse detection module. The present invention realizes the transfer of signals from the first clock domain to the second clock domain, which can not only meet the transfer of signals from a fast clock domain to a slow clock domain, but also meet the transfer of signals from a slow clock domain to a fast clock domain. Through the processing of the pulse detection module, the output of continuous cross-clock-domain synchronization signals is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit design, and particularly to a cross-clock domain signal synchronization circuit. Background Art

[0002] During the chip design process, the situation where there are multiple clock domain signals simultaneously is inevitable. In the case of multiple clock domain signals, it is necessary to consider the transmission of signals between different clock domains. Currently, the main method for processing the cross-clock domain transmission of signals in the prior art is to use the method of register pipelining to achieve the transmission of slow clock domain signals to fast clock domain signals. This processing method has the problem that it cannot achieve both the synchronous transmission of fast clock domain signals to slow clock domain signals and the synchronous transmission of slow clock domain signals to fast clock domain signals. Summary of the Invention

[0003] To solve the above problems, the present invention provides a cross-clock domain signal synchronization circuit, which can achieve the transmission of signals from the fast clock domain to the slow clock domain and also from the slow clock domain to the fast clock domain, and can achieve the continuous cross-clock domain synchronization transmission of signals in multiple clock cycles. The specific technical solution of the present invention is as follows:

[0004] A cross-clock domain signal synchronization circuit specifically includes: a high-level pulse synchronization module, connected to a pulse detection module, for outputting a single-pulse high-level synchronization signal synchronously converted from a first clock domain to a second clock domain; a low-level pulse synchronization module, connected to the pulse detection module, for outputting a single-pulse low-level synchronization signal synchronously converted from the first clock domain to the second clock domain; a pulse detection module, respectively connected to the high-level pulse synchronization module and the low-level pulse synchronization module, for outputting a continuous pulse signal synchronously converted from the first clock domain to the second clock domain; wherein, the output end of the high-level pulse synchronization module is connected to the first input end of the pulse detection module, and the output end of the low-level pulse synchronization module is connected to the second input end of the pulse detection module.

[0005] Furthermore, the high-level pulse synchronization module specifically includes: a single-pulse high-level signal synchronization module, configured to output a single-pulse high-level synchronization signal that is synchronously converted from the first clock domain to the second clock domain based on an externally input synchronization signal; a single-pulse high-level signal compensation module, configured to output a first compensation and correction signal for compensating and correcting an abnormal single-pulse high-level synchronization signal; a first AND gate, configured to perform an AND logic selection on the single-pulse high-level synchronization signal and the first compensation and correction signal, and output a normal single-pulse high-level synchronization signal that is synchronously converted from the first clock domain to the second clock domain; wherein, the output end of the single-pulse high-level signal synchronization module is connected to the first input end of the first AND gate, the output end of the single-pulse high-level signal compensation module is connected to the second input end of the first AND gate, and the output end of the first AND gate serves as the output end of the high-level pulse synchronization module and is connected to the pulse detection module.

[0006] Furthermore, the single-pulse high-level signal synchronization module specifically includes: a second AND gate, a third AND gate, a first register, a second register, a third register, a first inverter, and a second inverter; wherein, the input end of the first inverter serves as the input end of the single-pulse high-level signal synchronization module and is configured to receive an externally input synchronization signal of the first clock domain; the output end of the first inverter is connected to the first input end of the second AND gate, the output end of the second AND gate is connected to the reset signal input end of the first register, the output end of the first register is connected to the first input end of the second register, the output end of the second register is connected to the first input end of the third register, the output end of the second register is further connected to the second input end of the third AND gate, the output end of the third register is connected to the input end of the second inverter, and the output end of the second inverter serves as the output end of the single-pulse high-level signal synchronization module and is connected to the first input end of the first AND gate.

[0007] Furthermore, the single-pulse high-level signal compensation module specifically includes: a fourth register, a fifth register, a sixth register, a third inverter, a fourth AND gate, and a fourth inverter; wherein, the output end of the fourth register is connected to the first input end of the fifth register, the output end of the fifth register is connected to the first input end of the sixth register, the output end of the sixth register is connected to the input end of the third inverter, the output end of the third inverter is connected to the first input end of the fourth AND gate, the output end of the fourth AND gate is connected to the input end of the fourth inverter, and the output end of the fourth inverter serves as the output end of the single-pulse high-level signal compensation module and is connected to the second input end of the first AND gate.

[0008] Further, the low-level pulse synchronization module specifically includes: a single-pulse low-level signal synchronization module for outputting a single-pulse low-level synchronization signal that is synchronously converted from the first clock domain to the second clock domain based on an externally input synchronization signal; a single-pulse low-level signal compensation module for outputting a second compensation and correction signal for compensating and correcting an abnormal single-pulse low-level signal; a fifth AND gate respectively connected to the single-pulse low-level signal synchronization module and the single-pulse low-level signal compensation module for performing an AND logic selection by combining the single-pulse low-level synchronization signal and the second compensation and correction signal, and outputting the single-pulse low-level synchronization signal in the second clock domain after the AND logic selection; a fifth inverter for inverting the single-pulse low-level synchronization signal in the second clock domain output after the AND logic selection by the fifth AND gate, and outputting a normal single-pulse low-level synchronization signal in the second clock domain; wherein, the output end of the single-pulse low-level signal synchronization module is connected to the first input end of the fifth AND gate, the output end of the single-pulse low-level signal compensation module is connected to the second input end of the fifth AND gate, the output end of the fifth AND gate is connected to the input end of the fifth inverter, and the output end of the fifth inverter serves as the output end of the low-level pulse synchronization module and is connected to the pulse detection module.

[0009] Further, the single-pulse low-level signal synchronization module specifically includes: a sixth AND gate, a seventh AND gate, a seventh register, an eighth register, a ninth register, and a sixth inverter; wherein, the first input end of the sixth AND gate serves as the input end of the single-pulse low-level signal synchronization module for receiving a signal in the first clock domain input externally; the output end of the sixth AND gate is connected to the reset signal input end of the seventh register, the output end of the seventh register is connected to the first input end of the eighth register, the output end of the eighth register is connected to the first input end of the ninth register, the output end of the eighth register is further connected to the second input end of the seventh AND gate, the output end of the ninth register is connected to the input end of the sixth inverter, the output end of the sixth inverter is connected to the first input end of the seventh AND gate, and the output end of the seventh AND gate serves as the output end of the single-pulse low-level signal synchronization module and is connected to the first input end of the fifth AND gate.

[0010] Further, the single-pulse low-level signal compensation module specifically includes: a tenth register, an eleventh register, a twelfth register, a seventh inverter, an eighth inverter, and an eighth AND gate; wherein, the output end of the tenth register is connected to the first input end of the eleventh register, the output end of the eleventh register is connected to the input end of the twelfth register, the output end of the twelfth register is connected to the input end of the seventh inverter, the output end of the seventh inverter is connected to the first input end of the eighth AND gate, the output end of the eleventh register is further connected to the second input end of the eighth AND gate, the output end of the eighth AND gate is connected to the input end of the eighth inverter, and the output end of the eighth inverter serves as the output end of the single-pulse low-level signal compensation module and is connected to the second input end of the fifth AND gate.

[0011] Further, the pulse detection module specifically includes: a first selection module, connected to a second selection module and a thirteenth register respectively, for receiving and outputting a first selected and processed pulse synchronization signal to the second selection module according to the single-pulse high-level synchronization signal in the second clock domain output by the high-level pulse synchronization module and the single-pulse low-level synchronization signal in the second clock domain output by the low-level pulse synchronization module; a second selection module, connected to the first selection module and the thirteenth register respectively, for receiving the first selected and processed synchronization signal transmitted by the first selection module, the single-pulse high-level synchronization signal in the second clock domain output by the high-level pulse synchronization module, and the single-pulse low-level synchronization signal in the second clock domain output by the low-level pulse synchronization module, and outputting a second selected and processed pulse synchronization signal to the thirteenth register; a thirteenth register, connected to the first selection module and the second selection module respectively, for outputting a continuous pulse signal in the second clock domain; wherein, the output end of the first selection module is connected to the first input end of the second selection module, the output end of the second selection module is connected to the first input end of the thirteenth register, and the output end of the thirteenth register is connected to the first input end of the first selection module.

[0012] Further, the first selection module specifically includes: a ninth inverter, a tenth inverter, a ninth AND gate, and a first selector; wherein, the input end of the ninth inverter serves as the second input end of the first selection module and is connected to the output end of the high-level pulse synchronization module, the input end of the tenth inverter serves as the third input end of the first selection module and is connected to the output end of the low-level pulse synchronization module, the output end of the ninth inverter is connected to the first input end of the ninth AND gate, the output end of the tenth inverter is connected to the second input end of the ninth AND gate, the output end of the ninth AND gate is connected to the second input end of the first selector, and the output end of the first selector serves as the output end of the first selection module and is connected to the first input end of the second selection module.

[0013] Further, the second selection module specifically includes: a tenth AND gate and a second selector; wherein, the first input terminal of the tenth AND gate serves as the second input terminal of the second selection module and is connected to the output terminal of the high-level pulse synchronization module, the second input terminal of the tenth AND gate serves as the third input terminal of the second selection module and is connected to the output terminal of the low-level pulse synchronization module, the output terminal of the tenth AND gate is connected to the second input terminal of the second selector, the first input terminal of the second selector serves as the first input terminal of the second selection module and is connected to the output terminal of the first selector of the first module, and the output terminal of the second selector serves as the output terminal of the second selection module and is connected to the first input terminal of the thirteenth register.

[0014] Further, the second input terminal of the second AND gate, the second input terminal of the sixth AND gate, the reset signal input terminals of the second register, the third register, the fourth register, the fifth register, the sixth register, the eighth register, the ninth register, the tenth register, the eleventh register, the twelfth register, and the thirteenth register are respectively used to receive an externally input inverted reset signal.

[0015] Further, the clock signal input terminals of the second register, the third register, the fourth register, the fifth register, the sixth register, the eighth register, the ninth register, the tenth register, the eleventh register, the twelfth register, and the thirteenth register are respectively used to receive a clock signal of an externally input second clock domain.

[0016] Further, the first input terminals of the first register, the fourth register, the seventh register, the tenth register, and the third input terminal of the first selector respectively receive an externally input low control signal; the third input terminal of the second selector receives an externally input high control signal.

[0017] The cross-clock domain signal synchronization circuit disclosed by the present invention realizes the transfer of signals from the first clock domain to the second clock domain, which can not only meet the transfer of signals from a fast clock domain to a slow clock domain, but also meet the transfer of signals from a slow clock domain to a fast clock domain. Through the processing of the pulse detection module, the output of continuous cross-clock domain synchronous signals is realized. Description of the Drawings

[0018] Figure 1 It is a schematic diagram of the modules of the cross-clock domain signal synchronization circuit according to the first embodiment of the present invention.

[0019] Figure 2 It is a schematic diagram of the structure of the high-level pulse synchronization module according to the second embodiment of the present invention.

[0020] Figure 3 It is a schematic diagram of the structure of the single-pulse high-level signal synchronization module according to the third embodiment of the present invention.

[0021] Figure 4 It is a schematic diagram of the structure of the single-pulse high-level signal compensation module according to the fourth embodiment of the present invention.

[0022] Figure 5 It is a schematic diagram of the structure of the low-level pulse synchronization module according to the fifth embodiment of the present invention.

[0023] Figure 6 It is a schematic diagram of the structure of the single-pulse low-level signal synchronization module according to the sixth embodiment of the present invention.

[0024] Figure 7 It is a schematic diagram of the structure of the single-pulse low-level signal compensation module according to the seventh embodiment of the present invention.

[0025] Figure 8 It is a schematic diagram of the structure of the pulse detection module according to the eighth embodiment of the present invention.

[0026] Figure 9 It is a schematic diagram of the structure of the first selection module according to the ninth embodiment of the present invention.

[0027] Figure 10 It is a schematic diagram of the structure of the second selection module according to the tenth embodiment of the present invention.

[0028] Figure 11 It is a signal waveform diagram of each signal in the cross-clock signal synchronization circuit according to the eleventh embodiment of the present invention. Detailed Embodiments

[0029] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be described and explained below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described below are only used to explain the present invention and are not used to limit the present invention. In addition, it can also be understood that for those of ordinary skill in the art, making some design, manufacturing or production changes to the technical content disclosed in the present invention is only a conventional technical means and should not be understood that the content disclosed in this application is insufficient.

[0030] Unless otherwise defined, the technical terms or scientific terms involved in the present invention should have the ordinary meaning understood by those with general skills in the technical field to which this application belongs. The words "a", "one", "kind", "the", etc. involved in this application do not indicate a quantity limitation and can represent a singular or plural number. The terms "include", "comprise", "have" and any variations thereof involved in this application are intended to cover non-exclusive inclusion. For example, a process, method, system product or device that includes a series of steps or modules is not limited to the listed steps or units, but may further include steps or modules not listed, or may further include other steps or units inherent to these processes, methods, products or devices. The terms "first", "second", "third", etc. involved in this application are only used to distinguish similar counterparts and do not represent a specific order for the objects.

[0031] As a preferred embodiment of the present invention, in the first embodiment of the present invention, a cross-clock domain signal synchronization circuit is provided, as Figure 1 shown. The cross-clock domain signal synchronization circuit specifically includes: a high-level pulse synchronization module, a low-level pulse synchronization module, and a first AND gate.

[0032] Specifically, the output end of the high-level pulse synchronization module is connected to the pulse detection module, and is used to transmit the single-pulse high-level synchronization signal that is synchronized and converted from the first clock domain to the second clock domain and output by the high-level pulse synchronization module to the pulse detection module; the output end of the low-level pulse synchronization module is connected to the pulse detection module, and is used to transmit the single-pulse low-level synchronization signal that is synchronized and converted from the first clock domain to the second clock domain at the output end of the low-level pulse synchronization module to the pulse detection module; the pulse detection module is used to generate and output a continuous pulse signal in the second clock domain according to the received single-pulse high-level synchronization signal and the single-pulse low-level synchronization signal. It should be noted that the first clock domain and the second clock domain are two different clock domains, and the first clock domain can be a clock domain faster than the second clock domain or a clock domain slower than the second clock domain. In this embodiment, by setting the pulse detection module, the single-pulse high-level synchronization signal and the single-pulse low-level synchronization signal are fused into a continuous pulse signal in the second clock domain, which can not only meet the transmission of signals from the fast clock domain to the slow clock domain, but also meet the transmission of signals from the slow clock domain to the fast clock domain, realizing the conversion of cross-clock domain signals.

[0033] Based on the above embodiment, as a preferred embodiment of the present invention, in the second embodiment of the present invention, the high-level pulse synchronization module specifically includes: a single-pulse high-level signal synchronization module, a single-pulse high-level signal compensation module, and a first AND gate; wherein, as Figure 2 shown, the output end of the single-pulse high-level signal synchronization module is connected to the first input end of the first AND gate, the output end of the single-pulse high-level signal compensation module is connected to the second input end of the first AND gate, and the output end of the first AND gate serves as the output end of the high-level pulse synchronization module and is connected to the pulse detection module. Specifically, the single-pulse high-level signal synchronization module is used to output a single-pulse high-level synchronization signal that is synchronized and converted from the first clock domain to the second clock domain based on an externally input synchronization signal; the single-pulse high-level signal compensation module is used to output a first compensation and correction signal for compensating and correcting an abnormal single-pulse high-level synchronization signal; the first AND gate is used to perform an AND logic selection on the single-pulse high-level synchronization signal combined with the first compensation and correction signal, and output a normal single-pulse high-level synchronization signal that is synchronized and converted from the first clock domain to the second clock domain. In the high-level pulse synchronization module provided in this embodiment, by setting the single-pulse high-level signal compensation module, the abnormal conditions that occur during the clock domain synchronization conversion are compensated and corrected, improving the reliability of the single-pulse high-level synchronization signal output by the high-level pulse synchronization module.

[0034] Based on the above embodiment, as a preferred embodiment of the present invention, as Figure 3As shown in the figure, the single-pulse high-level signal synchronization module in the third embodiment of the present invention specifically includes: a second AND gate, a third AND gate, a first register, a second register, a third register, a first inverter, and a second inverter; wherein, the input end of the first inverter serves as the input end of the single-pulse high-level signal synchronization module and is used to receive the synchronization signal of the first clock domain input externally; the output end of the first inverter is connected to the first input end of the second AND gate, the output end of the second AND gate is connected to the reset signal input end of the first register, the first input end of the first register is used to receive the low control signal input externally, the output end of the first register is connected to the first input end of the second register, the output end of the second register is connected to the first input end of the third register, the output end of the second register is further connected to the second input end of the third AND gate, the output end of the third register is connected to the input end of the second inverter, and the output end of the second inverter serves as the output end of the single-pulse high-level signal synchronization module and is connected to the first input end of the first AND gate. Preferably, the second input end of the second AND gate, the reset signal input end of the second register, and the reset signal input end of the third register are respectively used to receive the inverted reset signal input externally; the clock signal input ends of the second register and the third register respectively receive the clock signals of the second clock domain. The single-pulse high-level signal synchronization module provided in this embodiment realizes the pipelining of the input first clock domain signal by means of three registers in series, realizes the conversion of the synchronization signal of the first clock domain to the second clock domain. At the same time, the synchronization signal of the first clock domain input externally is processed by the first inverter and the second AND gate and used as the reset signal of the first register, realizing the bidirectional free transfer of the high-level synchronization signal between the fast clock domain and the slow clock domain, not limited to the transfer from the slow clock domain to the fast clock domain only.

[0035] Based on the above embodiments, as a preferred embodiment of the present invention, as Figure 4As shown in the figure, in the fourth embodiment of the present invention, the single-pulse high-level signal compensation module specifically includes: a fourth register, a fifth register, a sixth register, a third inverter, a fourth AND gate, and a fourth inverter; wherein, the first input end of the fourth register is used to receive a low control signal input externally, the output end of the fourth register is connected to the first input end of the fifth register, the output end of the fifth register is connected to the first input end of the sixth register, the output end of the sixth register is connected to the input end of the third inverter, the output end of the third inverter is connected to the first input end of the fourth AND gate, the output end of the fourth AND gate is connected to the input end of the fourth inverter, and the output end of the fourth inverter serves as the output end of the single-pulse high-level signal compensation module and is connected to the second input end of the first AND gate; preferably, the reset signal input ends of the fourth register, the fifth register, and the sixth register are respectively used to receive an inverted reset signal input externally; the clock signal input ends of the fourth register, the fifth register, and the sixth register are respectively used to receive the clock signal of the second clock domain. The single-pulse high-level signal compensation module provided in this embodiment compensates and corrects the abnormal single-pulse high-level synchronization signal when the single-pulse high-level signal synchronization module outputs an abnormal single-pulse high-level synchronization signal.

[0036] Based on the above embodiments, as a relatively preferred embodiment of the present invention, as Figure 5 shown in the figure, in the fifth embodiment of the present invention, the low-level pulse synchronization module specifically includes: a single-pulse low-level signal synchronization module, a single-pulse low-level signal compensation module, a fifth AND gate, and a fifth inverter; wherein, the output end of the single-pulse low-level signal synchronization module is connected to the first input end of the fifth AND gate, the output end of the single-pulse low-level signal compensation module is connected to the second input end of the fifth AND gate, the output end of the fifth AND gate is connected to the input end of the fifth inverter, and the output end of the fifth inverter serves as the output end of the low-level pulse synchronization module and is connected to the pulse detection module.

[0037] Specifically, the single-pulse low-level signal synchronization module is configured to output a single-pulse low-level synchronization signal that is synchronously converted from the first clock domain to the second clock domain based on an externally input synchronization signal; the single-pulse low-level signal compensation module is configured to output a second compensation and correction signal for compensating and correcting an abnormal single-pulse low-level signal; the fifth AND gate is respectively connected to the single-pulse low-level signal synchronization module and the single-pulse low-level signal compensation module, and is configured to perform an AND logic selection by combining the single-pulse low-level synchronization signal and the second compensation and correction signal, and output the single-pulse low-level synchronization signal in the second clock domain after the AND logic selection; the fifth inverter is configured to invert the single-pulse low-level synchronization signal in the second clock domain output after the AND logic selection by the fifth AND gate, and output a normal single-pulse low-level synchronization signal in the second clock domain. The low-level pulse synchronization module provided in this embodiment is used to synchronize the low-level pulse signal of a single clock cycle, realize the bidirectional free transmission of the low-level synchronization signal between the fast clock domain and the slow clock domain, not only limited to transmitting from the slow clock domain to the fast clock domain, but also by setting the single-pulse low-level signal compensation module to compensate and correct abnormal situations that occur during the clock domain synchronization conversion, and improve the reliability of the single-pulse low-level synchronization signal output by the low-level pulse synchronization module.

[0038] Based on the above embodiments, as a preferred embodiment of the present invention, as Figure 6 shown, in the sixth embodiment of the present invention, the single-pulse low-level signal synchronization module specifically includes: a sixth AND gate, a seventh AND gate, a seventh register, an eighth register, a ninth register, and a sixth inverter; wherein, the first input terminal of the sixth AND gate serves as the input terminal of the single-pulse low-level signal synchronization module and is used to receive the signal in the first clock domain input externally, the second input terminal of the sixth AND gate is used to receive the externally input inverted reset signal, the output terminal of the sixth AND gate is connected to the reset signal input terminal of the seventh register, the first input terminal of the seventh register is used to receive the externally input low control signal, the output terminal of the seventh register is connected to the first input terminal of the eighth register, the output terminal of the eighth register is connected to the first input terminal of the ninth register, the output terminal of the eighth register is further connected to the second input terminal of the seventh AND gate, the output terminal of the ninth register is connected to the input terminal of the sixth inverter, the output terminal of the sixth inverter is connected to the first input terminal of the seventh AND gate, and the output terminal of the seventh AND gate serves as the output terminal of the single-pulse low-level signal synchronization module and is connected to the first input terminal of the fifth AND gate. Preferably, the reset signal input terminals of the eighth register and the ninth register are respectively used to receive the externally input inverted reset signal; the clock signal input terminals of the eighth register and the ninth register are respectively used to receive the clock signal in the second clock domain.

[0039] Based on the above embodiments, as a preferred embodiment of the present invention, as Figure 7 shown, in the seventh embodiment of the present invention, the single-pulse low-level signal compensation module specifically includes: a tenth register, an eleventh register, a twelfth register, a seventh inverter, an eighth inverter, and an eighth AND gate; wherein, the first input terminal of the tenth register is used to receive an externally input low control signal, the output terminal of the tenth register is connected to the first input terminal of the eleventh register, the output terminal of the eleventh register is connected to the input terminal of the twelfth register, the output terminal of the twelfth register is connected to the input terminal of the seventh inverter, the output terminal of the seventh inverter is connected to the first input terminal of the eighth AND gate, the output terminal of the eleventh register is also connected to the second input terminal of the eighth AND gate, the output terminal of the eighth AND gate is connected to the input terminal of the eighth inverter, and the output terminal of the eighth inverter serves as the output terminal of the single-pulse low-level signal compensation module and is connected to the second input terminal of the fifth AND gate. Preferably, the reset signal input terminals of the eleventh register and the twelfth register are respectively used to receive externally input inverted reset signals; the clock signal input terminals of the tenth register, the eleventh register, and the twelfth register are respectively used to receive clock signals of the second clock domain. The single-pulse low-level signal compensation module provided in this embodiment realizes providing a compensation correction signal for the abnormal single-pulse low-level synchronization signal output by the single-pulse low-level signal synchronization module, ensuring that the influence of abnormal situations is minimized, and improving the reliability of cross-clock domain synchronization signal conversion.

[0040] Based on the above embodiments, as a preferred embodiment of the present invention, as Figure 8 shown, in the eighth embodiment of the present invention, the pulse detection module specifically includes: a first selection module, a second selection module, and a thirteenth register; wherein, the output terminal of the first selection module is connected to the first input terminal of the second selection module, the output terminal of the second selection module is connected to the first input terminal of the thirteenth register, the output terminal of the thirteenth register is connected to the first input terminal of the first selection module, the reset input terminal of the thirteenth register is used to receive an externally input inverted signal, and the clock signal input terminal of the thirteenth register is used to input a clock signal of the second clock domain.

[0041] Specifically, the first selection module is configured to receive and output the first selected and processed pulse synchronization signal to the second selection module according to the single-pulse high-level synchronization signal in the second clock domain output by the high-level pulse synchronization module and the single-pulse low-level synchronization signal in the second clock domain output by the low-level pulse synchronization module; the second selection module is configured to receive the first selected and processed synchronization signal transmitted by the first selection module, the single-pulse high-level synchronization signal in the second clock domain output by the high-level pulse synchronization module, and the single-pulse low-level synchronization signal in the second clock domain output by the low-level pulse synchronization module, and output the second selected and processed pulse synchronization signal to the thirteenth register; the thirteenth register is configured to output the continuous pulse signal in the second clock domain. The pulse detection module provided in this embodiment realizes the conversion of the synchronization signal from a single pulse to a continuous pulse signal in the second clock domain by setting two selection modules to double-select the single-pulse high-level synchronization signal output by the high-level pulse synchronization module and the single-pulse level synchronization signal output by the low-level pulse synchronization module, and can continuously perform cross-clock transmission of the synchronization signal without being limited by the clock cycle.

[0042] Preferably, the inverted reset signals received by the second input terminal of the second AND gate, the second input terminal of the sixth AND gate, the reset signal input terminal of the second register, the reset signal input terminal of the third register, the reset signal input terminal of the fourth register, the reset signal input terminal of the fifth register, the reset signal input terminal of the sixth register, the reset signal input terminal of the eighth register, the reset signal input terminal of the ninth register, the reset signal input terminal of the tenth register, the reset signal input terminal of the eleventh register, the reset signal input terminal of the twelfth register, and the reset signal input terminal of the thirteenth register are the same.

[0043] Preferably, the clock signals in the second clock domain received by the clock signal input terminal of the second register, the clock signal input terminal of the third register, the clock signal input terminal of the fourth register, the clock signal input terminal of the fifth register, the clock signal input terminal of the sixth register, the clock signal input terminal of the eighth register, the clock signal input terminal of the ninth register, the clock signal input terminal of the tenth register, the clock signal input terminal of the eleventh register, the clock signal input terminal of the twelfth register, and the clock signal input terminal of the thirteenth register are the same.

[0044] Based on the above embodiments, as a preferred embodiment of the present invention, as Figure 9As shown in the figure, in the ninth embodiment of the present invention, the first selection module specifically includes: a ninth inverter, a tenth inverter, a ninth AND gate, and a first selector; wherein, the input terminal of the ninth inverter serves as the second input terminal of the first selection module and is connected to the output terminal of the high-level pulse synchronization module, the input terminal of the tenth inverter serves as the third input terminal of the first selection module and is connected to the output terminal of the low-level pulse synchronization module, the output terminal of the ninth inverter is connected to the first input terminal of the ninth AND gate, the output terminal of the tenth inverter is connected to the second input terminal of the ninth AND gate, the output terminal of the ninth AND gate is connected to the second input terminal of the first selector, the third input terminal of the first selector receives an externally input low control signal, and the output terminal of the first selector serves as the output terminal of the first selection module and is connected to the first input terminal of the second selection module.

[0045] Specifically, when the output signal of the ninth AND gate is at a high level, the low control signal is selected as the first selection processed synchronization signal output by the first selector; conversely, when the output signal of the ninth AND gate is at a low level, the second clock domain synchronization signal output by the thirteenth register is selected as the first selection processed synchronization signal output by the first selector.

[0046] Based on the above embodiments, as a preferred embodiment of the present invention, as Figure 10 As shown in the figure, in the tenth embodiment of the present invention, the second selection module specifically includes: a tenth AND gate and a second selector; wherein, the first input terminal of the tenth AND gate serves as the second input terminal of the second selection module and is connected to the output terminal of the high-level pulse synchronization module, the second input terminal of the tenth AND gate serves as the third input terminal of the second selection module and is connected to the output terminal of the low-level pulse synchronization module, the output terminal of the tenth AND gate is connected to the second input terminal of the second selector, the first input terminal of the second selector serves as the first input terminal of the second selection module and is connected to the output terminal of the first selector of the first module, the third input terminal of the second selector receives an externally input high control signal, and the output terminal of the second selector serves as the output terminal of the second selection module and is connected to the first input terminal of the thirteenth register.

[0047] Specifically, when the output signal of the tenth AND gate is at a high level, the high control signal is selected as the second selection processed synchronization signal output by the second selector; conversely, when the output signal of the tenth AND gate is at a low level, the first selection processed synchronization signal output by the first selector is selected as the second selection processed synchronization signal output by the second selector.

[0048] It should be noted that the reset values of the first register, the fourth register, the seventh register, and the tenth register are high level; the reset values of the second register, the third register, the fifth register, the sixth register, the eighth register, the ninth register, the eleventh register, and the twelfth register are low level.

[0049] Based on the above embodiments, as a preferred embodiment of the present invention, in the eleventh embodiment of the present invention, a cross-clock domain signal synchronization circuit is provided. Figure 11 The following shows the waveform changes of each signal in the circuit. Figure 11 Among them, aclk is the waveform change of the clock signal in the first clock domain, bclk is the waveform change of the clock signal in the second clock domain, signal_in refers to the waveform change of the synchronization signal externally input to the high-level pulse synchronization module and the low-level pulse synchronization module, signal_pos refers to the waveform change of the single-pulse high-level synchronization signal in the second clock domain output by the high-level pulse synchronization module, signal_neg refers to the waveform change of the single-pulse low-level synchronization signal in the second clock domain output by the low-level pulse synchronization module, and signal_out refers to the continuous pulse signal in the second clock domain output by the pulse detection module. As Figure 11 can be seen, when the level states of the single-pulse high-level synchronization signal output by the high-level pulse synchronization module and the single-pulse low-level synchronization signal output by the low-level pulse synchronization module are both high level states, the level state of the continuous pulse signal output by the pulse detection module is pulled high to the high level state. On the contrary, when the level states of the single-pulse high-level synchronization signal output by the high-level pulse synchronization module and the single-pulse low-level synchronization signal output by the low-level pulse synchronization module are both low level states, the level states of the continuous pulses output by the pulse detection module are pulled low to the low level state. Moreover, when the level states of the single-pulse high-level synchronization signal output by the high-level pulse synchronization module and the single-pulse low-level synchronization signal output by the low-level pulse synchronization module are different, the level state of the continuous pulse signal output by the pulse detection module remains unchanged.

[0050] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A cross-clock domain signal synchronization circuit, characterized in that, The cross-clock-domain signal synchronization circuit specifically includes: A high-level pulse synchronization module, connected to the pulse detection module, for outputting a single-pulse high-level synchronization signal that is synchronously converted from the first clock domain to the second clock domain; A low-level pulse synchronization module, connected to the pulse detection module, for outputting a single-pulse low-level synchronization signal that is synchronously converted from the first clock domain to the second clock domain; A pulse detection module, respectively connected to the high-level pulse synchronization module and the low-level pulse synchronization module, for outputting a continuous pulse signal that is synchronously converted from the first clock domain to the second clock domain; Wherein, the output end of the high-level pulse synchronization module is connected to the first input end of the pulse detection module, and the output end of the low-level pulse synchronization module is connected to the second input end of the pulse detection module; Wherein, the high-level pulse synchronization module specifically includes: A single-pulse high-level signal synchronization module, for outputting a single-pulse high-level synchronization signal that is synchronously converted from the first clock domain to the second clock domain based on an externally input synchronization signal; A single-pulse high-level signal compensation module, for outputting a first compensation and correction signal for compensating and correcting an abnormal single-pulse high-level synchronization signal; A first AND gate, for performing an AND logic selection on the single-pulse high-level synchronization signal and the first compensation and correction signal, and outputting a normal single-pulse high-level synchronization signal that is synchronously converted from the first clock domain to the second clock domain; Wherein, the output end of the single-pulse high-level signal synchronization module is connected to the first input end of the first AND gate, the output end of the single-pulse high-level signal compensation module is connected to the second input end of the first AND gate, and the output end of the first AND gate serves as the output end of the high-level pulse synchronization module and is connected to the pulse detection module; Wherein, the single-pulse high-level signal synchronization module specifically includes: a second AND gate, a third AND gate, a first register, a second register, a third register, a first inverter, and a second inverter; wherein, the input end of the first inverter serves as the input end of the single-pulse high-level signal synchronization module for receiving an externally input synchronization signal of the first clock domain; the output end of the first inverter is connected to the first input end of the second AND gate, the output end of the second AND gate is connected to the reset signal input end of the first register, the output end of the first register is connected to the first input end of the second register, the output end of the second register is connected to the first input end of the third register, the output end of the second register is further connected to the second input end of the third AND gate, the output end of the third register is connected to the input end of the second inverter, and the output end of the second inverter serves as the output end of the single-pulse high-level signal synchronization module and is connected to the first input end of the first AND gate; Among them, the second input terminal of the second AND gate, the reset signal input terminal of the second register, and the reset signal input terminal of the third register are respectively used to receive the inverted reset signal input externally; the clock signal input terminals of the second register and the third register are respectively used to receive the clock signal of the second clock domain input externally; the first input terminal of the first register receives the low control signal input externally.

2. The cross-clock domain signal synchronization circuit according to claim 1, wherein The single-pulse high-level signal compensation module specifically includes: a fourth register, a fifth register, a sixth register, a third inverter, a fourth AND gate, and a fourth inverter; among them, the output terminal of the fourth register is connected to the first input terminal of the fifth register, the output terminal of the fifth register is connected to the first input terminal of the sixth register, the output terminal of the sixth register is connected to the input terminal of the third inverter, the output terminal of the third inverter is connected to the first input terminal of the fourth AND gate, the output terminal of the fourth AND gate is connected to the input terminal of the fourth inverter, and the output terminal of the fourth inverter serves as the output terminal of the single-pulse high-level signal compensation module and is connected to the second input terminal of the first AND gate; Among them, the first input terminal of the fourth register receives the low control signal input externally; the reset signal input terminals of the fourth register, the fifth register, and the sixth register are respectively used to receive the inverted reset signal input externally; the clock signal input terminals of the fourth register, the fifth register, and the sixth register are respectively used to receive the clock signal of the second clock domain input externally; the output terminal of the fifth register is connected to the second input terminal of the fourth AND gate.

3. The cross-clock-domain signal synchronization circuit according to claim 1, wherein The low-level pulse synchronization module specifically includes: A single-pulse low-level signal synchronization module, which is used to output a single-pulse low-level synchronization signal that is synchronously converted from the first clock domain to the second clock domain based on the externally input synchronization signal; A single-pulse low-level signal compensation module, which is used to output a second compensation and correction signal for compensating and correcting the abnormal single-pulse low-level signal; A fifth AND gate, which is respectively connected to the single-pulse low-level signal synchronization module and the single-pulse low-level signal compensation module, and is used to perform an AND logic selection by combining the single-pulse low-level synchronization signal and the second compensation and correction signal, and output the single-pulse low-level synchronization signal of the second clock domain after the AND logic selection; A fifth inverter, which is used to invert the single-pulse low-level synchronization signal of the second clock domain output after the AND logic selection by the fifth AND gate, and output the normal single-pulse low-level synchronization signal of the second clock domain; Among them, the output terminal of the single-pulse low-level signal synchronization module is connected to the first input terminal of the fifth AND gate, the output terminal of the single-pulse low-level signal compensation module is connected to the second input terminal of the fifth AND gate, the output terminal of the fifth AND gate is connected to the input terminal of the fifth inverter, and the output terminal of the fifth inverter serves as the output terminal of the low-level pulse synchronization module and is connected to the pulse detection module.

4. The cross-clock-domain signal synchronization circuit according to claim 3, wherein The single-pulse low-level signal synchronization module specifically includes: a sixth AND gate, a seventh AND gate, a seventh register, an eighth register, a ninth register, and a sixth inverter; wherein, the first input terminal of the sixth AND gate serves as the input terminal of the single-pulse low-level signal synchronization module for receiving a signal in the first clock domain input externally; the output terminal of the sixth AND gate is connected to the reset signal input terminal of the seventh register, the output terminal of the seventh register is connected to the first input terminal of the eighth register, the output terminal of the eighth register is connected to the first input terminal of the ninth register, the output terminal of the eighth register is further connected to the second input terminal of the seventh AND gate, the output terminal of the ninth register is connected to the input terminal of the sixth inverter, the output terminal of the sixth inverter is connected to the first input terminal of the seventh AND gate, and the output terminal of the seventh AND gate serves as the output terminal of the single-pulse low-level signal synchronization module and is connected to the first input terminal of the fifth AND gate; wherein, the second input terminal of the sixth AND gate, the reset signal input terminal of the eighth register, and the reset signal input terminal of the ninth register are respectively used for receiving an inverted reset signal input externally; the clock signal input terminals of the eighth register and the ninth register are respectively used for receiving a clock signal in the second clock domain input externally; the first input terminal of the seventh register receives a low control signal input externally.

5. The cross-clock-domain signal synchronization circuit according to claim 4, wherein The single-pulse low-level signal compensation module specifically includes: a tenth register, an eleventh register, a twelfth register, a seventh inverter, an eighth inverter, and an eighth AND gate; wherein, the output terminal of the tenth register is connected to the first input terminal of the eleventh register, the output terminal of the eleventh register is connected to the input terminal of the twelfth register, the output terminal of the twelfth register is connected to the input terminal of the seventh inverter, the output terminal of the seventh inverter is connected to the first input terminal of the eighth AND gate, the output terminal of the eleventh register is further connected to the second input terminal of the eighth AND gate, the output terminal of the eighth AND gate is connected to the input terminal of the eighth inverter, and the output terminal of the eighth inverter serves as the output terminal of the single-pulse low-level signal compensation module and is connected to the second input terminal of the fifth AND gate; wherein, the reset signal input terminals of the tenth register, the eleventh register, and the twelfth register are respectively used for receiving an inverted reset signal input externally; the clock signal input terminals of the tenth register, the eleventh register, and the twelfth register are respectively used for receiving a clock signal in the second clock domain input externally; the first input terminal of the tenth register receives a low control signal input externally.

6. The cross-clock-domain signal synchronization circuit according to claim 1, wherein The pulse detection module specifically includes: The first selection module, which is connected to the second selection module and the thirteenth register respectively, is configured to receive and output the first selected and processed pulse synchronization signal to the second selection module according to the single-pulse high-level synchronization signal in the second clock domain output by the high-level pulse synchronization module and the single-pulse low-level synchronization signal in the second clock domain output by the low-level pulse synchronization module; The second selection module, which is connected to the first selection module and the thirteenth register respectively, is configured to receive the first selected and processed synchronization signal transmitted by the first selection module, the single-pulse high-level synchronization signal in the second clock domain output by the high-level pulse synchronization module, and the single-pulse low-level synchronization signal in the second clock domain output by the low-level pulse synchronization module, and output the second selected and processed pulse synchronization signal to the thirteenth register; The thirteenth register, which is connected to the first selection module and the second selection module respectively, is configured to output the continuous pulse signal in the second clock domain; Wherein, the output end of the first selection module is connected to the first input end of the second selection module, the output end of the second selection module is connected to the first input end of the thirteenth register, and the output end of the thirteenth register is connected to the first input end of the first selection module; Wherein, the reset signal input end of the thirteenth register is configured to receive the externally input inverted reset signal; the clock signal input ends of the thirteenth register are respectively configured to receive the externally input clock signal in the second clock domain.

7. The cross-clock-domain signal synchronization circuit according to claim 6, wherein The first selection module specifically includes: a ninth inverter, a tenth inverter, a ninth AND gate, and a first selector; wherein, the input end of the ninth inverter serves as the second input end of the first selection module and is connected to the output end of the high-level pulse synchronization module, the input end of the tenth inverter serves as the third input end of the first selection module and is connected to the output end of the low-level pulse synchronization module, the output end of the ninth inverter is connected to the first input end of the ninth AND gate, the output end of the tenth inverter is connected to the second input end of the ninth AND gate, the output end of the ninth AND gate is connected to the second input end of the first selector, the output end of the first selector serves as the output end of the first selection module and is connected to the first input end of the second selection module; the third input end of the first selector receives the externally input low control signal; the first input end of the first selector serves as the first input end of the first selection module and is connected to the output end of the thirteenth register for receiving the signal in the second clock domain output by the thirteenth register.

8. The cross-clock domain signal synchronization circuit according to claim 7, wherein, The second selection module specifically includes: a tenth AND gate and a second selector; wherein, the first input terminal of the tenth AND gate serves as the second input terminal of the second selection module and is connected to the output terminal of the high-level pulse synchronization module, the second input terminal of the tenth AND gate serves as the third input terminal of the second selection module and is connected to the output terminal of the low-level pulse synchronization module, the output terminal of the tenth AND gate is connected to the second input terminal of the second selector, the first input terminal of the second selector serves as the first input terminal of the second selection module and is connected to the output terminal of the first selector of the first selection module, the output terminal of the second selector serves as the output terminal of the second selection module and is connected to the first input terminal of the thirteenth register; the third input terminal of the second selector receives a high control signal input externally.

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