Output stage circuit

Abstract

The present invention provides an output stage circuit including a current source circuit, a bias circuit, and an output circuit. The bias circuit is coupled between the current source circuit and the ground terminal voltage. The output circuit includes a first transistor, a second transistor, a third transistor, and a load circuit. The control terminal of the first transistor is coupled to the bias circuit. The load circuit is coupled to the second terminal of the first transistor and the output terminal. The first terminal of the second transistor is coupled to the operating voltage, and the second terminal of the second transistor is coupled to the first terminal of the first transistor. The first terminal of the third transistor is coupled to the second terminal of the first transistor and the output terminal, and the second terminal of the third transistor is coupled to the ground terminal voltage.

Description

Technical Field

[0001] The present invention relates to a circuit, and more particularly to an output stage circuit. Background Art

[0002] Generally speaking, a traditional output stage circuit can only provide a voltage output result equal to the input / output supply voltage (I / O Supply Voltage, IOVDD). Therefore, if the circuit requires an output voltage with a different voltage level, the traditional output stage circuit must use a regulator to change the voltage level of the output voltage. In this regard, if the traditional output stage circuit is further equipped with a regulator circuit, the complexity of the overall circuit design will be greatly increased, and more circuit space will be required. In view of this, several solutions of embodiments are proposed below. Summary of the Invention

[0003] The present invention is directed to a regulator-free design for an output stage circuit.

[0004] According to an embodiment of the present invention, the output stage circuit of the present invention includes a current source circuit, a bias circuit, and an output circuit. The bias circuit is coupled between the current source circuit and the ground terminal voltage. The output circuit includes a first transistor, a second transistor, a third transistor, and a load circuit. The control terminal of the first transistor is coupled to the bias circuit. The load circuit is coupled to the second terminal of the first transistor and the output terminal. The first terminal of the second transistor is coupled to the operating voltage. The second terminal of the second transistor is coupled to the first terminal of the first transistor. The first terminal of the third transistor is coupled to the second terminal of the first transistor and the output terminal. The second terminal of the third transistor is coupled to the ground terminal voltage.

[0005] Based on the above, the output stage circuit of the present invention can effectively provide a stable output voltage signal.

[0006] To make the above features and advantages of the present invention more obvious and understandable, specific embodiments are hereinafter given and described in detail in conjunction with the accompanying drawings. Brief Description of the Drawings

[0007] Figure 1 is a circuit schematic diagram of an output stage circuit according to an embodiment of the present invention;

[0008] Figure 2 is a circuit schematic diagram of an output stage circuit according to a first exemplary embodiment of the present invention;

[0009] Figure 3 is a circuit schematic diagram of an output stage circuit according to a second exemplary embodiment of the present invention;

[0010] Figure 4 is a circuit schematic diagram of an output stage circuit according to a third exemplary embodiment of the present invention;

[0011] Figure 5 It is a circuit schematic diagram of the output stage circuit of the fourth exemplary embodiment of the present invention;

[0012] Figure 6 It is a circuit schematic diagram of the output stage circuit of the fifth exemplary embodiment of the present invention.

[0013] Description of reference numerals

[0014] 100, 200, 300, 400, 500, 600: Output stage circuit;

[0015] 110, 210, 310, 410, 510, 610: Current source circuit;

[0016] 120, 220, 320, 420, 520, 620: Bias circuit;

[0017] 121, 131, 133, 134, 211~214, 221, 231, 233, 234, 311~314, 321, 331, 333, 334, 411~415, 421, 431, 433, 434, 511~515, 517, 521, 531, 533, 534, 611~615, 621, 631, 633, 634: Transistor;

[0018] 130, 230, 330, 430, 530, 630: Output circuit;

[0019] 132, 232, 332, 432, 532, 632: Load circuit;

[0020] 122, 222, 322, 417, 422, 522, 616, 622: Reference resistor;

[0021] 2321, 3321, 4321, 5321, 6321: Resistor;

[0022] 250, 350, 450, 550, 650: Transistor capacitor;

[0023] 315, 416, 516, 615: Operational amplifier;

[0024] I_M, I_N: Current;

[0025] IS: Current input terminal;

[0026] SWN, SWP: Switching signal;

[0027] VSS: Ground terminal voltage;

[0028] VDD: Operating voltage;

[0029] VOUT: Voltage output terminal. Detailed implementation manners

[0030] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0031] Figure 1 is a circuit schematic diagram of an output stage circuit of an embodiment of the present invention. Refer to Figure 1 , the output stage circuit 100 may be an output pad circuit. The output stage circuit 100 includes a current source circuit 110, a bias circuit 120, and an output circuit 130. The bias circuit 120 and the output circuit 130 may form a replicabias circuit. The bias circuit 120 includes a transistor 121 and a reference resistor 122. The output circuit 130 includes a transistor 131, a load circuit 132, a transistor 133, and a transistor 134. In this embodiment, the first end of the transistor 121 is coupled to the current source circuit 110 and the control end of the transistor 121. The first end of the reference resistor 122 is coupled to the second end of the transistor 121. The second end of the reference resistor 122 is coupled to the ground voltage VSS. In other embodiments of the present invention, the bias circuit 120 may only have the transistor 121, and the second end of the transistor 121 is coupled to the ground voltage VSS. Alternatively, in still other embodiments of the present invention, the bias circuit 120 may only have the reference resistor 122, and the first end of the reference resistor 122 is coupled to the current source circuit 110.

[0032] In this embodiment, the control end of the transistor 131 is coupled to the control end of the transistor 121. The load circuit 132 is coupled to the second end of the transistor 131 and the output terminal VOUT. The first end of the transistor 133 is coupled to the operating voltage VDD. The second end of the transistor 133 is coupled to the first end of the transistor 131. The first end of the transistor 134 is coupled to the second end of the transistor 131 and the (voltage) output terminal VOUT. The second end of the transistor 134 is coupled to the ground voltage VSS.

[0033] In this embodiment, transistors 121, 131, and 134 may be N-type transistors, and transistor 133 may be a P-type transistor. The load circuit 132 may include a resistor and / or a capacitor, and the present invention is not limited thereto. Even in some other embodiments of the present invention, the output stage circuit 100 may not include the load circuit 132. The control terminals of transistor 133 and transistor 134 may receive switching signal SWN and switching signal SWP, respectively. In some embodiments of the present invention, switching signal SWN and switching signal SWP may be the same switching signal, but the present invention is not limited thereto. In this embodiment, the on-period of transistor 133 and the on-period of transistor 134 do not overlap, but the present invention is not limited thereto, either.

[0034] In this embodiment, the bias circuit 120 and the output circuit 130 may be designed such that the current ratio between the current I_M flowing through the bias circuit 120 and the current I_N flowing through the output circuit 130 is M:N, where M and N are positive integers. For example, the bias circuit 120 may include M transistors 121 connected in parallel, and the output circuit 130 may include N transistors 131 connected in parallel, where M and N are positive integers. Additionally, the number of parallel resistors of the reference resistor 122 in the bias circuit 120 and the number of parallel resistors in the load circuit 132 of the output circuit 130 may be designed as M:N. Therefore, in this embodiment, after the voltage of the circuit node Va1 (the second terminal of transistor 121) as shown in Figure 1 is set (i.e., setting the current I_M), the voltages of the circuit node Vb1 (the control terminal of transistor 121) and the circuit node Vc1 (the second terminal of transistor 131) will be fixed. In other words, when the current I_M changes, the voltage of the output terminal VOUT can follow the voltage of the circuit node Va1 to achieve the output stage function of adjusting the voltage level of the output voltage. Moreover, the output stage circuit 100 of this embodiment can provide a stable output voltage signal. It is worth mentioning that since the bias circuit 120 and the output circuit 130 have the same components and only differ in quantity, the voltage level of the output voltage can accurately track the set voltage of node Va1 without being affected by the process, voltage, and / or temperature.

[0035] In addition, the bases of the transistors 121, 131, 133, and 134 in this embodiment can be coupled to their respective corresponding sources to reduce the body effect. Additionally, an electrostatic protection circuit can be provided on the path where the output stage circuit 100 of this embodiment is coupled to the operating voltage VDD (for example, coupled between the operating voltage VDD and the output terminal VOUT), and another electrostatic protection circuit can also be provided on the path where the output stage circuit 100 of this embodiment is coupled to the ground terminal voltage VSS (for example, coupled between the ground terminal voltage VSS and the output terminal VOUT). In some other embodiments of the present invention, the output stage circuit 100 can also be designed or modified to have the function of an input stage circuit or be applied to an input stage circuit.

[0036] Figure 2 is a circuit schematic diagram of the output stage circuit of the first exemplary embodiment of the present invention. Refer to Figure 2 , this embodiment can be Figure 1 a specific implementation example of the output stage circuit 100 shown. In this embodiment, the output stage circuit 200 includes a current source circuit 210, a bias circuit 220, an output circuit 230, and a transistor capacitor 250. The bias circuit 220 and the output circuit 230 can form a replica bias circuit. The current source circuit 210 includes transistors 211 to 214. The bias circuit 220 includes a transistor 221 and a reference resistor 222. The output circuit 230 includes transistors 231, a load circuit 232, a transistor 233, and a transistor 234.

[0037] In this embodiment, the first end of transistor 211 is coupled to the operating voltage VDD. The second end of transistor 211 is coupled to the control end of transistor 211. The first end of transistor 212 is coupled to the operating voltage VDD. The control end of transistor 212 is coupled to the control end of transistor 211. The second end of transistor 212 is coupled to the first end of transistor 221. The first end of transistor 213 is coupled to the second end of transistor 211. The second end of transistor 213 is coupled to the ground voltage VSS. The first end of transistor 214 is coupled to the control end of transistor 213, the control end of transistor 214, and the current input terminal IS. The second end of transistor 214 is coupled to the ground voltage VSS. The first end of transistor 221 is coupled to the second end of transistor 212 and the control end of transistor 221. The second end of transistor 221 is coupled to the ground voltage VSS via the reference resistor 222. The control end of transistor 231 is coupled to the control end of transistor 221. The load circuit 232 is coupled to the second end of transistor 231 and the output terminal VOUT. The first end of transistor 233 is coupled to the operating voltage VDD. The second end of transistor 233 is coupled to the first end of transistor 231. The first end of transistor 234 is coupled to the second end of transistor 231 and the output terminal VOUT. The second end of transistor 234 is coupled to the ground voltage VSS. The first end and the second end of the transistor capacitor 250 are short-circuited and both are coupled to the ground voltage VSS. The second end of the transistor capacitor 250 is further coupled to the second end of transistor 234. The control end of the transistor capacitor 250 is coupled to the control end of transistor 221 and the control end of transistor 231.

[0038] It should be noted that the transistor 211 and the transistor 212 of the current source circuit 210 in this embodiment can be combined into a current mirror circuit. The current mirror circuit in this embodiment can effectively copy the input current input by the current input terminal IS. In this way, the current I_M can be equal to or approximately equal to the input current input by the current input terminal IS.

[0039] In this embodiment, the transistors 213, 214, 221, 231, 234, and the transistor capacitor 250 can be N-type transistors, and the transistors 211, 212, 233 can be P-type transistors. The load circuit 232 can include a resistor 2321, and the present invention is not limited thereto. The control ends of the transistors 233 and 234 can receive the switching signal SWN and the switching signal SWP respectively. In some embodiments of the present invention, the switching signal SWN and the switching signal SWP can be the same switching signal, but the present invention is not limited thereto. In this embodiment, the on-period of the transistor 233 and the on-period of the transistor 234 do not overlap, but the present invention is not limited thereto either.

[0040] In this embodiment, the bias circuit 220 and the output circuit 230 can be designed respectively such that the current ratio between the current I_M flowing through the bias circuit 220 and the current I_N flowing through the output circuit 230 is M:N, where M and N are positive integers. For example, the bias circuit 220 can include M transistors 221 connected in parallel, and the output circuit 230 can include N transistors 231 connected in parallel, where M and N are positive integers. Additionally, the number of parallel resistors of the reference resistor 222 of the bias circuit 220 and the number of parallel resistors in the load circuit 232 of the output circuit 230 can be designed as M:N. Therefore, in this embodiment, as Figure 2 After the voltage of the circuit node Va2 (the second end of the transistor 221) as shown is set (i.e., the current I_M is set), the voltages of the circuit node Vb2 (the control end of the transistor 221) and the circuit node Vc2 (the second end of the transistor 231) will be fixed. In other words, when the current I_M changes, the voltage of the output terminal VOUT can follow the voltage of the circuit node Va2 to achieve the output stage function of adjusting the voltage level of the output voltage. Moreover, the output stage circuit 200 of this embodiment can provide a stable output voltage signal according to the input current input by the current input terminal IS. It is worth mentioning that since the bias circuit 220 and the output circuit 230 have the same components and only differ in quantity, the voltage level of the output voltage can accurately track the set voltage of the node Va2 without being affected by the process, voltage, and / or temperature.

[0041] In addition, the bases of the transistors 211 - 214, 221, 231, 233, 234 of this embodiment can be coupled to their respective sources to reduce the substrate effect. Additionally, an electrostatic protection circuit can be provided on the path where the output stage circuit 200 of this embodiment is coupled to the operating voltage VDD (for example, coupled between the operating voltage VDD and the output terminal VOUT), and another electrostatic protection circuit can also be provided on the path where the output stage circuit 200 of this embodiment is coupled to the ground terminal voltage VSS (for example, coupled between the ground terminal voltage VSS and the output terminal VOUT).

[0042] Figure 3 is a circuit schematic diagram of the output stage circuit of the second exemplary embodiment of the present invention. Referring to Figure 3 , this embodiment can be Figure 1A specific implementation example of the output stage circuit 100 shown. In this embodiment, the output stage circuit 300 includes a current source circuit 310, a bias circuit 320, an output circuit 330, and a transistor capacitor 350. The bias circuit 320 and the output circuit 330 can form a Replica bias circuit. The current source circuit 310 includes transistors 311 to 314 and an Operational Amplifier (OPA) 315. The bias circuit 320 includes a transistor 321 and a reference resistor 322. The output circuit 330 includes a transistor 331, a load circuit 332, a transistor 333, and a transistor 334.

[0043] In this embodiment, the first end of the transistor 311 is coupled to the operating voltage VDD. The first end of the transistor 312 is coupled to the operating voltage VDD. The control end of the transistor 312 is coupled to the control end of the transistor 311. The second end of the transistor 312 is coupled to the first end of the transistor 321. The first end of the transistor 313 is coupled to the second end of the transistor 311. The second end of the transistor 313 is coupled to the ground terminal voltage VSS. The first end of the transistor 314 is coupled to the control end of the transistor 313, the control end of the transistor 314, and the current input terminal IS. The second end of the transistor 314 is coupled to the ground terminal voltage VSS. The first input terminal of the operational amplifier 315 is coupled to the second end of the transistor 211. The second input terminal of the operational amplifier 315 is coupled to the second end of the transistor 312. The output terminal of the operational amplifier 315 is coupled to the control end of the transistor 311 and the control end of the transistor 312. The first end of the transistor 321 is coupled to the second end of the transistor 312 and the control end of the transistor 321. The second end of the transistor 321 is coupled to the ground terminal voltage VSS via the reference resistor 322. The control end of the transistor 331 is coupled to the control end of the transistor 321. The load circuit 332 is coupled to the second end of the transistor 331 and the output terminal VOUT. The first end of the transistor 333 is coupled to the operating voltage VDD. The second end of the transistor 333 is coupled to the first end of the transistor 331. The first end of the transistor 334 is coupled to the second end of the transistor 331 and the output terminal VOUT. The second end of the transistor 334 is coupled to the ground terminal voltage VSS. The first end and the second end of the transistor capacitor 350 are short-circuited and both are coupled to the ground terminal voltage VSS. The second end of the transistor capacitor 350 is also coupled to the second end of the transistor 334. The control end of the transistor capacitor 350 is coupled to the control end of the transistor 321 and the control end of the transistor 331.

[0044] It should be noted that the transistor 311, transistor 312, and operational amplifier 315 of the current source circuit 310 in this embodiment can be combined into a current mirror circuit of an operational amplifier type (OPA type current mirror). The two input terminals of the operational amplifier 315 are coupled between the two second output terminals of the transistor 311 and the transistor 312, and the output terminal of the operational amplifier 315 is coupled between the two control terminals of the transistor 311 and the transistor 312. Therefore, the operational amplifier 315 in this embodiment can effectively lock the currents flowing through the transistor 311 and the transistor 312 respectively, so that the current mirror circuit in this embodiment can effectively copy the input current input by the current input terminal IS. In this way, the current I_M can be equal to or approximately equal to the input current input by the current input terminal IS.

[0045] In this embodiment, the transistors 313, 314, 321, 331, 334, and the transistor capacitor 350 can be N-type transistors, and the transistors 311, 312, 333 can be P-type transistors. The load circuit 332 can include a resistor 3321, and the present invention is not limited thereto. The control terminals of the transistor 333 and the transistor 334 can receive the switching signal SWN and the switching signal SWP respectively. In some embodiments of the present invention, the switching signal SWN and the switching signal SWP can be the same switching signal, but the present invention is not limited thereto. In this embodiment, the on-period of the transistor 333 and the on-period of the transistor 334 do not overlap, but the present invention is not limited to this either.

[0046] In this embodiment, the bias circuit 320 and the output circuit 330 can be designed respectively so that the current ratio between the current I_M flowing through the bias circuit 320 and the current I_N flowing through the output circuit 330 is M:N, where M and N are positive integers. For example, the bias circuit 320 can include M transistors 321 connected in parallel, and the output circuit 330 can include N transistors 331 connected in parallel, where M and N are positive integers. Alternatively, the number of parallel resistors of the reference resistor 322 in the bias circuit 320 and the number of parallel resistors in the load circuit 332 of the output circuit 330 can be designed as M:N. Therefore, in this embodiment, as Figure 3After the voltage of the circuit node Va3 (the second terminal of transistor 321) shown is set (i.e., setting current I_M), the voltages of circuit node Vb3 (the control terminal of transistor 321) and circuit node Vc3 (the second terminal of transistor 331) will be fixed. In other words, when current I_M changes, the voltage of output terminal VOUT can follow the voltage of circuit node Va3 to achieve the output stage function of adjusting the voltage level of the output voltage. Moreover, the output stage circuit 300 of this embodiment can provide a stable output voltage signal according to the input current input by current input terminal IS. It is worth mentioning that since bias circuit 320 and output circuit 330 have the same components and only differ in quantity, the voltage level of the output voltage can accurately track the set voltage of node Va3 without being affected by Process, Voltage, and / or Temperature.

[0047] In addition, the bases of transistors 311 to 314, 321, 331, 333, and 334 of this embodiment can be coupled to their respective corresponding sources to reduce the substrate effect. Additionally, an electrostatic protection circuit can be provided on the path where output stage circuit 300 is coupled to operating voltage VDD (for example, coupled between operating voltage VDD and output terminal VOUT), and another electrostatic protection circuit can also be provided on the path where output stage circuit 300 is coupled to ground terminal voltage VSS (for example, coupled between ground terminal voltage VSS and output terminal VOUT).

[0048] Figure 4 is a circuit schematic diagram of the output stage circuit of the third exemplary embodiment of the present invention. Refer to Figure 4 , this embodiment can be Figure 1 a specific implementation example of the output stage circuit 100 shown. In this embodiment, output stage circuit 400 includes current source circuit 410, bias circuit 420, output circuit 430, and transistor capacitor 450. Bias circuit 420 and output circuit 430 can form a Replica bias circuit. Current source circuit 410 includes transistors 411 to 415, operational amplifier 416, and reference resistor 417. Bias circuit 420 includes transistor 421 and reference resistor 422. Output circuit 430 includes transistor 431, load circuit 432, transistor 433, and transistor 434.

[0049] In this embodiment, the first end of transistor 411 is coupled to the operating voltage VDD. The second end of transistor 411 is coupled to the control end of transistor 411. The first end of transistor 412 is coupled to the operating voltage VDD. The control end of transistor 412 is coupled to the control end of transistor 411. The second end of transistor 412 is coupled to the first end of transistor 421. The first end of transistor 413 is coupled to the second end of transistor 411. The second end of transistor 413 is coupled to the ground terminal voltage VSS. The first end of transistor 414 is coupled to the control end of transistor 413, the control end of transistor 414, and the current input terminal IS. The second end of transistor 414 is coupled to the ground terminal voltage VSS. The control end of transistor 411 is coupled to the second end of transistor 411. The first end of transistor 415 is coupled to the operating voltage VDD. The control end of transistor 415 is coupled to the control end of transistor 411 and the control end of transistor 412. The second end of transistor 415 is coupled to the ground terminal voltage VSS via the reference resistor 417. The first input terminal of the operational amplifier 416 is coupled to the second end of transistor 415. The second input terminal of the operational amplifier 416 is coupled to the second end of transistor 421. The output terminal of the operational amplifier 416 is coupled to the control end of transistor 421.

[0050] In this embodiment, the first end of transistor 421 is coupled to the second end of transistor 412. The second end of transistor 421 is coupled to the ground terminal voltage VSS via the reference resistor 422. The control end of transistor 431 is coupled to the control end of transistor 421. The load circuit 432 is coupled to the second end of transistor 431 and the output terminal VOUT. The first end of transistor 433 is coupled to the operating voltage VDD. The second end of transistor 433 is coupled to the first end of transistor 431. The first end of transistor 434 is coupled to the second end of transistor 431 and the output terminal VOUT. The second end of transistor 434 is coupled to the ground terminal voltage VSS. The first end and the second end of the transistor capacitor 450 are short-circuited and both are coupled to the ground terminal voltage VSS. The second end of the transistor capacitor 450 is further coupled to the second end of transistor 434. The control end of the transistor capacitor 450 is coupled to the control end of transistor 421 and the control end of transistor 431.

[0051] It should be noted that the transistor 411, transistor 412, and transistor 415 of the current source circuit 410 in this embodiment can be combined into a current mirror circuit, and the control terminal of the transistor 421 in this embodiment is not coupled to the first terminal of the transistor 421. The output terminal of the operational amplifier 416 in this embodiment is coupled to the control terminal of the transistor 421 to fix the voltage of the control terminal of the transistor 421. Therefore, the operational amplifier 416 in this embodiment can effectively lock the current I_M flowing through the transistor 421. More importantly, there can be more voltage headroom between the first terminal of the transistor 421 and the operating voltage VDD. In this way, the current I_M can be equal to or approximately equal to the input current input by the current input terminal IS.

[0052] In this embodiment, the transistors 413, 414, 421, 431, 434, and the transistor capacitor 450 can be N-type transistors, and the transistors 411, 412, 415, 433 can be P-type transistors. The load circuit 432 can include a resistor 4321, and the present invention is not limited thereto. The control terminals of the transistor 433 and the transistor 434 can receive the switching signal SWN and the switching signal SWP respectively. In some embodiments of the present invention, the switching signal SWN and the switching signal SWP can be the same switching signal, but the present invention is not limited thereto. In this embodiment, the on-period of the transistor 433 and the on-period of the transistor 434 do not overlap, but the present invention is not limited thereto.

[0053] In this embodiment, the bias circuit 420 and the output circuit 430 can be designed respectively such that the current ratio between the current I_M flowing through the bias circuit 420 and the current I_N flowing through the output circuit 430 is M:N, where M and N are positive integers. For example, the bias circuit 420 can include M transistors 421 connected in parallel, and the output circuit 430 can include N transistors 431 connected in parallel, where M and N are positive integers. Alternatively, the number of parallel resistors of the reference resistor 422 in the bias circuit 420 and the number of parallel resistors in the load circuit 432 of the output circuit 430 can be designed as M:N. Therefore, in this embodiment, as Figure 4After the voltage of the circuit node Va4 (the second terminal of transistor 421) as shown is set (i.e., the set current I_M), the voltages of the circuit node Vb4 (the control terminal of transistor 421) and the circuit node Vc4 (the second terminal of transistor 431) will be fixed. In other words, when the current I_M changes, the voltage of the output terminal VOUT can follow the voltage of the circuit node Va4 to achieve the output stage function of adjusting the voltage level of the output voltage. Moreover, the output stage circuit 400 of this embodiment can provide a stable output voltage signal according to the input current input by the current input terminal IS. It is worth mentioning that since the bias circuit 420 and the output circuit 430 have the same components and only differ in quantity, the voltage level of the output voltage can accurately track the set voltage of node Va4 without being affected by the process, voltage, and / or temperature.

[0054] In addition, the bases of transistors 411 to 415, 421, 431, 433, and 434 of this embodiment can be coupled to their respective corresponding sources to reduce the substrate effect. Additionally, an electrostatic protection circuit can be provided on the path where the output stage circuit 400 of this embodiment is coupled to the operating voltage VDD (for example, coupled between the operating voltage VDD and the output terminal VOUT), and another electrostatic protection circuit can also be provided on the path where the output stage circuit 400 of this embodiment is coupled to the ground terminal voltage VSS (for example, coupled between the ground terminal voltage VSS and the output terminal VOUT).

[0055] Figure 5 is a circuit schematic diagram of the output stage circuit of the fourth exemplary embodiment of the present invention. Refer to Figure 5 , this embodiment can be Figure 1 a specific implementation example of the output stage circuit 100 as shown. In this embodiment, the output stage circuit 500 includes a current source circuit 510, a bias circuit 520, an output circuit 530, and a transistor capacitor 550. The bias circuit 520 and the output circuit 530 can form a replica bias circuit. The current source circuit 510 includes transistors 511 to 515, 517, and an operational amplifier 516. The bias circuit 520 includes a transistor 521 and a reference resistor 522. The output circuit 530 includes a transistor 531, a load circuit 532, a transistor 533, and a transistor 534.

[0056] In this embodiment, the first end of transistor 511 is coupled to the operating voltage VDD. The second end of transistor 511 is coupled to the control end of transistor 511. The first end of transistor 512 is coupled to the operating voltage VDD. The control end of transistor 512 is coupled to the control end of transistor 511. The second end of transistor 512 is coupled to the first end of transistor 521. The first end of transistor 513 is coupled to the second end of transistor 511. The second end of transistor 513 is coupled to the ground voltage VSS. The first end of transistor 514 is coupled to the control end of transistor 513, the control end of transistor 514, and the current input terminal IS. The second end of transistor 514 is coupled to the ground voltage VSS. The control end of transistor 511 is coupled to the second end of transistor 511. The first end of transistor 515 is coupled to the operating voltage VDD. The control end of transistor 515 is coupled to the control end of transistor 511 and the control end of transistor 512. The second end of transistor 515 is coupled to the first end of transistor 517. The second end of transistor 517 is coupled to the ground voltage VSS. The control end of transistor 517 is coupled to the control end of transistor 513. The first input terminal of operational amplifier 516 is coupled to the second end of transistor 512. The second input terminal of operational amplifier 516 is coupled to the second end of transistor 515. The output terminal of operational amplifier 516 is coupled to the control end of transistor 521.

[0057] In this embodiment, the first end of transistor 521 is coupled to the second end of transistor 512. The second end of transistor 521 is coupled to the ground voltage VSS via reference resistor 522. The control end of transistor 531 is coupled to the control end of transistor 521. Load circuit 532 is coupled to the second end of transistor 531 and the output terminal VOUT. The first end of transistor 533 is coupled to the operating voltage VDD. The second end of transistor 533 is coupled to the first end of transistor 531. The first end of transistor 534 is coupled to the second end of transistor 531 and the output terminal VOUT. The second end of transistor 534 is coupled to the ground voltage VSS. The first end and the second end of transistor capacitor 550 are short-circuited and both are coupled to the ground voltage VSS. The second end of transistor capacitor 550 is further coupled to the second end of transistor 534. The control end of transistor capacitor 550 is coupled to the control end of transistor 521 and the control end of transistor 531.

[0058] It should be noted that the transistor 511, transistor 512, transistor 515, and operational amplifier 516 of the current source circuit 510 in this embodiment can be combined into a current mirror circuit in the form of an operational amplifier, and the control terminal of the transistor 521 in this embodiment is not coupled to the first terminal of the transistor 521. The two input terminals of the operational amplifier 516 in this embodiment are coupled to the two second terminals of the transistor 512 and the transistor 515 to lock the current flowing through the transistor 512 and the transistor 515. Moreover, the output terminal of the operational amplifier 516 in this embodiment is coupled to the control terminal of the transistor 521 to fix the voltage of the control terminal of the transistor 521. Therefore, the operational amplifier 516 in this embodiment can effectively lock the current I_M flowing through the transistor 521. More importantly, there can be more voltage headroom between the first terminal of the transistor 521 and the operating voltage VDD. In this way, the current I_M can be equal to or approximately equal to the input current input by the current input terminal IS.

[0059] In this embodiment, the transistors 513, 514, 517, 521, 531, 533, and the transistor capacitor 550 can be N-type transistors, and the transistors 511, 512, 515, 534 can be P-type transistors. The load circuit 532 can include a resistor 5321, and the present invention is not limited thereto. The control terminals of the transistor 533 and the transistor 534 can receive the switching signal SWN and the switching signal SWP, respectively. In some embodiments of the present invention, the switching signal SWN and the switching signal SWP can be the same switching signal, but the present invention is not limited thereto. In this embodiment, the on period of the transistor 533 and the on period of the transistor 534 do not overlap, but the present invention is not limited thereto.

[0060] In this embodiment, the bias circuit 520 and the output circuit 530 can be designed respectively such that the current ratio between the current I_M flowing through the bias circuit 520 and the current I_N flowing through the output circuit 530 is M:N, where M and N are positive integers. For example, the bias circuit 520 can include M transistors 521 connected in parallel, and the output circuit 530 can include N transistors 531 connected in parallel, where M and N are positive integers. Alternatively, the number of parallel resistors of the reference resistor 222 in the bias circuit 520 and the number of parallel resistors in the load circuit 532 of the output circuit 530 can be designed as M:N. Therefore, in this embodiment, as Figure 5After the voltage of the circuit node Va5 (the second terminal of transistor 521) as shown is set (i.e., setting current I_M), the voltages of circuit node Vb5 (the control terminal of transistor 521) and circuit node Vc5 (the second terminal of transistor 531) will be fixed. In other words, when current I_M changes, the voltage of output terminal VOUT can follow the voltage of circuit node Va5 to achieve the output stage function of adjusting the voltage level of the output voltage. Moreover, the output stage circuit 500 of this embodiment can provide a stable output voltage signal according to the input current input by current input terminal IS. It is worth mentioning that since bias circuit 520 and output circuit 530 have the same components and only differ in quantity, the voltage level of the output voltage can accurately track the set voltage of node Va5 without being affected by Process, Voltage, and / or Temperature.

[0061] In addition, the bases of transistors 511 - 515, 517, 521, 531, 533, 534, 550 of this embodiment can be coupled to their respective corresponding sources to reduce the substrate effect. Additionally, an electrostatic protection circuit can be provided on the path where output stage circuit 500 of this embodiment is coupled to operating voltage VDD (for example, coupled between operating voltage VDD and output terminal VOUT), and another electrostatic protection circuit can also be provided on the path where output stage circuit 500 of this embodiment is coupled to ground terminal voltage VSS (for example, coupled between ground terminal voltage VSS and output terminal VOUT).

[0062] Figure 6 is a circuit schematic diagram of the output stage circuit of the fifth exemplary embodiment of the present invention. Refer to Figure 6 , this embodiment can be Figure 1 a specific implementation example of the output stage circuit 100 as shown. In this embodiment, output stage circuit 600 includes current source circuit 610, bias circuit 620, output circuit 630, and transistor capacitor 650. Bias circuit 620 and output circuit 630 can form a Replica bias circuit. Current source circuit 610 includes transistors 611 - 614, operational amplifier 615, and reference resistor 616. Bias circuit 620 includes transistor 621 and reference resistor 622. Output circuit 630 includes transistor 631, load circuit 632, transistor 633, and transistor 634.

[0063] In this embodiment, the first end of transistor 611 is coupled to the operating voltage VDD. The second end of transistor 611 is coupled to the control end of transistor 611. The first end of transistor 612 is coupled to the operating voltage VDD. The control end of transistor 612 is coupled to the control end of transistor 611. The second end of transistor 612 is coupled to the ground terminal voltage VSS via a reference resistor 616. The first end of transistor 613 is coupled to the second end of transistor 611. The second end of transistor 613 is coupled to the ground terminal voltage VSS. The first end of transistor 614 is coupled to the control end of transistor 613, the control end of transistor 614, and the current input terminal IS. The second end of transistor 614 is coupled to the ground terminal voltage VSS. The control end of transistor 611 is coupled to the second end of transistor 611. The first input terminal of operational amplifier 616 is coupled to the second end of transistor 612. The second input terminal of operational amplifier 616 is coupled to the second end of transistor 621. The output terminal of operational amplifier 616 is coupled to the control end of transistor 621.

[0064] In this embodiment, the first end of transistor 621 is coupled to the second end of transistor 612. The second end of transistor 621 is coupled to the ground terminal voltage VSS via a reference resistor 622. The control end of transistor 631 is coupled to the control end of transistor 621. The load circuit 632 is coupled to the second end of transistor 631 and the output terminal VOUT. The first end of transistor 633 is coupled to the operating voltage VDD. The second end of transistor 633 is coupled to the first end of transistor 631. The first end of transistor 634 is coupled to the second end of transistor 631 and the output terminal VOUT. The second end of transistor 634 is coupled to the ground terminal voltage VSS. The first end and the second end of transistor capacitor 650 are short-circuited and both are coupled to the ground terminal voltage VSS. The second end of transistor capacitor 650 is further coupled to the second end of transistor 634. The control end of transistor capacitor 650 is coupled to the control end of transistor 621 and the control end of transistor 631.

[0065] It should be noted that the transistor 611, transistor 612, and operational amplifier 616 of the current source circuit 610 in this embodiment can be combined into a current mirror circuit of an operational amplifier type, and the control terminal of the transistor 621 in this embodiment is not coupled to the first terminal of the transistor 621. The two input terminals of the operational amplifier 616 in this embodiment are coupled to the two second terminals of the transistor 612 and the transistor 621 to lock the current flowing through the transistor 612 and the transistor 621. Moreover, the output terminal of the operational amplifier 616 in this embodiment is coupled to the control terminal of the transistor 621 to fix the voltage of the control terminal of the transistor 621. Therefore, the operational amplifier 616 in this embodiment can effectively lock the current I_M flowing through the transistor 621. More importantly, there can be more voltage headroom between the first terminal of the transistor 621 and the operating voltage VDD. In this way, the current I_M can be equal to or approximate the input current input by the current input terminal IS.

[0066] In this embodiment, the transistors 613, 614, 621, 631, 633, and the transistor capacitor 650 can be N-type transistors, and the transistors 611, 612, 634 can be P-type transistors. The load circuit 632 can include a resistor 6321, and the present invention is not limited thereto. The control terminals of the transistor 633 and the transistor 634 can receive the switching signal SWN and the switching signal SWP respectively. In some embodiments of the present invention, the switching signal SWN and the switching signal SWP can be the same switching signal, but the present invention is not limited thereto. In this embodiment, the on-period of the transistor 633 and the on-period of the transistor 634 are not overlapped, but the present invention is not limited thereto.

[0067] In this embodiment, the bias circuit 620 and the output circuit 630 can be designed respectively such that the current ratio between the current I_M flowing through the bias circuit 620 and the current I_N flowing through the output circuit 630 is M:N, where M and N are positive integers. For example, the bias circuit 620 can include M transistors 621 connected in parallel, and the output circuit 630 can include N transistors 631 connected in parallel, where M and N are positive integers. Alternatively, the number of parallel resistors of the reference resistor 622 in the bias circuit 620 and the number of parallel resistors in the load circuit 632 of the output circuit 630 can be designed as M:N. Therefore, in this embodiment, as Figure 6After the voltage of the circuit node Va6 (the second terminal of the transistor 621) as shown is set (i.e., the current I_M is set), the voltages of the circuit node Vb6 (the control terminal of the transistor 621) and the circuit node Vc6 (the second terminal of the transistor 631) will be fixed. In other words, when the current I_M changes, the voltage of the output terminal VOUT can follow the voltage of the circuit node Va6 to achieve the output stage function of adjusting the voltage level of the output voltage. Moreover, the output stage circuit 600 of this embodiment can provide a stable output voltage signal according to the input current input by the current input terminal IS. It is worth mentioning that since the bias circuit 620 and the output circuit 630 have the same components and only differ in quantity, the voltage level of the output voltage can accurately track the set voltage of the node Va6 without being affected by the process, voltage, and / or temperature.

[0068] In addition, the bases of the transistors 611-614, 621, 631, 633, 634, 650 of this embodiment can be coupled to their respective corresponding sources to reduce the substrate effect. Additionally, an electrostatic protection circuit can be provided on the path where the output stage circuit 600 of this embodiment is coupled to the operating voltage VDD (for example, coupled between the operating voltage VDD and the output terminal VOUT), and another electrostatic protection circuit can also be provided on the path where the output stage circuit 600 of this embodiment is coupled to the ground terminal voltage VSS (for example, coupled between the ground terminal voltage VSS and the output terminal VOUT).

[0069] In summary, the output stage circuit of the present invention can provide a corresponding and stable output voltage signal according to the input current, and the output stage circuit architecture of the present invention is a regulator-free design. The output stage circuit architecture of the present invention can have a flexible current conversion ratio through the circuit designs of the bias circuit and the output circuit, and thus can flexibly adjust the voltage level of the output voltage. It is worth mentioning that by replicating the bias circuit architecture, the voltage level of the output voltage can accurately track the set voltage without being affected by the process, voltage, and / or temperature. Moreover, the output stage circuit of the present invention can be additionally provided with an electrostatic protection circuit to provide good output stage circuit functions.

[0070] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An output stage circuit, characterized in that, Comprising: A current source circuit; A bias circuit, coupled between the current source circuit and the ground terminal voltage; And An output circuit, comprising: A first transistor, wherein the control terminal of the first transistor is coupled to the bias circuit; and A load circuit, coupled to the second terminal of the first transistor and the output terminal; A second transistor, wherein the first terminal of the second transistor is coupled to a working voltage, and the second terminal of the second transistor is coupled to the first terminal of the first transistor; and A third transistor, wherein the first terminal of the third transistor is coupled to the second terminal of the first transistor and the output terminal, and the second terminal of the third transistor is coupled to the ground terminal voltage, The bias circuit comprises: A fourth transistor, wherein the first terminal of the fourth transistor is coupled to the current source circuit, the second terminal of the fourth transistor is coupled to the ground terminal voltage, and the control terminal of the fourth transistor is coupled to the control terminal of the first transistor and the first terminal of the fourth transistor, The current source circuit comprises: A fifth transistor, wherein the first terminal of the fifth transistor is coupled to the working voltage; A sixth transistor, wherein the first terminal of the sixth transistor is coupled to the working voltage, the control terminal of the sixth transistor is coupled to the control terminal of the fifth transistor, and the second terminal of the sixth transistor is coupled to the bias circuit; A seventh transistor, wherein the first terminal of the seventh transistor is coupled to the second terminal of the fifth transistor and the control terminal of the fifth transistor, and the second terminal of the seventh transistor is coupled to the ground terminal voltage; and An eighth transistor, wherein the first terminal of the eighth transistor is coupled to the control terminal of the seventh transistor, the control terminal of the eighth transistor, and the current input terminal, and the second terminal of the eighth transistor is coupled to the ground terminal voltage.

2. The output stage circuit according to claim 1, characterized in that The second transistor is a P-type transistor, and the first transistor and the third transistor are N-type transistors.

3. The output stage circuit according to claim 1, characterized in that, The load circuit comprises a resistor and / or a capacitor.

4. The output stage circuit according to claim 1, characterized in that, The bias circuit comprises: A reference resistor, wherein the first terminal of the reference resistor is coupled to the current source circuit and the control terminal of the first transistor, and the second terminal of the reference resistor is coupled to the ground terminal voltage.

5. The output stage circuit according to claim 1, characterized in that The bias circuit comprises: A reference resistor, wherein the first terminal of the reference resistor is coupled to the second terminal of the fourth transistor and the control terminal of the first transistor, and the second terminal of the reference resistor is coupled to the ground terminal voltage.

6. The output stage circuit according to claim 1, wherein The fifth transistor and the sixth transistor are P-type transistors, and the seventh transistor and the eighth transistor are N-type transistors.

7. The output stage circuit according to claim 1, characterized in that, The current source circuit further comprises: A first operational amplifier, wherein the first input terminal of the first operational amplifier is coupled to the second terminal of the fifth transistor, the second input terminal of the first operational amplifier is coupled to the second terminal of the sixth transistor, and the output terminal of the first operational amplifier is coupled to the control terminal of the fifth transistor and the control terminal of the sixth transistor.

8. The output stage circuit according to claim 1, characterized in that The control terminal of the fifth transistor is coupled to the second terminal of the fifth transistor, and the output stage circuit further includes: A ninth transistor, wherein a first terminal of the ninth transistor is coupled to the operating voltage, a control terminal of the ninth transistor is coupled to the control terminal of the fifth transistor and the control terminal of the sixth transistor, and a second terminal of the ninth transistor is coupled to a reference resistor; and A second operational amplifier, wherein a first input terminal of the second operational amplifier is coupled to the second terminal of the ninth transistor, a second input terminal of the second operational amplifier is coupled to the second terminal of the fourth transistor, and an output terminal of the second operational amplifier is coupled to the control terminal of the fourth transistor and the control terminal of the first transistor.

9. The output stage circuit according to claim 8, characterized in that The ninth transistor is a P-type transistor.

10. The output stage circuit according to claim 8, characterized in that, The control terminal of the fifth transistor is coupled to the second terminal of the fifth transistor, and the output stage circuit further includes: A tenth transistor, wherein a first terminal of the tenth transistor is coupled to the operating voltage, a control terminal of the tenth transistor is coupled to the control terminal of the fifth transistor and the control terminal of the sixth transistor; An eleventh transistor, wherein a first terminal of the eleventh transistor is coupled to the second terminal of the tenth transistor, a control terminal of the eleventh transistor is coupled to the control terminal of the seventh transistor, and a second terminal of the eleventh transistor is coupled to the ground terminal voltage; and A third operational amplifier, wherein a first input terminal of the third operational amplifier is coupled to the second terminal of the tenth transistor, a second input terminal of the third operational amplifier is coupled to the second terminal of the sixth transistor, and an output terminal of the second operational amplifier is coupled to the control terminal of the fourth transistor and the control terminal of the first transistor.

11. The output stage circuit according to claim 10, wherein The tenth transistor is a P-type transistor, and the eleventh transistor is an N-type transistor.

12. The output stage circuit according to claim 1, wherein The current source circuit includes: A twelfth transistor, wherein a first terminal of the twelfth transistor is coupled to the operating voltage, and a control terminal of the twelfth transistor is coupled to the second terminal of the twelfth transistor; A thirteenth transistor, wherein a first terminal of the thirteenth transistor is coupled to the operating voltage, a control terminal of the thirteenth transistor is coupled to the control terminal of the twelfth transistor, and a second terminal of the twelfth transistor is coupled to a reference resistor; A fourth operational amplifier, wherein a first input terminal of the fourth operational amplifier is coupled to the second terminal of the thirteenth transistor, a second input terminal of the fourth operational amplifier is coupled to the second terminal of the fourth transistor, and an output terminal of the fourth operational amplifier is coupled to the control terminal of the fourth transistor; A fourteenth transistor, wherein a first terminal of the fourteenth transistor is coupled to the second terminal of the twelfth transistor, and a second terminal of the fourteenth transistor is coupled to the ground terminal voltage; and A fifteenth transistor, wherein a first end of the fifteenth transistor is coupled to a control end of the fourteenth transistor, a control end of the fifteenth transistor, and a current input terminal, and a second end of the fifteenth transistor is coupled to the ground terminal voltage.

13. The output stage circuit according to claim 12, characterized in that, The twelfth transistor and the thirteenth transistor are P-type transistors, and the fourteenth transistor and the fifteenth transistor are N-type transistors.

14. The output stage circuit according to claim 1, characterized in that, The control end of the second transistor receives a first switching signal, and the control end of the third transistor receives a second switching signal.

15. The output stage circuit according to claim 1, wherein An on period of the second transistor and an on period of the third transistor do not overlap.

16. The output stage circuit according to claim 1, characterized in that, Further comprising: A transistor capacitor, wherein a first end and a second end of the transistor capacitor are short-circuited and coupled to the ground terminal voltage, the second end of the transistor capacitor is further coupled to the second end of the third transistor, and a control end of the transistor capacitor is coupled to the control end of the first transistor and the bias circuit.

17. The output stage circuit according to claim 1, wherein A current ratio between a first current flowing through the bias circuit and a second current flowing through the output circuit is M:N, where M and N are positive integers.

18. The output stage circuit according to claim 1, characterized in that The bias circuit includes M fourth transistors connected in parallel, and the output circuit includes N first transistors connected in parallel, where M and N are positive integers.

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