Clock dividing circuit and phase synchronization method thereof, and electronic device

Abstract

The application provides a clock divider circuit, a phase synchronization method thereof and an electronic device. The clock divider circuit comprises: an electronic oscillator configured to generate a root clock signal of a first frequency; and a plurality of clock dividers connected to the electronic oscillator respectively, wherein the root clock signal is input into the plurality of clock dividers respectively, and the plurality of clock dividers are configured to generate a plurality of variable frequency clock signals of different frequencies according to the root clock signal of the first frequency and a preset variable frequency coefficient. In this scheme, the modification of the frequency division coefficient of one clock divider does not affect the clock signals of other clock dividers, and the phase synchronization between the clock signals can be maintained after frequency division, and the phase relationship is not lost due to the variable frequency process.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of clock circuit, in particular to a clock frequency divider circuit, a phase synchronization method thereof and an electronic device. BACKGROUND

[0002] In digital low-power technology, dynamic clock frequency and voltage scaling (DVFS) technology is one of the key technologies to achieve low power consumption. The core of realizing this technology lies in the reasonable planning of the clock tree. The traditional clock tree technology of series clock frequency divider, as shown in the figure, connects multiple clock dividers in series, and the clock output of one divider is used as the clock input of the next divider. This technology has complex clock constraints and multiple clock dependencies. Modification of one divider will cause a series of changes in subsequent clock signals. Figure 1 SUMMARY

[0003] The clock frequency divider circuit provided by the embodiments of the present application reduces clock dependencies, and modification of a clock divider does not affect other clock signals.

[0004] The clock frequency divider circuit provided by the embodiments of the present application reduces clock dependencies, and modification of a clock divider does not affect other clock signals.

[0005] An electronic oscillator is configured to generate a root clock signal of a first frequency.

[0006] A plurality of clock dividers are connected to the electronic oscillator, and the root clock signal is input into the plurality of clock dividers. The plurality of clock dividers are configured to generate a plurality of variable frequency clock signals of different frequencies according to the root clock signal of the first frequency and a preset frequency conversion coefficient.

[0007] In an embodiment, each clock divider includes a counter, and the counters of the plurality of clock dividers are configured to start counting from the same period of the root clock signal.

[0008] In an embodiment, each clock divider is configured to load a modified frequency conversion coefficient at a period corresponding to the least common multiple of the frequency conversion coefficients of the plurality of clock dividers.

[0009] In an embodiment, after loading the modified frequency conversion coefficient, the first rising edges of the plurality of variable frequency clock signals are aligned.

[0010] In an embodiment, each clock divider supports 0 frequency conversion processing, and each clock divider further includes a backup counter connected to the electronic oscillator. The backup counter is configured to count according to a specified frequency conversion coefficient during 0 frequency conversion processing.

[0011] ​The embodiment of the present application further provides a phase synchronization method of a clock frequency division circuit, the clock frequency division circuit comprising an electronic oscillator and a plurality of clock frequency dividers, the plurality of clock frequency dividers being connected to the electronic oscillator respectively, and the method comprising:

[0012] The electronic oscillator generates a root clock signal of a first frequency and transmits the root clock signal to the plurality of clock frequency dividers respectively;

[0013] Counters in the plurality of clock frequency dividers start counting from a same period of the root clock signal;

[0014] The plurality of clock frequency dividers generate a plurality of variable frequency clock signals of different frequencies according to the root clock signal of the first frequency and preset frequency division coefficients.

[0015] In an embodiment, the method further comprises: when the preset frequency division coefficients are modified, each clock frequency divider loads the modified frequency division coefficients at a period of a least common multiple of the frequency division coefficients of the plurality of clock frequency dividers.

[0016] In an embodiment, the method further comprises: after the modified frequency division coefficients are loaded, a first rising edge of the plurality of variable frequency clock signals of different frequencies is aligned.

[0017] In an embodiment, each clock frequency divider supports 0 frequency division processing, each clock frequency divider further comprises a backup counter connected to the electronic oscillator, and the method further comprises:

[0018] In 0 frequency division processing, the backup counter counts according to a specified frequency division coefficient.

[0019] The embodiment of the present application further provides an electronic device comprising a plurality of functional modules and any one of the above clock frequency division circuits, the clock frequency division circuit being connected to the plurality of functional modules and used for transmitting the plurality of variable frequency clock signals of different frequencies to the plurality of functional modules.

[0020] The technical scheme provided by the above embodiment of the present application is that the plurality of clock frequency dividers are connected to the electronic oscillator respectively, the root clock signal is input to the plurality of clock frequency dividers respectively, and the plurality of clock frequency dividers are used for generating the plurality of variable frequency clock signals of different frequencies according to the root clock signal of the first frequency and the preset frequency division coefficients. Since the plurality of clock frequency dividers are independent of each other and respectively receive the root clock signal for frequency division processing, the modification of the frequency division coefficient of one clock frequency divider does not affect the clock signal of another clock frequency divider, thereby reducing dependency and reducing frequency division complexity. BRIEF DESCRIPTION OF DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments of the present application will be briefly introduced.

[0022] Figure 1 A principle schematic diagram of a series clock frequency division circuit provided by an embodiment of the present application is shown in FIG. 1.

[0023] Figure 2 A schematic diagram of a clock frequency division circuit provided by an embodiment of the present application is shown in FIG. 2.

[0024] Figure 3 A waveform schematic diagram of a root clock signal and frequency-converted clock signals clk1, clk2 and clk3 is shown in FIG. 3.

[0025] Figure 4 A flowchart of a phase synchronization method of a clock frequency division circuit provided by an embodiment of the present application is shown in FIG. 4.

[0026] Figure 5 A schematic diagram of an electronic device provided by an embodiment of the present application is shown in FIG. 5. DETAILED DESCRIPTION

[0027] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

[0028] Similar labels and letters represent similar items in the following drawings, thus, once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. Meanwhile, in the description of the present application, the terms “first”, “second” and the like are only used for distinguishing description, and cannot be understood as indicating or implying relative importance.

[0029] Figure 2 A schematic diagram of a clock frequency division circuit provided by an embodiment of the present application is shown in FIG. 2. Figure 2 As shown in FIG. 2, the clock frequency division circuit 40 includes an electronic oscillator 10 and a plurality of clock frequency dividers 20.

[0030] The electronic oscillator 10 is used to generate a root clock signal of a first frequency. The root clock signal (clk_root) refers to the clock signal generated by the electronic oscillator 10, which is distinguished from the clock signal output by the clock frequency divider 20 below, and is called the root clock signal. The first frequency refers to the frequency of the root clock signal, which is distinguished from the frequency of the clock signal output by the clock frequency divider 20, and is called the first frequency.

[0031] The electronic oscillator 10 is an electronic component used to generate a repetitive electronic signal (usually a sine wave or square wave), and is an electronic circuit or device that converts direct current into an alternating current signal output with a certain frequency. The electronic oscillator 10 can be divided into RC oscillators, LC oscillators, and crystal oscillators. In order to obtain a root clock signal with a relatively stable frequency, in an embodiment, the electronic oscillator 10 can be a crystal oscillator.

[0032] A plurality of clock dividers 20 are connected to the electronic oscillator 10, and the root clock signal is input to each of the plurality of clock dividers 20. The plurality of clock dividers 20 are used to generate a plurality of variable frequency clock signals with different frequencies according to the root clock signal with the first frequency and a preset variable frequency coefficient.

[0033] As shown in Figure 2 , the plurality of clock dividers 20 can be in a "parallel" mode, and the plurality of clock dividers 20 are independent of each other. The root clock signal generated by the electronic oscillator 10 is input to each of the plurality of clock dividers 20. Each clock divider 20 generates a variable frequency clock signal with a second frequency according to the preset variable frequency coefficient and the root clock signal with the first frequency. The variable frequency clock signal refers to the clock signal output by the clock divider 20, and is referred to as a variable frequency clock signal for distinction. The variable frequency coefficients of the plurality of clock dividers 20 can be completely different or partially the same, so the frequencies of the variable frequency clock signals output by the plurality of clock dividers 20 can be different or partially the same. Since the plurality of clock dividers 20 are in a "parallel" mode, the modification of the frequency division coefficient of one clock divider 20 does not affect the output of the clock signal on the other branch.

[0034] The frequency division coefficient is used to represent the number of cycles of the root clock signal included in one cycle of the variable frequency clock signal. For example, the frequency division coefficients of the plurality of clock dividers 20 can be 2 division, 3 division, 4 division, and the like.

[0035] For example, Figure 2 , the frequency division coefficient of clk_div1 (the first clock divider 20) can be 2 division, and the output variable frequency clock signal is denoted as clk1; the frequency division coefficient of clk_div2 (the second clock divider 20) can be 3 division, and the output variable frequency clock signal is denoted as clk2; the frequency division coefficient of clk_div3 (the third clock divider 20) can be 4 division, and the output variable frequency clock signal is denoted as clk3. The waveforms of the root clock signal (clk_root) and the variable frequency clock signals clk1, clk2, and clk3 can be as shown in Figure 3 , one cycle of clk1 includes 2 cycles of the root clock signal, one cycle of clk2 includes 3 cycles of the root clock signal, and one cycle of clk3 includes 4 cycles of the root clock signal.

[0036] The clock frequency division circuit 40 provided by the above embodiments of the present application comprises a plurality of clock frequency dividers 20 connected to the electronic oscillator 10 respectively, and a root clock signal is input to the plurality of clock frequency dividers 20 respectively. The plurality of clock frequency dividers 20 are used to generate a plurality of frequency conversion clock signals with different frequencies according to the root clock signal with the first frequency and a preset frequency conversion coefficient. Since the plurality of clock frequency dividers 20 are independent of each other and each receives the root clock signal for frequency division processing, the modification of the frequency division coefficient of one clock frequency divider 20 does not affect the clock signal of the other clock frequency dividers 20, thereby reducing the dependency and lowering the frequency division complexity.

[0037] In an embodiment, each clock frequency divider 20 comprises a counter, and the counters of the plurality of clock frequency dividers 20 are used to start counting from the same period of the root clock signal. Figure 3 As can be seen, the counter div1_cnt inside the first clock frequency divider 20 returns to 0 every 2 periods (assuming that the counter is in the increment mode), the counter div2_cnt inside the second clock frequency divider 20 returns to 0 every 3 periods, and the counter div3_cnt inside the third clock frequency divider 20 returns to 0 every 4 periods, all of which start counting from the same period of the root clock signal, so that the rising edges of the first period are completely aligned.

[0038] Further, the frequency conversion clock signals clk1, clk2 and clk3 generated from the same root clock signal clk_root are not necessarily phase-aligned. For example, the definition of the in-phase of the frequency conversion clock signals clk1 and clk2 is that if clk1 and clk2 come from the same root clock signal clk_root, the rising edges of the two clocks are completely aligned when the frequency division coefficients of clk1 and clk2 are modified to the same value at any time.

[0039] To achieve this goal, two points are required: the counters inside the frequency dividers of clk1 and clk2 start counting from the same period; and when the frequency division coefficients between clk1 and clk2 need to be modified, the loading can only be performed at the period where the least common multiple of the two frequency dividers is located.

[0040] Therefore, the counters of the plurality of clock frequency dividers 20 are used to start counting from the same period of the root clock signal, and each clock frequency divider 20 is further used to load the modified frequency division coefficient at the period where the least common multiple of the frequency division coefficients of the plurality of clock frequency dividers 20 is located.

[0041] For example, if clk1 is 2-divided and clk2 is 3-divided, the counter inside clk1 resets every 2 cycles (assuming the counter is in increment mode); the counter of clk2 resets every 3 cycles. Then every 2*3=6 cycles, the two counters of clk1 and clk2 reset at the same time. Therefore, the frequency conversion factor loading of clk1 or clk2 can only be performed in this period of time when the two counters reset at the same time. At this time, the corresponding frequency dividers of clk1 and clk2 are not completely independent, and the frequency dividers processed in this way can be considered to be always in synchronization.

[0042] Similarly, for three frequency conversion clock signals, the frequency conversion factor loading can be performed in the period of the least common multiple of the frequency conversion factors of the three clock dividers 20, and so on. After the modified frequency conversion factor is loaded, the first rising edges of the multiple frequency conversion clock signals of different frequencies are aligned. For example, if clk1 is 2-divided and clk2 is 3-divided, at the end of the 6th cycle of the root clock signal, clk1 can be converted to 3-divided and clk2 can be converted to 4-divided, at this time, clk1 starts a new cycle and clk2 also starts a new cycle, so the first rising edges are aligned. Therefore, the phase synchronization between the frequency conversion clock signals and other clock signals can be maintained after frequency conversion, and the phase relationship will not be lost due to the frequency conversion process. The synchronization between the parallel clock trees is achieved by realizing the synchronization between the clock dividers.

[0043] In an embodiment, each clock divider supports 0-divided processing, and each clock divider further comprises a backup counter connected to the electronic oscillator, which is used to count according to a specified frequency conversion factor when the 0-divided processing is performed.

[0044] The frequency conversion factor of 0 represents that the clock signal output by the clock divider has the same frequency as the root clock signal. The backup counter is another counter of the clock divider, when the frequency conversion factor of a certain clock divider 20 is 0, the backup counter can count according to a specified frequency conversion factor at the same time when the 0-divided factor is loaded, and the specified frequency conversion factor can be 2-divided or other frequency conversion, so as to record the phase relationship and prevent the phase loss in the special case of 0-divided.

[0045] The technical scheme provided by the above embodiment ensures that any clock division process can be synchronized with other clock dividers 20, and the phase of each clock will not be synchronized due to frequency division, and the clock edge cannot be aligned. Further, the clock divider processes the 0-divided by enabling a backup counter to record the phase information, so that the 0-divided counter does not lose the phase.

[0046] Figure 4The clock dividing circuit 40 comprises an electronic oscillator 10 and a plurality of clock dividers 20, and the clock dividers 20 are connected to the electronic oscillator 10. Figure 2 The clock dividing circuit 40 is described in the corresponding embodiments. As shown in Figure 4 The phase synchronization method comprises steps S410-S430.

[0047] In step S410, the electronic oscillator 10 generates a root clock signal of a first frequency and transmits the root clock signal to the clock dividers 20.

[0048] In step S420, the counters in the clock dividers 20 start counting from the same cycle of the root clock signal.

[0049] In step S430, the clock dividers 20 generate a plurality of variable frequency clock signals of different frequencies according to the root clock signal of the first frequency and a preset frequency dividing coefficient.

[0050] The specific process of steps S410-S430 is described above in the description of the clock dividing circuit 40, which is not repeated here.

[0051] In an embodiment, the phase synchronization method of the clock dividing circuit 40 provided by the embodiments of the present application can further comprise: when the preset frequency dividing coefficient is modified, each clock divider 20 loads the modified frequency dividing coefficient at a cycle of a least common multiple of the frequency dividing coefficients of the clock dividers 20.

[0052] Since the counters in the clock dividers 20 start counting from the same cycle of the root clock signal, assuming that there are two clock dividers 20, one is 2 dividing and the other is 3 dividing, the least common multiple is 6, so the two clock dividers 20 can load the modified frequency dividing coefficient at the 6th cycle of the root clock signal. After loading the modified frequency dividing coefficient, the first rising edges of the plurality of variable frequency clock signals of different frequencies are aligned, realizing phase synchronization.

[0053] In an embodiment, each clock divider supports 0 dividing processing, and each clock divider further comprises a backup counter connected to the electronic oscillator, and the method further comprises: when the 0 dividing processing is performed, the backup counter counts according to a specified frequency dividing coefficient.

[0054] The frequency dividing coefficient of 0 represents that the clock signal output by the first divider is the same as the root clock signal. The specified frequency dividing coefficient can be 2 dividing or other dividing, thereby avoiding phase loss of 0 dividing.

[0055] The implementation process of the above method is detailed in the description of the clock divider circuit 40 above, and will not be repeated here.

[0056] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 5 As shown, the electronic device includes multiple functional modules 30 and a clock divider circuit 40 as described in the above embodiment. The clock divider circuit 40 is connected to multiple functional modules 30 and is used to send multiple frequency-converted clock signals of different frequencies to multiple functional modules 30.

[0057] Functional module 30 can be a central processing unit (CPU), a network processor (NP), a digital signal processor (DSP), or other programmable logic devices.

[0058] Because the multiple clock dividers 20 in the clock divider circuit 40 of this application embodiment adopt a "parallel" mode and are directly connected to the electronic oscillator 10 to receive the root clock signal generated by the electronic oscillator 10, the modification of the division coefficient of any one clock divider 20 will not affect the clock signal output of the clock dividers 20 in other branches, thus improving the stability of the electronic equipment. Furthermore, by introducing synchronization technology between the clock dividers 20, phase alignment between the divided clock signals is achieved, which can greatly optimize the clock structure of the DVFS (Dynamic Frequency Conversion and Transformer) digital circuit.

[0059] The apparatuses and methods disclosed in the several embodiments provided in this application can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatuses, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0060] In addition, each functional module in each embodiment of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0061] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the parts that contribute to the prior art or parts of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

Claims

1. A clock dividing circuit, characterized by comprising: The method comprises: an electronic oscillator for generating a root clock signal of a first frequency; a plurality of clock dividers, each connected to the electronic oscillator, the root clock signal being input to each of the plurality of clock dividers, the plurality of clock dividers being configured to generate a plurality of different frequency variable clock signals based on the root clock signal of the first frequency and a preset frequency conversion coefficient; wherein each of the clock dividers comprises a counter, the counters of the plurality of clock dividers being configured to start counting from a same cycle of the root clock signal; each of the clock dividers is configured to load a modified frequency conversion coefficient at a cycle corresponding to a least common multiple of the frequency conversion coefficients of the plurality of clock dividers, the frequency conversion coefficient being indicative of a number of cycles of the root clock signal included in a cycle of the variable clock signal; a first rising edge of the plurality of different frequency variable clock signals is aligned after the modified frequency conversion coefficient is loaded.

2. The clock division circuit of claim 1, wherein, each of the clock dividers supports 0 frequency conversion processing, each of the clock dividers further comprises a backup counter connected to the electronic oscillator, the backup counter being configured to count according to a specified frequency conversion coefficient during 0 frequency conversion processing.

3. A method of phase synchronization of a clock division circuit, characterized by, The clock divider circuit comprises an electronic oscillator and a plurality of clock dividers, each of the plurality of clock dividers being connected to the electronic oscillator, and the method comprises: the electronic oscillator generates a root clock signal of a first frequency and transmits the root clock signal to each of the plurality of clock dividers; counters in each of the plurality of clock dividers start counting from a same cycle of the root clock signal; each of the plurality of clock dividers generates a plurality of different frequency variable clock signals based on the root clock signal of the first frequency and a preset frequency conversion coefficient; when the preset frequency conversion coefficient is modified, each of the clock dividers loads a modified frequency conversion coefficient at a cycle corresponding to a least common multiple of the frequency conversion coefficients of the plurality of clock dividers, the frequency conversion coefficient being indicative of a number of cycles of the root clock signal included in a cycle of the variable clock signal; a first rising edge of the plurality of different frequency variable clock signals is aligned after the modified frequency conversion coefficient is loaded.

4. The method of claim 3, wherein, each of the clock dividers supports 0 frequency conversion processing, and each of the clock dividers further comprises a backup counter connected to the electronic oscillator, and the method further comprises: during 0 frequency conversion processing, the backup counter counts according to a specified frequency conversion coefficient.

5. An electronic device, comprising: The system comprises a plurality of functional modules and the clock divider circuit of claim 1 or 2, the clock divider circuit being connected to the plurality of functional modules and configured to transmit the plurality of different frequency variable clock signals to the plurality of functional modules.

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