Circuit Board

Abstract

The present invention is a circuit board. The circuit board comprises a carrier board, a circuit layer, a reinforcement layer, a flow blocker and a protective layer, wherein the circuit layer, the reinforcement layer and the flow blocker are arranged on the carrier board, the reinforcement layer has a receiving groove, the flow blocker is arranged in the receiving groove, the protective layer covers the circuit layer and the reinforcement layer, and the flow blocker is used to stop the protective layer to prevent the protective layer from overflowing beyond the overflow allowable boundary.

Description

Technical Field

[0001] The invention relates to a circuit board, in particular to a circuit board with a reinforcing layer and a flow-blocking component arranged outside a chip arrangement area. Background Art

[0002] See also Figure 1 A conventional circuit board 10 is provided with a predetermined chip setting area 11a and a circuit setting area 11b on a carrier board 11, a first axis X is extended along a first side 11c of the chip setting area 11a, a second axis Y is extended along a second side 11d of the chip setting area 11a, and a blank area 11e is formed between the first axis X and the second axis Y.

[0003] See also Figure 1 , a plurality of circuits 12 are arranged in the circuit setting area 11b, and the circuits 12 and the blank area 11e are covered with a protective layer 13. In the prior art, a fluid solder mask material is printed on the circuits 12 and the blank area 11e by screen printing technology to form the protective layer 13. The protective layer 13 also exposes the inner pins 12a and the outer pins 12b of each of the circuits 12. The inner pins 12a are arranged in the chip setting area 11a, and the inner pins 12a are used to bond the chip. However, since the protective layer 13 is still fluid before solidification, the unsolidified protective layer 13 will overflow toward the chip setting area 11a, and the protective layer 13 overflowing toward the chip setting area 11a will affect the subsequent process, or cause the circuit board 10 to fail to meet the specification requirements.

[0004] See also Figure 1 In addition, since the blank area 11e is only covered by the protective layer 13, the blank area 11e will be warped during the process of baking and curing the protective layer 13, or the blank area 11e will be warped during the process of thermally pressing the circuit board 10 and the chip. When the blank area 11e is warped, it will be disadvantageous for the processes of aligning, bonding and cutting the chip and the inner pins 12a. Summary of the invention

[0005] The main purpose of the present invention is to provide a reinforcing layer and a baffle with a receiving groove on a carrier, the baffle being arranged in the receiving groove, the reinforcing layer and the baffle can prevent the carrier from warping, the receiving groove is used to accommodate an uncured and excess protective layer, and the baffle arranged in the receiving groove can prevent the uncured protective layer accommodated in the receiving groove from overflowing out of the allowable overflow boundary.

[0006] A circuit board of the present invention comprises a carrier, a circuit layer, a reinforcement layer, a baffle and a protective layer. The carrier has a surface, and the surface comprises a chip setting area, a circuit setting area and a protective layer setting area. The chip setting area has a first boundary and a second boundary, and the first boundary is connected to the second boundary at a corner. The circuit setting area and the protective layer setting area are located outside the chip setting area, and the protective layer setting area partially overlaps with the circuit setting area. The protective layer setting area has a third boundary, a fourth boundary and a corner boundary, and two ends of the corner boundary are respectively connected to the third boundary and the fourth boundary. The third boundary corresponds to the first boundary, the fourth boundary corresponds to the second boundary, and the corner boundary corresponds to the corner. There is an exposed area between the chip setting area and the protective layer setting area, and a An allowable overflow boundary, a virtual axis passes through the corner, the allowable overflow boundary and the corner boundary, the circuit layer is arranged in the circuit setting area, the circuit layer has a plurality of circuits, the inner pins of each of the circuits are located in the exposed area and the chip setting area, the reinforcement layer is arranged in the protective layer setting area and the exposed area, the reinforcement layer has a receiving groove, the receiving groove exposes the surface of the carrier, the reinforcement layer is projected onto the surface to form a reinforcement layer projection area, the virtual axis passes through the reinforcement layer projection area, the baffle is arranged in the receiving groove, and the baffle is projected onto the surface to form a baffle projection area, the protective layer covers the circuit layer and the reinforcement layer, and the protective layer exposes the inner pins and the baffle located in the receiving groove, and the baffle is used to stop the protective layer to prevent the protective layer from overflowing the allowable overflow boundary.

[0007] Preferably, the baffle projection area is located between the overflow allowable boundary and the corner boundary.

[0008] Preferably, the baffle projection area has a first side edge and a second side edge, the first side edge is located between the corner boundary and the second side edge, and the second side edge is located between the corner and the overflow allowable boundary.

[0009] Preferably, the baffle projection area has a first side edge and a second side edge, the first side edge is located between the corner boundary and the second side edge, and the first side edge overlaps the overflow allowable boundary.

[0010] Preferably, the baffle projection area has a first side edge and a second side edge, the first side edge is located between the corner boundary and the second side edge, and the second side edge overlaps the overflow allowable boundary.

[0011] Preferably, the accommodating groove has a notch, the notch faces the wafer setting area, and the notch is located between the baffle and the wafer setting area.

[0012] Preferably, the virtual axis passes through the projection area of ​​the baffle.

[0013] Preferably, the virtual axis passes through the gap.

[0014] Preferably, the flow blocking member has at least one blocking groove, the blocking groove includes at least one flow guiding opening, and the flow guiding opening faces the protective layer.

[0015] Preferably, the distance between the corner boundary and the allowable overflow boundary is no more than 300 microns.

[0016] Preferably, the minimum distance between the outer wall of the baffle and the inner wall of the accommodating groove is no more than 900 microns.

[0017] Preferably, the baffle is selected from various three-dimensional geometric shapes.

[0018] The present invention sets the reinforcing layer and the baffle in the area where the circuit layer is not set, and increases the strength of the area where the circuit layer is not set by the reinforcing layer and the baffle to prevent the carrier from warping, and the uncured and excessive protective layer is accommodated by the receiving groove of the reinforcing layer, and the baffle arranged in the receiving groove blocks the uncured protective layer in the receiving groove, so that the uncured protective layer is retained in the receiving groove to prevent the uncured protective layer from overflowing the allowable overflow boundary, so that the circuit board meets the specification requirements, so as to facilitate the subsequent chip alignment, bonding and cutting processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 : A top view of a conventional circuit board.

[0020] Figure 2 : A top view of the circuit board of the present invention.

[0021] Figure 3 : A cross-sectional view of a circuit board of the present invention.

[0022] Figure 4 : A top view of the reinforcing layer and the baffle of the circuit board of the present invention.

[0023] Figure 5 : A partial enlarged view of an embodiment of a circuit board of the present invention.

[0024] Figure 6 : A partial enlarged view of another embodiment of the circuit board of the present invention.

[0025] Figure 7 : A top view of the reinforcing layer and the baffle of the circuit board of the present invention.

[0026] Figure 8 : A top view of the reinforcing layer and the baffle of the circuit board of the present invention.

[0027] Fig. 9: A top view of the reinforcing layer and the baffle of the circuit board of the present invention.

[0028] Fig.10 : A top view of the reinforcing layer and the baffle of the circuit board of the present invention.

[0029]

Main component symbol description

[0030] 10: Circuit board 11: Carrier board

[0031] 11a: chip setting area 11b: circuit setting area

[0032] 11c: first side 11d: second side

[0033] 11e: Blank area 12: Line

[0034] 12a: inner pin 12b: outer pin

[0035] 13: Protective layer 100: Circuit board

[0036] 110: carrier board 111: surface

[0037] 112: wafer placement area 112a: first boundary

[0038] 112b: second boundary 112c: corner

[0039] 113: Line setting area 114: Protective layer setting area

[0040] 114a: third boundary 114b: fourth boundary

[0041] 114c: Corner border 115: Revealed area

[0042] 116: Allowable overflow boundary 117: Reinforcement layer projection area

[0043] 118: flow blocking member projection area 118a: first side edge

[0044] 118b: second side edge 120: circuit layer

[0045] 121: Line 122: Inner pin

[0046] 130: reinforcement layer 131: receiving groove

[0047] 131a: inner wall 132: notch

[0048] 140: flow blocking member 141: outer side wall

[0049] 142: blocking groove 142a: diversion opening

[0050] 150: Protective layer L: Virtual axis

[0051] X: First axis Y: Second axis DETAILED DESCRIPTION

[0052] See also Figure 2 and Figure 3 A circuit board 100 of the present invention comprises a carrier 110, a circuit layer 120, a reinforcement layer 130, a baffle 140 and a protective layer 150. The carrier 110 has a surface 111. The surface 111 comprises a chip setting area 112, a circuit setting area 113 and a protective layer setting area 114. The circuit setting area 113 and the protective layer setting area 114 are located outside the chip setting area 112. In the present embodiment, the circuit setting area 113 partially overlaps with the chip setting area 112, and the protective layer setting area 114 partially overlaps with the circuit setting area 113. An exposed area 115 is provided between the chip setting area 112 and the protective layer setting area 114.

[0053] See also Figure 2 The chip setting area 112 has a first boundary 112a and a second boundary 112b, the first boundary 112a is connected to the second boundary 112b at a corner 112c, the protection layer setting area 114 has a third boundary 114a, a fourth boundary 114b and a corner boundary 114c, two ends of the corner boundary 114c are respectively connected to the third boundary 114a and the fourth boundary 114b, the third boundary 114a corresponds to the first boundary 112a, the fourth boundary 114b corresponds to the second boundary 112b, the corner boundary 114c corresponds to the corner 112c, an allowable overflow boundary 116 is defined between the corner boundary 114c and the corner 112c, the spacing between the corner boundary 114c and the allowable overflow boundary 116 is not greater than 300 microns, and the virtual axis L passes through the corner 112c, the allowable overflow boundary 116 and the corner boundary 114c.

[0054] See also Figure 2 and Figure 3 The circuit layer 120 is disposed in the circuit setting area 113 . The circuit layer 120 has a plurality of circuits 121 . The inner pins 122 of each circuit 121 are located in the exposed area 115 and the chip setting area 112 .

[0055] See also Figure 2 and Figure 4The reinforcing layer 130 is disposed in an area where the circuit layer 120 is not disposed. In the present embodiment, the reinforcing layer 130 is disposed in the protection layer setting area 114 and the exposed area 115. The appearance of the reinforcing layer 130 is selected from various three-dimensional geometric shapes. The reinforcing layer 130 has a receiving groove 131. The receiving groove 131 exposes the surface 111 of the carrier 110. The reinforcing layer 130 is projected onto the surface 111 to form a reinforcing layer projection area 117. The virtual axis L passes through the reinforcing layer projection area 117. In the present embodiment, the receiving groove 131 has a notch 132. The notch 132 faces the chip setting area 112. The notch 132 is located between the baffle 140 and the chip setting area 112. In the present embodiment, the virtual axis L passes through the notch 132.

[0056] See also Figure 2 and Figure 4 , the baffle 140 is disposed in the accommodating groove 131, preferably, the minimum spacing between the outer wall 141 of the baffle 140 and the inner wall 131a of the accommodating groove 131 is not greater than 900 microns, and the baffle 140 is projected onto the surface 111 to form a baffle projection area 118, and the baffle projection area 118 is located between the allowable overflow boundary 116 and the corner boundary 114c. In one embodiment, the baffle projection area 118 has a first side edge 118a and a second side edge 118b, and the first side edge 118a is located between the corner boundary 114c and the second side edge 118b, and the second side edge 118b is located between the corner 112c and the allowable overflow boundary 116. In this embodiment, the virtual axis L passes through the baffle projection area 118.

[0057] See also Figure 5 In another embodiment, similarly, the baffle projection area 118 has the first side edge 118a and the second side edge 118b, the first side edge 118a is located between the corner boundary 114c and the second side edge 118b, and the first side edge 118b overlaps with the allowable overflow boundary 116. In this embodiment, the virtual axis L passes through the baffle projection area 118.

[0058] See also Figure 6 In another embodiment, similarly, the baffle projection area 118 has the first side edge 118a and the second side edge 118b, the first side edge 118a is located between the corner boundary 114c and the second side edge 118b, and the second side edge 118b overlaps with the allowable overflow boundary 116. In this embodiment, the virtual axis L passes through the baffle projection area 118.

[0059] See also Figure 2 , Figure 3 and Figure 4The protective layer 150 covers the circuit layer 120 and the reinforcement layer 130, and the protective layer 150 exposes the inner pin 122 and the baffle 140 located in the receiving groove 131. In the process of forming the protective layer 150, the receiving groove 131 is used to accommodate the uncured and excess protective layer 150, and the baffle 140 is used to stop the uncured protective layer 150 to prevent the protective layer 150 from overflowing the allowable overflow boundary 116.

[0060] See also Figure 4 , Figures 7 to 10 The flow blocking member 140 is selected from various three-dimensional geometric shapes, see Figures 7 to 10 Preferably, the blocking member 140 has at least one blocking groove 142 , and the blocking groove 142 includes at least one guide opening 142 a , and the guide opening 142 a faces the protective layer 150 . The blocking groove 142 is used to accommodate the protective layer 150 overflowing toward the wafer setting area 112 .

[0061] The present invention increases the strength of the area where the circuit layer 120 is not provided by means of the reinforcing layer 130 and the baffle 140 disposed in the area where the circuit layer 120 is not provided, so as to prevent the carrier 110 from warping, and the uncured and excessive protective layer 150 is accommodated by the receiving groove 131 of the reinforcing layer 130, and the baffle 140 disposed in the receiving groove 131 blocks the uncured protective layer 150 that overflows into the receiving groove 131, so that the uncured protective layer 150 is retained in the receiving groove 131, so as to prevent the uncured protective layer 150 from overflowing out of the allowable overflow boundary 116, so that the circuit board 100 meets the specification requirements, so as to facilitate subsequent chip alignment, bonding and cutting processes.

[0062] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with the profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A circuit board, characterized in that: Include: A carrier having a surface, the surface including a wafer setting area, a circuit setting area and a protection layer setting area, the wafer setting area having a first boundary and a second boundary, the first boundary connecting the second boundary at a corner, the circuit setting area and the protection layer setting area being located outside the wafer setting area, and the protection layer setting area partially overlaps with the circuit setting area, the protection layer setting area having a third boundary, a fourth boundary and a corner boundary, two ends of the corner boundary connecting the third boundary and the fourth boundary respectively, the third boundary corresponding to the first boundary, the fourth boundary corresponding to the second boundary, the corner boundary corresponding to the corner, an exposed area between the wafer setting area and the protection layer setting area, an allowable overflow boundary defined between the corner boundary and the corner, and a virtual axis passing through the corner, the allowable overflow boundary and the corner boundary; A circuit layer is arranged in the circuit setting area, the circuit layer has a plurality of circuits, and the inner pins of each circuit are located in the exposed area and the chip setting area; A reinforcing layer is arranged in the protective layer setting area and the exposed area, the reinforcing layer has a receiving groove, the receiving groove exposes the surface of the carrier plate, the reinforcing layer is projected onto the surface to form a reinforcing layer projection area, and the virtual axis passes through the reinforcing layer projection area; A flow-blocking member is disposed in the accommodating groove, and the flow-blocking member is projected onto the surface to form a flow-blocking member projection area; and The protective layer covers the circuit layer and the reinforcement layer, and the protective layer exposes the inner pin and the blocking member located in the receiving groove, and the blocking member is used to stop the protective layer to prevent the protective layer from overflowing the allowable overflow boundary.

2. The circuit board according to claim 1, characterized in that: The blocking member projection area is located between the overflow allowable boundary and the corner boundary.

3. The circuit board according to claim 1, characterized in that: The blocking member projection area has a first side edge and a second side edge, the first side edge is located between the corner boundary and the second side edge, and the second side edge is located between the corner and the overflow allowable boundary.

4. The circuit board according to claim 1, characterized in that: The flow-blocking component projection area has a first side edge and a second side edge, the first side edge is located between the corner boundary and the second side edge, and the first side edge overlaps the overflow-allowing boundary.

5. The circuit board according to claim 1, characterized in that: The flow-blocking component projection area has a first side edge and a second side edge, the first side edge is located between the corner boundary and the second side edge, and the second side edge overlaps the overflow-allowing boundary.

6. The circuit board according to any one of claims 1 to 5, characterized in that: The accommodating groove has a notch, the notch faces the wafer setting area, and the notch is located between the flow blocking component and the wafer setting area.

7. The circuit board according to any one of claims 1 to 5, characterized in that: The virtual axis passes through the projection area of ​​the baffle.

8. The circuit board according to claim 6, characterized in that: The virtual axis passes through the gap.

9. The circuit board according to any one of claims 1 to 5, characterized in that: The flow blocking member has at least one blocking groove, and the blocking groove includes at least one flow guiding opening, and the flow guiding opening faces the protective layer.

10. The circuit board according to any one of claims 1 to 5, characterized in that: The distance between the corner boundary and the allowable overflow boundary is no greater than 300 micrometers.

11. The circuit board according to any one of claims 1 to 5, characterized in that: The minimum distance between the outer wall of the baffle and the inner wall of the accommodating groove is no more than 900 micrometers.

12. The circuit board according to any one of claims 1 to 5, characterized in that: The flow-blocking element is selected from various three-dimensional geometric shapes.

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