Device for generating an electrical signal indicative of temperature

Abstract

Disclosed is a device for generating an electrical signal indicative of temperature. The device includes: a first thin-film transistor (TFT) comprising a first source, a first gate, and a first drain, the first drain being configured to receive a reference current; and a second TFT comprising a second source, a second gate, and a second drain, the first gate and the second drain being configured to receive the same gate voltage. The first and second TFTs are configured such that the temperature dependency of the first TFT differs from the temperature dependency of the second TFT, such that the output current at the second TFT and the second drain is temperature-dependent. The temperature dependency of the output current can be controlled by selecting appropriate design parameters for the first and second TFTs. Also disclosed is a method for designing the device to generate an output current with a target temperature dependency.

Description

Technical Field

[0001] The present invention relates to a device for generating an electrical signal indicative of temperature. Background Art

[0002] Circuits and devices that can detect temperature changes are known. For example, the threshold voltage of a metal oxide semiconductor field effect transistor (MOSFET) can be used to detect temperature changes, or a thermistor can be used to generate an output current that increases with temperature. In both cases, the generated signal can be used for temperature regulation (for example, in an overheat protection circuit), but additional circuitry is required to reduce the output current in response to the detected increase in current. In addition, the design freedom for modifying the temperature dependence of the output signal in such circuits may be limited. Therefore, there is a need in the art for a circuit design that can be adapted to generate an output signal with a varying temperature dependence. Summary of the Invention

[0003] According to a first aspect of the present invention, a device is provided, comprising: a first thin-film transistor (TFT), comprising a first source, a first gate, and a first drain, the first drain being configured to receive a reference current; and a second TFT, comprising a second source, a second gate, and a second drain, the first gate and the second gate being configured to receive the same gate voltage, wherein the first TFT and the second TFT are configured such that the temperature correlation of the first TFT is different from the temperature correlation of the second TFT, so that the output current at the second TFT and the second drain depends on the temperature.

[0004] In some embodiments according to the first aspect, the first TFT and the second TFT each independently have a positive temperature correlation, and the temperature correlation of the first TFT is stronger than that of the second TFT, so that the overall temperature correlation of the output current is negative, so that the amplitude of the output current decreases as the temperature of the first TFT and the second TFT increases.

[0005] In some embodiments according to the first aspect, the first TFT and the second TFT each independently have a negative temperature correlation, and the temperature correlation of the second TFT is stronger than that of the first TFT, so that the overall temperature correlation of the output current is negative, so that the amplitude of the output current decreases as the temperature of the first TFT and the second TFT increases.

[0006] In some embodiments according to the first aspect, the first TFT and the second TFT are source-gated transistors.

[0007] In some embodiments according to the first aspect, an overlapping area S1 between the first source and the first gate is different from an overlapping area S2 between the second source and the second gate, so that the temperature dependency of the first TFT is different from the temperature dependency of the second TFT.

[0008] In some embodiments according to the first aspect, there is a threshold source length for each of the first TFT and the second TFT, beyond which the effect of increasing the source length on the temperature dependence of the current flowing through the TFT is negligible, wherein one of S1 and S2 is at or greater than the threshold source length, and the other of S1 and S2 is less than the threshold source length.

[0009] In some embodiments according to the first aspect, the first TFT and the second TFT have different compositions, such that a temperature dependency of the first TFT is different from a temperature dependency of the second TFT.

[0010] In some embodiments according to the first aspect, the first gate and the second gate comprise respective portions of a single gate, such that the single gate serves as a common gate for the first TFT and the second TFT.

[0011] In some embodiments according to the first aspect, the apparatus is configured to operate within a temperature range between an upper temperature threshold and a lower temperature threshold, wherein the upper temperature threshold and the lower temperature threshold are temperatures within a linear portion of the temperature-current curves of the first TFT and the second TFT, respectively. It should be understood that "linear" in this context should be interpreted as approximately or substantially linear, as in practice the relationship between temperature and current may not be completely linear.

[0012] In some embodiments according to the first aspect, the apparatus includes a constant current source configured to provide a constant current to the first drain as a reference current.

[0013] In some embodiments according to the first aspect, the device includes a load connected to the second TFT such that a current flowing through the load depends on the output current at the second drain.

[0014] In some embodiments according to the first aspect, the apparatus is configured to operate as a temperature sensor, wherein the magnitude of the output current at the second drain is indicative of the temperature of the first TFT and the second TFT.

[0015] In some embodiments according to the first aspect, the apparatus includes: a current measuring unit configured to measure the magnitude of the output current; and a temperature determining unit configured to determine the temperatures of the first TFT and the second TFT based on the current measured by the current measuring unit. The temperature determining unit may be configured to output the determined temperature, for example, as an audible or visual indication of the determined temperature.

[0016] In some embodiments according to the first aspect, the device includes a temperature controller configured to increase or decrease the temperature of the first TFT and the second TFT, wherein the second TFT is configured to provide an output current to the temperature controller, so that the magnitude of the heating or cooling effect generated by the temperature controller depends on the magnitude of the output current, wherein the first TFT, the second TFT and the temperature controller form a feedback loop, so that the device acts as a temperature regulation circuit, which is configured to maintain the environment in which the first TFT and the second TFT are located at a substantially constant temperature.

[0017] In some embodiments according to the first aspect, the temperature controller includes an oscillator circuit configured such that an oscillation frequency of the oscillator circuit depends on an amplitude of an output current provided by the second TFT.

[0018] In some embodiments according to the first aspect, a Joule heating effect on the first TFT and the second TFT due to the current flowing through the oscillator circuit depends on the magnitude of the output current provided by the second TFT.

[0019] In some embodiments according to the first aspect, the device includes a temperature control circuit, which is configured to receive the output of the oscillator circuit as a timing signal and generate a heating or cooling effect according to the oscillation frequency of the timing signal, so that the heating or cooling effect generated by the temperature control circuit depends on the temperature of the first TFT and the second TFT.

[0020] In some embodiments according to the first aspect, the oscillator circuit is a current-starved ring oscillator circuit, and the second TFT is one of a plurality of second TFTs included in the current-starved ring oscillator circuit, each of the plurality of second TFTs including a corresponding second gate configured to receive the same gate voltage as the first gate.

[0021] According to a second aspect of the present invention, there is provided a wearable electronic device comprising the apparatus according to the first aspect, wherein the apparatus is configured to regulate the temperature of at least a portion of the wearable electronic device.

[0022] According to a third aspect of the present invention, a method for designing an apparatus according to the first aspect is provided, the method comprising: determining a target temperature correlation of an output current at a second TFT; determining a temperature correlation of a first TFT and a temperature correlation of a second TFT required to provide an output current having the target temperature correlation; and determining characteristics of the first TFT required to provide the determined temperature correlation of the first TFT, and determining characteristics of the second TFT required to provide the determined temperature correlation of the second TFT.

[0023] In some embodiments according to the third aspect, the method may further comprise the step of manufacturing the designed device. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0025] Figure 1 A device for generating an electrical signal having a positive temperature correlation or a negative temperature correlation according to an embodiment of the present invention is shown;

[0026] Figure 2 FIG. 2 shows a plan view of a polysilicon Schottky barrier SGT according to an embodiment of the present invention;

[0027] Figure 3 shows a cross section of a polysilicon Schottky barrier SGT according to an embodiment of the present invention;

[0028] Figure 4 shows a cross section of an indium-gallium-zinc oxide (IGZO) SGT according to an embodiment of the present invention;

[0029] Figure 5 is a graph showing measured transfer characteristics of a polysilicon SGT according to an embodiment of the present invention;

[0030] Figure 6 is a graph showing measured output characteristics of a polysilicon SGT according to an embodiment of the present invention;

[0031] Figure 7 is a graph showing measured transmission characteristics of an IGZOSGT according to an embodiment of the present invention;

[0032] Figure 8 is a graph showing measured output characteristics of an IGZO SGT according to an embodiment of the present invention;

[0033] Figure 9 is a graph showing simulated transfer characteristics of a polysilicon SGT according to an embodiment of the present invention;

[0034] Figure 10 is a graph showing simulated output characteristics of a polysilicon SGT according to an embodiment of the present invention;

[0035] Figure 11 1. A top view of a current mirror (CM) type circuit using SGTs according to an embodiment of the present invention is shown, wherein a first transistor and a second transistor have the same source length S and the same source-drain gap d;

[0036] Figure 121. A top view of a CM type circuit using SGT according to an embodiment of the present invention is shown, wherein the first transistor and the second transistor have the same source length S and the same source-drain gap d;

[0037] Figure 13 1. A top view of a CM type circuit using SGT according to an embodiment of the present invention is shown, wherein the first transistor has a larger source length S and a larger source-drain gap d than the second transistor;

[0038] Figure 14 1. A top view of a CM type circuit using SGTs according to an embodiment of the present invention is shown, wherein a first transistor has a smaller source length S and a smaller source-drain gap d than a second transistor;

[0039] Figure 15 is a graph showing the measured dependence of the output current of a CM type circuit including an SGT on temperature according to an embodiment of the present invention;

[0040] Figure 16 is a graph showing simulated temperature dependence of output current of a CM type circuit using SGTs with different S combinations according to an embodiment of the present invention;

[0041] Figure 17 is a graph of output current relative to a reference current at various temperatures for a CM type circuit using an SGT according to an embodiment of the present invention;

[0042] Figure 18 A CM type circuit using an n-type SGT and a constant current source according to an embodiment of the present invention is shown;

[0043] Figure 19 The device according to an embodiment of the present invention is shown. The device includes a Figure 18 The ring oscillator circuit driven by the inverter stage shown;

[0044] Figure 20 is a diagram showing an embodiment of the present invention Figure 19 A graph showing the temperature dependence of the inverter stage delay of the ring oscillator circuit;

[0045] Figure 21 is a diagram showing an embodiment of the present invention Figure 19 A graph showing the output current of the inverter stage of the ring oscillator circuit as a function of temperature;

[0046] Figure 22 is a diagram showing an embodiment of the present invention Figure 19 A graph showing the gate voltage of the inverter stage of the ring oscillator circuit as a function of temperature;

[0047] Figure 23is a diagram showing an embodiment of the present invention Figure 19 a graph showing a switching delay of an inverter stage of a ring oscillator circuit as a function of temperature; and

[0048] Figure 24 A temperature sensing device according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0049] In the following detailed description, only certain exemplary embodiments of the present invention are shown and described by way of illustration. As will be appreciated by those skilled in the art, the described embodiments may be modified in various ways, all of which do not depart from the scope of the present invention. Therefore, the drawings and descriptions are to be regarded as illustrative rather than restrictive in nature. Throughout the specification, the same reference numerals represent the same elements.

[0050] Now refer to Figure 1 , shows an apparatus for generating an electrical signal indicative of temperature according to an embodiment of the present invention. The apparatus 100 comprises a first transistor 110 and a second transistor 120 connected in a similar manner to a current mirror circuit. The first transistor 110 and the second transistor 120 each comprise a source 111, 121, a gate 112, 122 and a drain 113, 123. The first transistor 110 and the second transistor 120 are arranged such that the potential difference between the source 111 and the gate 112 of the first transistor 110 is the same as the potential difference between the source 121 and the gate 122 of the second transistor 120. In the present embodiment, this is achieved by connecting the sources 111, 121 of the two transistors 110, 120 to a common reference voltage (ground in this case) and applying the same gate voltage V G This is achieved by providing gates 112 and 122 of the two transistors 110 and 120.

[0051] like Figure 1 The circuit shown is referred to herein as a "CM-type" circuit. The term "CM-type" should be understood to mean that the circuit includes two transistors connected in a similar manner to a current mirror, and does not imply that the circuit operates in exactly the same manner as a current mirror. As described below, embodiments of the present invention utilize the difference between the first transistor 110 and the second transistor 120 to generate a temperature-dependent output current, unlike a conventional current mirror in which a fixed ratio of a reference current is copied to the output at all temperatures.

[0052] In addition, in this embodiment, the apparatus 100 includes a circuit configured to provide a constant reference current I refThe output of the constant current source 130 is connected to the drain 113 of the first transistor 110, and is also connected to the gate 112 of the first transistor 110 and the gate 122 of the second transistor 120. In other words, the gate 112 of the first transistor 110 and the gate 122 of the second transistor 120 are both connected to the drain 113 of the first transistor 110. In this way, the gate 112 of the first transistor 110 and the gate 122 of the second transistor 120 are both provided with the same gate voltage V G , which in this embodiment is the voltage at the output of the constant current source 130. In other embodiments, a variable current source may be used instead of the constant current source 130. In such an embodiment, the gate 112 of the first transistor 110 and the gate 122 of the second transistor 120 may still be provided with the same gate voltage V G , for example by connecting the two gates 112, 122 to a common node, such as Figure 1 The embodiment shown.

[0053] In another embodiment, the sources 111 and 121 of the first transistor 110 and the second transistor 120 may be less than Figure 1 Instead of being directly connected to each other as shown, they may be connected to separate input terminals configured to provide the same voltage to both sources 111, 121. Similarly, in another embodiment, the gates 112, 122 of the first transistor 110 and the second transistor 120 may not be as large as the gates 112, 122 of the first transistor 110 and the second transistor 120. Figure 1 The gates 112 , 122 are not shown connected directly to each other, but may be connected to separate inputs configured to provide the same voltage to both gates 112 , 122 .

[0054] In a conventional current mirror, the first transistor and the second transistor have the same temperature-dependent current and voltage characteristics. Since the function of the current mirror is to replicate a reference current or a fixed ratio of a reference current at the output of the second transistor, using identical transistors ensures that the reference current is accurately replicated. However, the inventors have recognized that by using transistors 110, 120 that exhibit different temperature dependencies, the output current generated at the drain 122 of the second transistor 120 varies depending on the temperature, thereby indicating the temperature of the first transistor 110 and the second transistor 120. Therefore, in an embodiment of the present invention, the first transistor 110 and the second transistor 120 are configured so that the temperature dependency of the first transistor 110 is different from the temperature dependency of the second transistor 120. As a result, the load R flowing through the drain 123 connected to the second transistor 120 is L 140 output current I L In addition, the output current I can be controlled by appropriately selecting the relative temperature dependence of the first transistor 110 and the second transistor 120. Ltemperature dependence.

[0055] As described above, the device 100 can be used to generate an electrical signal indicating temperature. In this embodiment, the signal indicating temperature includes a current I L , whose magnitude depends on the temperature of the first transistor 110 and the second transistor 120. Such an apparatus 100 can be used in various applications, for example as a temperature sensor, or as part of a feedback loop in a temperature regulation circuit.

[0056] In some embodiments, the first transistor 110 and / or the second transistor 120 may be a source-gated transistor (SGT). Figure 2 FIG. 2 shows a plan view of a polysilicon Schottky barrier SGT 210 according to an embodiment of the present invention. Figure 2 The illustrated SGT 210 includes a source 211, a gate 212, a drain 213, and a field plate 214. In an SGT, the temperature dependency of the drain current depends on the source-gate overlap S, which may also be referred to as the "source length." In embodiments using thin-film transistors (TFTs) instead of SGTs, the equivalent parameter for the source length S in an SGT would be the channel length L. Therefore, when using SGTs, the relative temperature dependency of the output currents of the two transistors 110 and 120 can be controlled simply by selecting an appropriate source-gate overlap S. When using other types of transistors, the difference in the temperature dependency between the first and second transistors may be another characteristic. For example, some other types of thin-film transistors (TFTs) may have a temperature dependency that varies depending on the channel length L, and the desired PTD or NTD output current for a CM-type circuit may be obtained by selecting an appropriate channel length L. In some embodiments, a combination of different transistor types may be used. For example, in one embodiment, one of the first transistor 110 and the second transistor 120 may be a non-SGT TFT, and the other of the first transistor 110 and the second transistor 120 may be an SGT TFT.

[0057] In addition, in the embodiment of the present invention, the current I L The temperature dependence (TD) can be positive (PTD) or negative (NTD). Figure 2In the illustrated SGT 210, the current injected from the drain-side edge of the source 211 has a high PTD, and the PTD decreases as S increases because the charge injection from the bulk of the source 211 begins to dominate. Different temperature behaviors can be obtained by varying S in an otherwise identical device. Therefore, by appropriately selecting the output current temperature dependency of each of the first transistor 110 and the second transistor 120, embodiments of the present invention can provide a circuit having relatively few components that has an output current I L The height of the TD is configurable. If the relative widths of the first and second transistors are different, the output current of the CM circuit will be amplified or reduced depending on the width ratio of the transistors. However, the temperature dependence of the output current will still be determined by the S ratio between the two transistors.

[0058] A circuit (e.g., Figure 1 The circuit 100 shown may prove useful in a wide range of applications, such as temperature sensing circuits and self-regulating circuits for overheat protection in compact devices (e.g., wearable electronic devices or sensor systems). Such circuits may be particularly suitable for applications such as printed and flexible large-area electronic circuits because, by being able to generate current with desired PTD or NTD characteristics using a small number of components, embodiments of the present invention may help improve reliability and increase manufacturing yield.

[0059] although Figure 2 A polysilicon Schottky barrier SGT 210 is shown, but in other embodiments of the present invention, different types of transistors may be used as the first transistor 110 and the second transistor 120 . Figure 3 FIG. 4 shows a cross section of a low temperature polysilicon (LTPS) Schottky barrier SGT according to another embodiment of the present invention, and FIG. Figure 4 FIG. 4 shows a cross section of a tunnel contact SGT according to another embodiment of the present invention. Figure 4 In the embodiment of the present invention, the tunnel contact SGT is formed of indium-gallium-zinc oxide (IGZO), but in other embodiments, any other suitable material may be used. Figure 3 The LTPS SGT 310 includes a source 311 , a gate 312 , and a drain 313 . Figure 4 The IGZO SGT 410 also includes a source electrode 411 , a gate electrode 412 , and a drain electrode 413 , and further includes an insulating layer 414 disposed between a semiconductor active layer 415 and the source electrode 411 and the drain electrode 413 . Figure 3 Different charge injection paths are shown in the LTPS transistor 310 from the bulk of the source and at the drain-side edge of the source, with similar paths also applying to the IGZO transistor 410 .

[0060] In addition, although Figures 2 to 4 A specific TFT structure is shown in FIG. 1 , but in other embodiments of the present invention, a similar TFT structure may be used. Figures 2 to 4 The transistors shown may be different types of transistors, for example, using different materials and / or different structures. For example, although the insulating layer 414 is disposed over the source-drain gap and over the source electrode 411 and the drain electrode 413 in this embodiment, in other embodiments, the insulating layer 414 may be disposed only over the source electrode 411 and omitted from the source-drain gap and the drain electrode 413.

[0061] Table 1 below summarizes Figure 3 LTPS SGT310 and Figure 4 The device parameters of the IGZO SGT410 and the simulation parameters used in the technical computer-aided design (TCAD) simulation are shown. It should be understood that the dimensions and materials listed below are provided only as illustrative examples to aid in understanding the present invention and should not be interpreted as limiting. In other embodiments, the first transistor 110 and the second transistor 120 may use different materials and / or different dimensions than those listed in Table 1, or may include different types of TFTs with different temperature dependencies (for example, one transistor may be an SGT TFT and the other may be another type of TFT).

[0062]

[0063]

[0064] Table 1

[0065] Figure 5 and Figure 6 Graphs are shown that show the Figure 3 The measured electrical data of the SGT 310 is similar to that of the polysilicon SGT. Figure 5 Plotted for a constant drain voltage V of 5V D , Transmission characteristics for different combinations of S and d at temperatures T = 300K and T = 330K. Figure 6 Plotted for a constant gate voltage V of 12V G , at T = 300K and T = 330K, for Figure 5 Output characteristics of the same S and d combination. In this embodiment, the SGT operates in the depletion state due to the body doping and exhibits typical low voltage saturation and drain current independence with respect to d. In addition, as Figure 6As shown, the saturation drain current is virtually independent of the drain voltage. This can be a desirable property because the output current is thereby insensitive to changes in the resistance of the load on the circuit RL (or equivalently, to changes in the supply voltage). Due to the 2-D charge injection process in SGTs, the temperature dependence of the drain current is slightly higher for devices with shorter sources. In embodiments of the present invention, the drain current can be increased in the presence of a short source. Figure 1 This behavior is exploited in circuits like those shown to generate NTD and PTD currents.

[0066] Figure 7 and Figure 8 Graphs are shown that show the Figure 4 The measured electrical data of SGT 410 are similar to those of IGZO SGT. Figure 7 Plotted for a constant drain voltage V of 5V D , transmission characteristics for devices with S=45 μm and S=9 μm (both with d=50 μm) at temperatures T=300 K and T=330 K. Figure 7 It is shown that the drain current PTD is larger for devices with longer sources. Figure 8 Plotted for various values of gate voltage V G , at T = 330K, the output characteristics of the device for S = 45μm are shown, and it is shown that the device exhibits SGT behavior. The low-pressure behavior is superlinear, but does not prevent Figure 1 The function of the CM type circuit is shown, in which the transistor operates in saturation.

[0067] Figure 9 and Figure 10 The thermal and electrical co-simulation results of a polysilicon enhancement mode device according to an embodiment of the present invention using SilvacoAtlas v.5.24.1.R are shown. The device parameters used in the simulation are shown in Table 1. Figure 9 Plotted for a constant drain voltage V of 5V D , simulated transfer characteristics of polysilicon SGT devices with S = 1 μm, S = 5 μm and S = 25 μm at temperatures T = 300K and T = 340K. Figure 10 Plotted for a constant gate voltage V of 8V G , at T = 300K and T = 340K, for Figure 9 The output characteristics of the same device.

[0068] like Figure 9 and Figure 10 As shown, the simulated polysilicon SGT exhibits the same Figure 6 and Figure 7The simulated device with S = 1 μm has reduced drain current due to the small source area. In addition, the drain current in this device has a large PTD due to the dominance of injection from the source edge. The simulated devices with S = 5 μm and S = 25 μm behave very similarly, indicating that in these two devices, injection from the bulk of the source not only dominates, but also saturates as early as 5 μm as S increases. In other words, increasing the source length from 1 μm to 5 μm has a relatively large effect on the temperature dependence of the drain current, while continuing to increase the source length beyond 5 μm has a relatively small effect on the amplitude and temperature dependence of the output current.

[0069] Therefore, for any given device geometry and material combination, there exists a threshold source length S Tsat , at the threshold source length S Tsat The temperature dependence saturates at , so increasing the source length beyond the threshold S Tsat In an embodiment of the present invention, the source length S of one of the transistors 110 and 120 can be selected to be at or greater than the threshold source length S. Tsat , and select the source length S of another transistor to be smaller than the threshold source length S Tsat , to obtain a larger TD contrast between the first transistor 110 and the second transistor 120, thereby obtaining an output current with a stronger PTD or NTD. This can be achieved by selecting the source length S of the other transistor to be much smaller than the threshold source length S Tsat To obtain an output current with a strong temperature dependence (high PTD or high NTD).

[0070] Now refer to Figures 11 to 14 , showing the embodiment of the present invention Figure 1 A top view of a CM type circuit similar to that shown in FIG. Figure 1 An embodiment of Figures 11 to 14 Each circuit shown includes a first transistor and a second transistor, the first transistor including a first source 111, a first gate 112, and a first drain 113, and the second transistor including a second source 121, a second gate 122, and a second drain 123. Figures 11 to 14 In an embodiment, the first gate 112 and the second gate 122 comprise respective portions of a single gate terminal such that the single gate terminal serves as a common gate for the first transistor and the second transistor.

[0071] Figure 11 An embodiment is shown in which the first transistor and the second transistor have the same source length S and the same source-drain gap d. Figure 12Also shown are embodiments in which the first transistor and the second transistor have the same source length S and the same source-drain gap d, but the values of S and d are less than Figure 11 Since the first transistor and the second transistor have the same size in both cases, if the same materials are used in the first transistor and the second transistor, the circuit will behave as an ideal current mirror. However, in some embodiments of the present invention, the difference between the TD of the first transistor and the second transistor can be generated by using different materials and / or dopant levels in the first transistor and the second transistor. In such embodiments, the first transistor and the second transistor can have the same size as each other, or can have different sizes.

[0072] Figure 13 and Figure 14 An embodiment is shown in which the first transistor has a different S value and / or a different d value than the second transistor, with the result that the first transistor and the second transistor have different TDs. Figure 13 In , the first transistor has a larger source length S and a larger source-drain gap d than the second transistor. Figure 14 In FIG, the first transistor has a smaller source length S and a smaller source-drain gap d than the second transistor. Figure 13 and Figure 14 In the embodiment shown in FIG1 , the first transistor and the second transistor may be formed of the same material and still exhibit different TDs. However, in some embodiments, transistors with different source lengths S (e.g., Figure 13 and Figure 14 The examples shown) can also be formed of materials that are different from each other.

[0073] Now refer to Figure 15 and Figure 16 , shows measurement and simulation data of a CM-type circuit including SGTs with different source lengths S according to an embodiment of the present invention. Figure 15 is a graph showing the measured dependence of the output current of a CM type circuit including polysilicon SGT on temperature. Specifically, Figure 15 Data are plotted for the following items: including S M1 = 2μm first transistor (M1) and S M2 = 8μm second transistor (M2) circuit; including S M1 = 2μm first transistor (M1) and S M2 = 2μm second transistor (M2) circuit; and includes S Ml =8μm first transistor (M1) and S M2 = 2 μm of the second transistor (M2).

[0074] like Figure 15 As shown, the source length S of the first transistor is smaller than that of the second transistor (S M1 <S M2 ), the overall TD of the output current is negative, which means that the magnitude of the output current decreases as the temperature of the first transistor and the second transistor increases. This is because the PTD of the drain current of the first transistor is higher than the PTD of the drain current of the second transistor, which can be achieved by using a shorter source length S in the first transistor in the case of Schottky contacts SGT in silicon, as shown in FIG. Figure 14 In such an embodiment, when the first transistor is at a constant current I ref When driving, the increase in the overall temperature of the circuit will cause the gate voltage of both the first transistor and the second transistor to decrease. However, since the PTD of the second transistor is lower than that of the first transistor, the drain current of the second transistor (i.e., the output current of the circuit) decreases with temperature due to the longer source length S of the second transistor. Figure 15 In the plotted data, for S M1 =2μm and S M2 =8 μm, an average temperature sensitivity output current (TSOC) of -0.53% / K was observed.

[0075] In contrast, in other embodiments, the PTD output current may be obtained by using a second transistor having a shorter source length S than the first transistor, such as Figure 13 This is the case in the embodiment shown. Figure 15 In the plotted data, for S M1 =8μm and S M2 = 2 μm, a TSOC of +0.64% / K was observed. M1 =S M2 = 2 μm embodiment of the same transistor, TSOC is almost negligible at +0.06% / K, indicating that the device behaves close to an ideal current mirror.

[0076] Figure 16 is a graph showing simulated temperature dependence of output current of a CM type circuit using polysilicon SGTs with different S and d combinations according to an embodiment of the present invention. Figure 16 The output current temperature dependence in the simulation is based on DC conditions. Figure 15 The measured data are plotted compared to Figure 16 The plotted TCAD simulations show similar behavior but with larger TSOC due to the larger differences in source length S between devices. M1 =1μm and S M2= 25μm device, a TSOC of -1.83% / K was observed, while for S M1 =25μm and S M2 = 1 μm device, a TSOC of +3.15% / K was observed. M1 =S M2 =1, 5, 25 μm), a negligible TSOC of +0.002% / K was observed.

[0077] As mentioned above Figure 10 As mentioned above, there is a threshold source length S Tsat , exceeding the threshold source length S Tsat , further increasing the source length has little or no effect on the drain current. Figure 16 The device geometry and materials used in the TDAC simulation are plotted. The threshold S Tsat Occurs near S = 5 μm. For example, in this embodiment, the threshold S Tsat In addition, as described above, the source length S of one of the selection transistors 110 and 120 can be at or above the threshold source length S. Tsat , and select the source length S of another transistor to be smaller than the threshold source length S Tsat , to obtain a larger TD contrast between the first transistor 110 and the second transistor 120, thereby obtaining an output current with a stronger PTD or NTD.

[0078] Can be Figure 16 This effect is seen in M1 =1μm, S M2 =5μm and S M1 =1μm, S M2 = 25μm devices all produce strong NTD output current, while S M1 =5μm, S M2 = 25 μm device produces an output current with only very weak NTD. Similarly, S M1 =25μm, S M2 =1μm and S M1 =5μm, S M2 = 1μm devices all produce strong PTD output current, while S M1 =25μm, S M2 = 5 μm device produces an output current with only very weak PTD. Therefore, by selecting the source length S of one of the transistors 110, 120 to be at or above the threshold source length S Tsat , and select the source length S of another transistor to be smaller than the threshold source length S Tsat, a CM type circuit with greater sensitivity to temperature changes can be obtained.

[0079] In addition, if Figure 16 As shown, the temperature-current curve of the device exhibits an approximately linear portion between approximately 305K and 325K, and has nonlinear behavior outside this temperature range. In some embodiments, the device 100 is configured to operate within a temperature range between an upper temperature threshold and a lower temperature threshold, where the upper temperature threshold and the lower temperature threshold are temperatures within the linear portion of the temperature-current curves of the respective first transistor and the second transistor. In this way, the output current of the device 100 remains approximately linearly proportional to temperature throughout the entire designed operating range, making it easy to convert the amplitude of the output current into a temperature measurement. In some applications, it may be preferable to have an output current that varies with temperature in a nonlinear manner, for example to make the output current more sensitive to temperature changes within a specific temperature range.

[0080] Now refer to Figure 17 , which shows a graph of output current relative to reference current at various temperatures of a current mirror circuit using IGZO SGT according to an embodiment of the present invention. Figure 17 The plotted data shows that the IGZO circuit achieves the same net effect as the polysilicon based circuit described above.In this example, where the drain current of the first transistor has a higher PTD than the second transistor, a TSOC of -1.17% / K is achieved.

[0081] Now refer to Figure 18 and Figure 19 , shows a device including a ring oscillator circuit 1902 according to an embodiment of the present invention. Figure 18 Shown includes with Figure 1 A similar CM type arrangement is shown for connecting the first transistor 1810 and the second transistor 1820. In addition, Figure 18 The circuit includes a third transistor 1841, whose source is connected to the drain of the second transistor 1820. The voltage V at the source of the third transistor 1841 is out is supplied to one terminal of capacitor 1842, and the other terminal of capacitor 1842 is grounded.

[0082] Figure 19 Shown based on Figure 18 The device 1900 shown in the figure includes a Figure 1The first and second transistors 1901 are connected to a similar CM type circuit as shown, and include an oscillator core 1902 driven by an array of third transistors 1830, each third transistor 1830 receiving a current copied from the second transistor 1820. Each stage of the ring oscillator includes a signal amplification stage with a signal inversion property. In this embodiment, the signal amplification stage includes an inverting logic gate. Each stage includes Figure 18 The second transistor 1820 and the third transistor 1841 in the stage are arranged similarly. The third transistors 1841 in all stages can have their gates connected together as inputs and their drains connected together as outputs, and the output of each stage is used as the input of the next stage. In some embodiments, the third transistor 1841 can be used as an inverter, provided that the second transistor 1820 is replicated at the bottom of each stage, such as Figure 19 The lower row of transistors in the figure are shown below.

[0083] Oscillator circuit 1902 is positioned adjacent to first and second transistors 1901, such that the temperatures of first and second transistors 1901 are affected by the temperature of oscillator circuit 1902. The heating effect on the first and second transistors due to the oscillator circuit depends on the magnitude of the current flowing through the oscillator circuit and may also depend on the external temperature. In this manner, the oscillator circuit can increase the temperature of the first and second transistors through Joule heating by increasing the current flowing through the oscillator circuit.

[0084] In this embodiment, the oscillator circuit 1902 is a current-starved ring oscillator circuit, and the second transistor is one of a plurality of second transistors of the current-starved ring oscillator circuit. The oscillator circuit 1902 includes a plurality of stages, each stage including one of the second transistors, and each second transistor including a corresponding second gate electrode configured to receive the same gate voltage as the first gate. In this manner, the output current I L The output current at the drain of transistor M2 is replicated to each stage of oscillator circuit 1902, so that changes in the output current at transistor M2 produce corresponding changes in the current flowing through each stage of oscillator circuit 1902. When the output current at the drain of transistor M2 has a negative temperature dependency, current-starved ring oscillator 1902 adjusts its operating frequency based on the temperature of device 1900 through a negative feedback mechanism. Furthermore, when CM-type circuit 1901 is configured to generate an NTD output current, current-starved ring oscillator 1902 will self-regulate the operating speed and power consumption of any other circuits driven by oscillator circuit 1902. In some embodiments, a precise clock can be generated independently by a circuit configured to generate a stable clock signal that is independent of temperature.

[0085] Due to the negative temperature dependence of the output current at the drain of the second transistor M2, the first and second transistors 1901 and the oscillator circuit 1902 together form a feedback loop, so that the device acts as a temperature regulation circuit. In addition, the oscillator circuit 1902 may be powerful enough to affect the temperature of the surrounding environment of the device 1900, and / or may be configured to drive a separate heating or cooling device. In this way, the temperature regulation circuit can be used to maintain the surrounding environment of the device 1900 at a substantially constant temperature. For example, the device 1900 may be included in a wearable electronic device and used to regulate the temperature of at least a portion of the wearable electronic device. In some embodiments, the circuit can be integrated into clothing to help regulate the temperature of the person wearing the clothing.

[0086] For example, in some embodiments, Figure 19 The output of the illustrated oscillator circuit 1902 can be used as a timing signal to additional circuitry, such that the frequency of the timing signal provided to the additional circuitry varies depending on temperature. The additional circuitry can be configured to produce a heating or cooling effect that depends on the frequency of the timing signal provided by the operating circuitry 1902, and thus can be referred to as a temperature-controlled circuit. For example, the temperature-controlled circuitry can be configured to dissipate heat proportionally to its operating frequency, which is controlled by the timing signal from the oscillator circuit 1902. In this way, an increase in the temperature of the first and second transistors 1901 reduces the frequency of the timing signal generated by the oscillator circuit 1902, thereby reducing heat dissipation in the temperature-controlled circuitry and, thereby, reducing the temperature of the first and second transistors 1901. For example, this arrangement can ensure that the temperature-controlled circuitry remains within safe operating limits with respect to temperature, or can ensure that heat dissipated by the temperature-controlled circuitry does not raise the temperature to a level that could be harmful to a user or other components of the system.

[0087] In other embodiments, a similar Figure 19 The circuit shown in FIG. 1 shows an oscillator circuit in which the first and second transistors 1901 are configured to produce an output current at the drain of the second transistor M2 that has a positive temperature dependence. In this case, the oscillator circuit frequency increases with increasing temperature and can be used as a sensitive temperature sensor. For example, a counter can be used to determine the frequency of the oscillator circuit and convert it into a temperature measurement.

[0088] The oscillator circuit 1902 can be more generally referred to as a temperature controller because the function of the oscillator circuit 1902 is to control the temperature of the first and second transistors 1901 and the surrounding environment. Although the temperature controller is an oscillator circuit in this embodiment, in other embodiments, different types of temperature controllers can be implemented differently. For example, in some embodiments, Figure 1The CM circuit shown can be connected to a temperature controller in the form of a Peltier device, with the first and second transistors positioned on either the heating or cooling side of the Peltier device. The Peltier device can then heat or cool the first and second transistors and the surrounding environment, with the magnitude of the heating or cooling effect depending on the output current provided by the drain of the second transistor.

[0089] Now refer to Figure 20 , which illustrates an embodiment of the present invention Figure 19 The circuit includes Figure 18 A graph showing the temperature dependence of the inverter stage delay of the circuit.

[0090] Use the above Figure 16 The Atlas mixed-mode capability, where both SPICE (i.e. capacitors) and Atlas (physical modeling) devices are used to describe and simulate SPICE circuits, is similar to Figure 18 The device shown is simulated as Figure 19 A portion of the circuit shown. Figure 18 The common source amplifier shown uses a CM type circuit as an active load and is driven by a square wave. Transient simulation is used to study the time response of the circuit, and the simulation results are shown in Figures 20 to 23 Draw in.

[0091] like Figure 20 As shown, as the temperature of the device 1800 increases, the output current I out is reduced because, in this embodiment, the first transistor 1810 and the second transistor 1820 are configured to generate the NTD output current I out .

[0092] Therefore, the time taken to discharge the load capacitor 1842 (CL=10pF) increases, and Figure 19 The operating speed of the oscillator circuit 1902 in the device 1900 is reduced and thus the heat dissipation is reduced. This constitutes a negative feedback loop because the increase in the temperature of the device 1900 causes the heat generated by the oscillator circuit 1902 to decrease. Figure 21 is a graph showing the output current of the inverter stage 1800 of the oscillator circuit 1902 as a function of temperature, and shows that the output current decreases as the temperature of the oscillator circuit 1902 increases. Figure 22 is a graph showing the gate voltage of the inverter stage 1800 of the oscillator circuit 1902 as a function of temperature, and shows that the gate voltage decreases as the temperature of the oscillator circuit 1902 increases. Figure 23is a graph showing the switching delay of the inverter stage 1800 of the oscillator circuit 1902 as a function of temperature, and shows that the switching delay increases as the temperature rises, resulting in a decrease in the operating speed of the oscillator circuit 1902 .

[0093] Now refer to Figure 24 , shows a temperature sensing device according to an embodiment of the present invention. In this embodiment, the device 2400 is configured to function as a temperature sensor, wherein the magnitude of the output current at the second drain indicates the temperature of the first transistor and the second transistor. The device 2400 includes: a current measurement unit 2403 configured to measure the magnitude of the output current; and a conversion unit 2403 configured to convert the measured current into a measurement of the temperature of the first transistor and the second transistor. In this embodiment, the device 2400 is configured to send the temperature measurement to an output device 2404. The output device 2404 can output the temperature measurement value in a form understandable to a human user, such as an audio or visual format.

[0094] Although certain embodiments of the present invention have been described herein with reference to the accompanying drawings, it will be understood that many changes and modifications are possible without departing from the scope of the invention as defined in the appended claims.

Claims

1. A device for generating an electrical signal indicative of temperature, the device comprising: a first thin film transistor comprising a first source, a first gate, and a first drain, wherein the first drain is configured to receive a reference current; as well as a second thin film transistor comprising a second source electrode, a second gate electrode, and a second drain electrode, wherein the first gate electrode and the second gate electrode are configured to receive the same gate voltage; The first thin film transistor and the second thin film transistor are configured such that a temperature dependency of the first thin film transistor is different from a temperature dependency of the second thin film transistor, so that an output current at the second thin film transistor and the second drain depends on temperature.

2. The device according to claim 1, wherein The first thin film transistor and the second thin film transistor each independently have a positive temperature correlation, or each independently have a negative temperature correlation, and The temperature dependence of the first thin film transistor is stronger than that of the second thin film transistor, so the overall temperature dependence of the output current is negative, so that the amplitude of the output current decreases as the temperature of the first thin film transistor and the second thin film transistor increases.

3. The device according to claim 1, wherein The first thin film transistor and the second thin film transistor each independently have a negative temperature dependence, and The temperature dependence of the second thin film transistor is stronger than that of the first thin film transistor, so the overall temperature dependence of the output current is negative, so that the amplitude of the output current decreases as the temperature of the first thin film transistor and the second thin film transistor increases.

4. The device according to claim 1, 2 or 3, wherein: The first thin film transistor and the second thin film transistor are source-gated transistors.

5. The device according to claim 4, wherein An overlapping area S1 between the first source and the first gate is different from an overlapping area S2 between the second source and the second gate, so that the temperature dependency of the first thin film transistor is different from the temperature dependency of the second thin film transistor.

6. The device according to claim 5, wherein There is a threshold source length for each of the first thin film transistor and the second thin film transistor, beyond which the effect of increasing the source length on the temperature dependence of the current flowing through the thin film transistor is negligible, and Among them, one of S1 and S2 is at or greater than the threshold source length, and the other of S1 and S2 is less than the threshold source length.

7. The device according to claim 1, 2 or 3, wherein: The first thin film transistor and the second thin film transistor have different compositions, so that the temperature dependency of the first thin film transistor is different from the temperature dependency of the second thin film transistor.

8. The device according to claim 1, 2 or 3, wherein: The first gate and the second gate include respective portions of a single gate, such that the single gate serves as a common gate for the first and second thin film transistors.

9. The device according to claim 1, 2 or 3, wherein: The device is configured to operate within a temperature range between an upper temperature threshold and a lower temperature threshold, and wherein the upper temperature threshold and the lower temperature threshold are temperatures within a linear portion of the respective temperature-current curves of the first thin film transistor and the second thin film transistor.

10. The apparatus according to claim 1, 2 or 3, comprising: A constant current source is configured to provide a constant current to the first drain as the reference current.

11. The apparatus according to claim 1, 2 or 3, comprising: A load is connected to the second thin film transistor so that a current flowing through the load depends on the output current at the second drain.

12. The device according to claim 1, 2 or 3, wherein: The apparatus is configured to operate as a temperature sensor, wherein the magnitude of the output current at the second drain is indicative of the temperature of the first and second thin film transistors.

13. The apparatus according to claim 12, comprising: a current measuring unit configured to measure the amplitude of the output current; as well as A temperature determination unit is configured to determine temperatures of the first thin film transistor and the second thin film transistor according to the current measured by the current measurement unit.

14. The device according to claim 13, wherein The temperature determination unit is configured to output the determined temperature.

15. The device according to any one of claims 1 to 3, comprising: a temperature controller configured to increase or decrease the temperature of the first thin film transistor and the second thin film transistor, wherein the second thin film transistor is configured to provide the output current to the temperature controller such that the magnitude of the heating or cooling effect produced by the temperature controller depends on the magnitude of the output current, The first thin film transistor, the second thin film transistor and the temperature controller form a feedback loop, so that the device acts as a temperature regulation circuit, which is configured to maintain the environment of the first thin film transistor and the second thin film transistor at a substantially constant temperature.

16. The device according to claim 15, wherein The temperature controller includes an oscillator circuit configured such that an oscillation frequency of the oscillator circuit depends on a magnitude of an output current provided by the second thin film transistor.

17. The device according to claim 16, wherein The Joule heating effect on the first and second thin film transistors due to the current flowing through the oscillator circuit depends on the magnitude of the output current provided by the second thin film transistor.

18. The apparatus according to claim 16, comprising: a temperature control circuit configured to receive the output of the oscillator circuit as a timing signal and to generate a heating or cooling effect according to an oscillation frequency of the timing signal, such that the heating or cooling effect generated by the temperature control circuit depends on the temperatures of the first thin film transistor and the second thin film transistor.

19. The apparatus according to claim 16, 17 or 18, wherein The oscillator circuit is a current-starved ring oscillator circuit, and the second thin film transistor is one of a plurality of second thin film transistors included in the current-starved ring oscillator circuit, each of the plurality of second thin film transistors including a corresponding second gate configured to receive the same gate voltage as the first gate.

20. A wearable electronic device comprising the apparatus according to any one of claims 15 to 19, wherein: The apparatus is configured to regulate the temperature of at least a portion of the wearable electronic device.

21. A method of designing the device according to claim 1, the method comprising: determining a target temperature dependency of an output current at the second thin film transistor; determining a temperature dependency of the first thin film transistor and a temperature dependency of the second thin film transistor required to provide an output current having the target temperature dependency; as well as A characteristic of the first thin film transistor required to provide the determined temperature dependency of the first thin film transistor is determined, and a characteristic of the second thin film transistor required to provide the determined temperature dependency of the second thin film transistor is determined.

22. The method of claim 21, further comprising manufacturing the designed device.

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