Integrated assembly containing two-dimensional material

Abstract

Some embodiments include an integrated assembly having a semiconductor material with a more heavily doped region adjacent to a less heavily doped region. A two-dimensional material is located between the more heavily doped region and a portion of the less heavily doped region. Some embodiments include an integrated assembly that contains a semiconductor material, a metal-containing material over the semiconductor material, and a two-dimensional material between a portion of the semiconductor material and the metal-containing material. Some embodiments include a transistor having a first source / drain region, a second source / drain region, a channel region between the first source / drain region and the second source / drain region, and a two-dimensional material between the channel region and the first source / drain region.

Description

[0001] Related patent data

[0002] This application claims the benefit of U.S. Patent Application No. 16 / 542,078, filed on August 15, 2019, entitled "Integrated Assemblies Containing Two-Dimensional Materials", the entire content of which is incorporated herein by reference. Technical Field

[0003] Integrated assemblies containing two-dimensional materials. Background Art

[0004] Integrated assemblies can include dopants or other materials that can problematically diffuse or otherwise problematically migrate. For example, polysilicon can have different grain sizes, and this can enable dopants to diffuse to different depths within the polysilicon. The performance of highly integrated devices (e.g., transistors) can be affected by the diffusion depth of dopants. Different depths of diffusion across the layout of an integrated device can problematically cause non-uniformity in the performance of the integrated device; this can cause operational difficulties and even device failure. As another example, metals can migrate from metal silicides (or another metal source) and problematically alter the electrical characteristics of nearby regions.

[0005] There is a need to develop structures that can be readily incorporated into integrated assemblies to mitigate or even prevent the problematic migration of dopants and other materials. Brief Description of the Drawings

[0006] Figures 1 to 11 A diagrammatic cross-sectional side view of a region of an exemplary integrated assembly.

[0007] Figure 12 A diagrammatic schematic view of a region of an exemplary memory array. Detailed Description

[0008] Some embodiments include an integrated assembly having a two-dimensional material in a barrier region to prevent the improper migration of dopants and other materials. Refer to Figures 1 to 12 Describe exemplary embodiments.

[0009] Refer to Figure 1 , the integrated assembly 10 includes a semiconductor material 12 having a first region 14 over a second region 16. The first region is more heavily doped than the second region. A dashed line 15 is provided to diagrammatically illustrate a general barrier between the first region 14 and the second region 16.

[0010] The semiconductor material 12 may comprise any suitable composition; and in some embodiments may comprise, consist essentially of, or consist of one or more of silicon, germanium, III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, etc.; where the term III / V semiconductor material refers to a semiconductor material comprising elements selected from Groups III and V of the periodic table (where Groups III and V are the old nomenclature and are now referred to as Groups 13 and 15). In some applications, the semiconductor material 12 may comprise, consist essentially of, or consist of polysilicon.

[0011] The doped region 14 of the semiconductor material 12 may comprise any suitable dopant concentration; and in some embodiments may be heavily doped (i.e., doped to a concentration of at least about 10 20 atoms / cm 3 . The dopant within region 14 may be p-type or n-type; and in some embodiments may comprise one or more of boron, phosphorus, arsenic, etc.

[0012] The region 16 of the semiconductor material 12 may be doped to less than or equal to about 10 18 atoms / cm 3 , or even less than or equal to about 10 16 atoms / cm 3 ; and in some embodiments may be inherently doped (or in other words, may be effectively undoped).

[0013] A problem that can occur in conventional assemblies is that dopants can migrate from region 14 into region 16. If the semiconductor material 12 comprises a polycrystalline material (e.g., polysilicon), then the dopants can migrate along grain boundaries. In Figure 1 the illustrated embodiment, a barrier region 18 is provided to mitigate or even prevent improper dopant migration. Specifically, a barrier region is provided between the more heavily doped region 14 and a portion 20 of the less doped region 16 of the semiconductor material 12.

[0014] The barrier region 18 comprises a two-dimensional material 22. The term "two-dimensional material" refers to a material having one or more layers with stronger forces within each layer (ionic, covalent, etc.) than along the edges of the layer (e.g., between adjacent layers). The forces along the edges of the layer (e.g., between adjacent layers) will typically be primarily van der Waals forces. The two-dimensional material 22 may comprise any suitable number of layers; and in some embodiments may comprise a stack having 1 to 10 individual layers.

[0015] The two-dimensional material 22 may include any suitable composition; and in some embodiments may include one or more of carbon, boron, germanium, silicon, tin, phosphorus, bismuth, molybdenum, platinum, tungsten, and hafnium. In certain applications, the two-dimensional material 22 may include one or more of the following: graphene, graphyne, borophene, germanene, silicene, Si2BN, stanine, phosphorene, bismuthene, molybdenum disulfide, molybdenum diselenide, tungsten diselenide, and hafnium disulfide. In some embodiments, molybdenum disulfide may be advantageous because it can be very thin (less than ) such that electrons can tunnel through the molybdenum disulfide. Additionally, the band offset relative to polysilicon is small, so the tunneling barrier can be small in a configuration where molybdenum disulfide is adjacent to polysilicon. In some embodiments, it may be advantageous to utilize molybdenum disulfide and / or molybdenum diselenide within the two-dimensional material 22, and thus it can be easily fabricated as part of an integrated assembly.

[0016] An advantage of the two-dimensional material 22 is that it can block dopant migration while still allowing electrons to pass through it. Thus, even though the blocking region 18 is positioned to prevent dopants from migrating from the more heavily doped region 14 to the less doped portion 20, the portion 20 of the less doped region 16 remains electrically coupled to the more heavily doped region 14.

[0017] The blocking region 18 may include a single two-dimensional material 22 (as shown) or may include a laminate of two or more different two-dimensional materials.

[0018] The blocking region 18 can be disposed at any suitable location within the semiconductor material 12. In Figure 1 embodiments, the blocking region 18 is offset from the boundary 15 of the more heavily doped region 14 by an insertion region 24 of the semiconductor material 12. In other embodiments, the blocking region 18 may be directly against the more heavily doped region 14 of the semiconductor material 12, as shown in Figure 2 . Specifically, Figure 2 shows an integrated assembly 10a where the blocking region 18 is directly against the interface 15 along the bottom of the more heavily doped region 14. The blocking region 18 can act as a barrier during dopant activation (rapid thermal processing, laser annealing, etc.) to confine the desired junction depth.

[0019] In some embodiments, the blocking region 18 may include two or more two-dimensional materials 22 that may be directly against each other or may be spaced apart from each other by an insertion region of the semiconductor material 12. For example, Figure 3Shown is assembly 10b, where blocking region 18 includes a pair of two-dimensional materials 22a and 22b spaced apart from each other by an insertion region 26 of semiconductor material 12. The two-dimensional materials 22a and 22b can be the same composition as each other, or can be different compositions relative to each other. The two-dimensional materials 22a and 22b can have the same thickness as each other, or can have different thicknesses relative to each other. The advantage of utilizing two two-dimensional materials in blocking region 18 is that if the first material slightly leaks dopants into blocking region 18, then the second material can assist in preventing migration through blocking region 18.

[0020] In some embodiments, Figure 3 blocking region 18 can be considered to include a first portion and to include a second portion, the first portion including a first two-dimensional material 22a and the second portion including an additional two-dimensional material 22b. The first portion can be considered to be spaced apart from the second portion by an insertion region 26 of semiconductor material 12.

[0021] In some embodiments, in addition to or as an alternative to preventing dopant migration, blocking region 18 can also mitigate or prevent the migration of metal-containing materials. For example, Figure 4 shown is assembly 10c having a metal silicide 28 (or another metal-containing material) over semiconductor material 12. In a conventional configuration, metal can problematically migrate from the metal silicide (and / or from another metal-containing material) into semiconductor material 12, thereby altering the electrical properties of the semiconductor material and / or altering the electrical properties of other materials (not shown) adjacent to the semiconductor material. In the illustrated embodiment, blocking region 18 is provided adjacent to metal-containing material 28. Blocking region 18 includes a two-dimensional material 22 and can mitigate or prevent metal migration therethrough while enabling electrical coupling across the two-dimensional material (i.e., the blocking material). For example, in the illustrated embodiment, blocking region 18 is located between a portion 20 of semiconductor material 12 and metal-containing material 28 and can prevent metal from migrating into portion 20 while enabling electrical coupling between portion 20 and metal-containing material 28.

[0022] In some example embodiments, metal-containing material 28 can include, consist essentially of, or consist of a metal silicide. For example, metal-containing material 28 can include, consist essentially of, or consist of cobalt silicide. Cobalt can be the metal that migrates problematically, and the two-dimensional material 22 within blocking region 18 can advantageously prevent the improper migration of cobalt.

[0023] Figure 4 The configuration shown has blocking region 18 spaced apart from metal-containing material 28 by an insertion region 30 of semiconductor material 12. In other embodiments, the blocking region can be directly against metal-containing material 28, as Figure 5 shown relative to example integrated assembly 10d.

[0024] Figures 1 to 5 The blocking region 18 can be used in any suitable integrated assembly. In some embodiments, the blocking region can be incorporated into an integrated transistor, as described with reference to Figures 6 to 11 .

[0025] Referring to Figure 6 , the assembly 10e includes a transistor 32. The transistor 32 includes a first source / drain region 34, a second source / drain region 36, and a channel region 38 between the first source / drain region and the second source / drain region. Dashed lines 39 and 41 are provided to show the approximate boundaries of the source / drain regions 34 and 36.

[0026] The source / drain regions 34 and 36 can be heavily doped with an n-type dopant or a p-type dopant (e.g., one or more of phosphorus, boron, and arsenic); and the channel region 38 can be less heavily doped or can even be intrinsically doped. It is necessary to prevent dopants from migrating from the heavily doped source / drain regions into the channel region.

[0027] The regions 34, 36, and 38 are within the semiconductor material 12. The semiconductor material 12 can include any of the compositions described above with reference to Figure 1 ; and in some embodiments can include polysilicon, consist essentially of polysilicon, or consist of polysilicon.

[0028] The transistor 32 includes a gate material 40 that forms a conductive gate 42 adjacent to the channel region 38. The gate material 40 can include any suitable conductive composition; for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.).

[0029] The conductive gate 42 is spaced apart from the channel region 38 by a gate dielectric material 44. The gate dielectric material can include any suitable composition; and in some embodiments can include silicon dioxide, consist essentially of silicon dioxide, or consist of silicon dioxide.

[0030] The transistor 32 includes a blocking region 18 between the channel region 38 and the first source / drain region 34. The blocking region 18 includes the two-dimensional material 22 described above with reference to Figure 1 .

[0031] The illustrated transistor may represent a number of transistors extending across an integrated assembly. In some embodiments, the semiconductor material 12 comprises polysilicon. The grain size can vary throughout the polysilicon, which can cause dopants to diffuse (or otherwise migrate) along the grain boundaries. The dopants can migrate from the source / drain regions 34 toward the channel region 38, and the amount of migration can vary depending on the grain size in the various regions of the polycrystalline semiconductor material 12. Thus, it may be difficult to control the amount of migration across the transistors of the integrated assembly. The blocking region 18 can stop the migration of dopants at a predetermined level corresponding to the level of the blocking region, which can enable better control of the dopant profile compared to conventional configurations.

[0032] The illustrated transistor 32 is within an integrated assembly that includes a digital line DL1 located under and electrically coupled to the source / drain region 36. The digital line includes a conductive material 48. The material 48 can include any suitable conductive composition; for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.).

[0033] The digital line DL1 is supported by an insulating material 50. The material 50 can include any suitable composition; and in some embodiments can include silicon dioxide, consist essentially of silicon dioxide, or consist of silicon dioxide.

[0034] The transistor gate 42 is part of the word line WL1.

[0035] The word line WL1 extends into and out of the page relative to Figure 6 the cross-section, while the digital line DL1 extends along Figure 6 the cross-section. Thus, the word line extends generally orthogonally to the digital line (where the term "generally orthogonal" means orthogonal within reasonable tolerances of manufacturing and management).

[0036] The gate 42 can have any suitable configuration. In Figure 6 the illustrated embodiment, the gate is along both sides of the channel region 38. In other embodiments, the gate can be along only one side of the channel region, along three sides of the channel region, or can extend completely around the channel region (i.e., can be part of a gate-all-around configuration). Additionally, it should be understood that the embodiments can extend to any device geometry that can benefit from the blocking regions described herein, including finFET configurations and the like.

[0037] An insulating material 52 extends around the gate 42. The insulating material 52 can include any suitable composition; and in some embodiments can include silicon dioxide, consist essentially of silicon dioxide, or consist of silicon dioxide. In the illustrated embodiment, the gate dielectric material 44 is incorporated with the insulating material 52 to indicate that the gate dielectric material 44 and the insulating material 52 can include the same composition as each other. In other embodiments, the gate dielectric material 44 can include a composition different from that of the insulating material 52.

[0038] A conductive material 54 is located over the source / drain region 34. The conductive material 54 can include any suitable composition; and in some embodiments can include a metal-containing material (e.g., at least a portion of the material 54 can include copper, platinum, titanium, tantalum, etc., consist essentially of them, or consist of them) and / or a metal silicide (e.g., tantalum silicide, titanium silicide, cobalt silicide, etc.).

[0039] A storage element 56 is electrically coupled to the source / drain region 34 through the conductive material 54. The storage element 56 can be any suitable device having at least two detectable states; and in some embodiments can be, for example, a capacitor, a resistive memory device, a conductive bridging device, a phase change memory (PCM) device, a programmable metallization cell (PMC), etc.

[0040] The storage element 56 and the transistor 32 can be included together by a memory structure 58. In some embodiments, the memory structure 58 can be a dynamic random access memory (DRAM) cell, and the storage element 56 can be a capacitor. The illustrated memory structure 58 can represent a large number of memory structures of a memory array.

[0041] In the illustrated embodiment, the memory structure 58 is supported by a substrate 60. The substrate 60 can include a semiconductor material; and can include, for example, single-crystalline silicon, consist essentially of single-crystalline silicon, or consist of single-crystalline silicon. The substrate 60 can be referred to as a semiconductor substrate. The term "semiconductor substrate" means any configuration including a semiconducting material, which includes but is not limited to bulk semiconducting materials, such as (alone or in assemblies including other materials) semiconducting wafers, and (alone or in assemblies including other materials) semiconducting material layers. The term "substrate" refers to any supporting structure, including but not limited to the semiconductor substrates described above. In some applications, the substrate 60 can correspond to a semiconductor substrate containing one or more materials associated with integrated circuit fabrication. Such materials can include, for example, one or more of refractory metal materials, diffusion materials, insulator materials, etc.

[0042] A gap is provided between the substrate 60 and the insulating material 50 to indicate that other materials, structures, etc. can be present between the substrate 60 and the insulating material 50. Alternatively, the insulating material 50 can directly abut the upper surface of the substrate 60.

[0043] Figure 6 The embodiments of Figure 1 have an insertion region 24 between the first source / drain region 34 and the two-dimensional material 22 that has a configuration similar to Figure 7 (i.e., the first source / drain region 34 is spaced apart from the two-dimensional material 22 by an insertion region of the semiconductor material 12). In other embodiments, the bottom of the source / drain region 34 can directly abut the two-dimensional material 22, as shown in

[0044] In some embodiments, in addition to, or as an alternative to, a blocking region disposed between the first source / drain region and the channel region, a blocking region 18 can also be disposed between the second source / drain region 36 and the channel region 38. For example, Figure 8 shows an assembly 10g in which a first blocking region 18a is disposed between the source / drain region 34 and the channel region 12, and a second blocking region 18b is disposed between the source / drain region 36 and the channel region 12.

[0045] The first blocking region 18a includes a first two-dimensional material 22a, and the second blocking region 18b includes a second two-dimensional material 22b. The materials 22a and 22b can be the same in composition to each other, or can be different in composition relative to each other.

[0046] In the illustrated embodiments, the blocking regions 18a and 18b are spaced apart from the source / drain regions 34 and 36 by insertion regions 24a and 24b. In other embodiments, one or both of the insertion regions 24a and 24b can be omitted so that one or both of the blocking regions 18a and 18b directly abut the adjacent source / drain region.

[0047] In some embodiments, an additional blocking region can be disposed within the channel region 38, as shown in Figure 9 the assembly 10h. Specifically, in addition to the assembly 10h including a third blocking region 18c within the channel region 38, Figure 9 the assembly 10h of Figure 8 is the same as the assembly 10g of

[0048] The blocking region 18c includes a two-dimensional material 22c. The two-dimensional material 22c can be the same as one or both of the two-dimensional materials 22a and 22b, or can be different from both of the two-dimensional materials 22a and 22b. The two-dimensional material 22c within the channel region 38 can be used to prevent the dopant or other material from migrating across the channel region in the case where the dopant or other material can enter the channel region.

[0048] In some embodiments, an additional blocking region can be disposed adjacent to the metal-containing material 54, as shown in Figure 10 the assembly 10i. Specifically, in addition to the assembly 10i including a fourth blocking region 18d that is directly adjacent to the metal-containing material 54,Figure 10 The assembly 10i of Figure 9 is the same as the assembly 10h of . The blocking region 18d includes a two-dimensional material 22d. The two-dimensional material 22d can be the same as one or more of the two-dimensional materials 22a, 22b, and 22c; or can be different from all of the two-dimensional materials 22a, 22b, and 22c. The two-dimensional material 22d can be used to prevent a metal (e.g., cobalt) from migrating from the metal-containing material 54 into the semiconductor material 12 (and in the illustrated embodiment, can be used to prevent metal migration into the source / drain region 34).

[0049] Various embodiments can include any one of the blocking regions 18a to 18d, either alone or in combination with any other blocking region among the blocking regions 18a to 18d.

[0050] In some embodiments, one or more of the blocking regions 18a to 18d can include two or more two-dimensional materials. The two-dimensional materials within an individual blocking region can be directly adjacent to each other, or can be spaced apart from each other by an insertion region of the semiconductor material 12. Figure 11 An integrated assembly 10j is shown having blocking regions 18a to 18d each including two or more two-dimensional materials. Specifically, the blocking region 18a includes three two-dimensional materials 22a-1, 22a-2, and 22a-3; the blocking region 18b includes three two-dimensional materials 22b-1, 22b-2, and 22b-3; the blocking region 18c includes a pair of two-dimensional materials 22c-1 and 22c-2; and the blocking region 18d includes a pair of two-dimensional materials 22d-1 and 22d-2. The various two-dimensional materials can include any suitable composition; and can include, for example, any one of the compositions described for the blocking material 22 with respect to Figure 1 of . Figure 11 Two or more of the two-dimensional materials of can be the same composition as each other, and / or one or more of the two-dimensional materials can be a different composition from one or more of the other two-dimensional materials of .

[0051] The memory structure 58 can be incorporated into a memory array, such as a DRAM array. Figure 12 A region of an example DRAM array 70 is schematically illustrated. The DRAM array 70 includes a plurality of word lines (WL1 to WL4) and a plurality of digit lines (DL1 to DL4). The word lines can be considered to extend along the rows of the memory array, and the digit lines can be considered to extend along the columns of the memory array.

[0052] The memory structure 58 has a transistor 32. The gate 42 of the transistor is coupled to the word line. The source / drain region 36 of the transistor is coupled to the digit line, and the source / drain region 34 of the transistor is coupled to a storage element 56 corresponding to a capacitor. Each of the capacitors is coupled to a reference voltage 72. The reference voltage can be any suitable reference voltage, including, for example, ground, VCC / 2, etc.

[0053] Each of the memory structures 58 is uniquely addressed by a combination of one of the word lines and one of the digit lines.

[0054] The assemblies and structures discussed above can be used within an integrated circuit (where the term "integrated circuit" means an electronic circuit supported by a semiconductor substrate); and can be incorporated into an electronic system. Such an electronic system can be used, for example, in memory modules, device drivers, power modules, communication modems, processor modules, and special application modules, and can include multi-layer, multi-chip modules. The electronic system can be any one of a wide range of systems: for example, cameras, wireless devices, displays, chip sets, set-top boxes, games, lighting systems, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, airplanes, etc.

[0055] Unless otherwise specified, the various materials, substances, compositions, etc. described herein can be formed by any suitable method known now or to be developed, the methods including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0056] The terms "dielectric" and "insulating" can be used to describe materials having insulating electrical properties. The terms are considered synonymous in this disclosure. In some cases the term "dielectric" and in other cases the term "insulating" (or "electrically insulating") can be used within this disclosure to provide a variation in language to simplify the antecedent basis within the following claims, rather than to indicate any significant chemical or electrical differences.

[0057] The terms "electrically connected" and "electrically coupled" can both be used in this disclosure. The terms are considered synonymous. In some cases one term and in other cases the other term can be used within this disclosure to provide a variation in language to simplify the antecedent basis within the following claims.

[0058] The specific orientation of the various embodiments in the figures is for illustrative purposes only, and in some applications, the embodiments can be rotated relative to the shown orientation. The description provided herein and the appended claims relate to any structure having the described relationships between the various features, whether the structure is in the specific orientation of the figures or rotated relative to such orientation.

[0059] Unless otherwise specified, the cross-sectional views of the accompanying description show only the features within the cross-sectional plane and not the material behind the cross-sectional plane, in order to simplify the figures.

[0060] When a structure is said to be "on", "adjacent" to, or "against" another structure, the structure may be directly on the other structure or there may also be intervening structures. In contrast, when a structure is said to be "directly on" another structure, "directly adjacent" to another structure, or "directly against" another structure, there are no intervening structures. The terms "directly under", "directly over", etc. do not indicate direct physical contact (unless expressly stated otherwise), but instead indicate vertical alignment.

[0061] A structure (e.g., a layer, material, etc.) may be said to "vertically extend" to indicate that the structure generally extends upward from a underlying substrate (e.g., a wafer). The vertically extending structure may or may not extend generally orthogonally to the upper surface of the substrate.

[0062] Some embodiments include an integrated assembly having a semiconductor material having a more heavily doped region adjacent to a less heavily doped region. A two-dimensional material is located between the more heavily doped region and a portion of the less heavily doped region.

[0063] Some embodiments include an integrated assembly that includes a semiconductor material, a metal-containing material over the semiconductor material, and a two-dimensional material between a portion of the semiconductor material and the metal-containing material.

[0064] Some embodiments include a transistor having a first source / drain region, a second source / drain region, a channel region between the first source / drain region and the second source / drain region, and a two-dimensional material between the channel region and the first source / drain region.

[0065] By stipulation, the subject matter disclosed herein has been described in more specific or less specific language with respect to structural and method features. However, it should be understood that the claims are not limited to the specific features shown and described, since the components disclosed herein include example embodiments. Accordingly, the claims have the full scope as set forth in writing and should be interpreted properly according to the doctrine of equivalents.

Claims

1. An integrated assembly, comprising: A semiconductor material having a more heavily doped region adjacent to a less heavily doped region; And A diffusion barrier region located between the more heavily doped region and a portion of the less heavily doped region, the diffusion barrier region including multiple layers and having at least two different two-dimensional material layers, the two different two-dimensional material layers being spaced apart from each other by an insertion region.

2. The integrated assembly according to claim 1, wherein the semiconductor material is a polycrystalline material.

3. The integrated assembly according to claim 1, wherein the semiconductor material includes polysilicon.

4. The integrated assembly according to claim 3, wherein the more heavily doped region includes one or more of boron, phosphorus, and arsenic.

5. The integrated assembly according to claim 1, wherein the two-dimensional material includes one or more of carbon, boron, germanium, silicon, tin, phosphorus, bismuth, molybdenum, platinum, tungsten, and hafnium.

6. The integrated assembly according to claim 1, wherein the two-dimensional material includes one or more of the following: graphene, graphyne, borophene, germanene, silicene, Si2BN, stanene, phosphorene, bismuthene, molybdenum disulfide, molybdenum diselenide, tungsten diselenide, and hafnium disulfide.

7. The integrated assembly according to claim 1, wherein the two-dimensional material includes molybdenum.

8. The integrated assembly according to claim 1, wherein the two-dimensional material includes molybdenum disulfide and / or molybdenum diselenide.

9. An integrated assembly, comprising: A semiconductor material; A metal-containing material located on the semiconductor material; And A diffusion barrier region located between a portion of the semiconductor material and the metal-containing material, the diffusion barrier region including multiple layers and having at least two different two-dimensional material layers, the two different two-dimensional material layers being spaced apart from each other by an insertion region.

10. The integrated assembly according to claim 9, wherein the semiconductor material is a polycrystalline material.

11. The integrated assembly according to claim 9, wherein the metal-containing material is a metal silicide.

12. The integrated assembly according to claim 11, wherein the metal silicide is cobalt silicide.

13. The integrated assembly according to claim 9, wherein the two-dimensional material includes one or more of carbon, boron, germanium, silicon, tin, phosphorus, bismuth, molybdenum, platinum, tungsten, and hafnium.

14. The integrated assembly according to claim 9, wherein the two-dimensional material includes molybdenum.

15. The integrated assembly according to claim 9, wherein the two-dimensional material includes molybdenum disulfide and / or molybdenum diselenide.

16. A transistor, comprising: A first source / drain region; A second source / drain region; A channel region located between the first source / drain region and the second source / drain region; And A diffusion barrier region located between the channel region and the first source / drain region, the diffusion barrier region including multiple layers and having at least two different two-dimensional material layers, the two different two-dimensional material layers being spaced apart from each other by an insertion region, the two-dimensional material including one or more materials selected from the group consisting of carbon, boron, tin, bismuth, molybdenum, platinum, tungsten, and hafnium.

17. The transistor according to claim 16, wherein at least one layer of the two-dimensional material has a thickness in the range of about 0.5 nm to about 5 nm.

18. The transistor according to claim 16, wherein the first source / drain region abuts directly against the diffusion barrier region.

19. The transistor according to claim 16, wherein the first source / drain region is spaced apart from the diffusion barrier region.

20. The transistor according to claim 16, wherein the diffusion barrier region is a first diffusion barrier region, and the transistor further includes a second diffusion barrier region between the second source / drain region and the channel region.

21. The transistor according to claim 20, further including a third diffusion barrier region in the channel region.

22. The transistor according to claim 16, wherein the first source / drain region, the second source / drain region, and the channel region extend within a semiconductor material.

23. The transistor according to claim 16, wherein the two-dimensional material further includes one or more of germanium, silicon, and phosphorus.

24. The transistor according to claim 16, wherein the two-dimensional material includes molybdenum.

25. The transistor according to claim 16, wherein the two-dimensional material includes molybdenum disulfide and / or molybdenum diselenide.

26. A memory structure including the transistor according to claim 16, the memory structure including a storage element coupled to one of the first source / drain region and the second source / drain region, and including a digital line coupled to the other of the first source / drain region and the second source / drain region.

27. A transistor including: a first source / drain region; a second source / drain region; a channel region located between the first source / drain region and the second source / drain region, the first source / drain region, the second source / drain region, and the channel region extending within a semiconductor material; and a diffusion barrier region located between the channel region and the first source / drain region, the diffusion barrier region including multiple layers and having at least two different two-dimensional material layers spaced apart from each other by an insertion region, wherein the semiconductor material is a polycrystalline material.

28. The transistor according to claim 27, wherein the semiconductor material includes polysilicon.

29. A transistor including: a first source / drain region; a second source / drain region; a channel region located between the first source / drain region and the second source / drain region; and a first diffusion barrier region located between the channel region and the first source / drain region, the first diffusion barrier region including multiple layers and having at least two different two-dimensional material layers spaced apart from each other by an insertion region; and a metal-containing material adjacent to the first source / drain region and spaced apart from the first source / drain region by a second diffusion barrier region.

30. The transistor according to claim 29, wherein the metal-containing material is a metal silicide.

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