One-time power-on detection circuit

Abstract

The present invention belongs to the technical field of integrated circuits, and specifically relates to a power-on detection circuit. A one-time open power-on detection circuit includes a voltage detection circuit, which has a power supply terminal and a power-on reset signal terminal; the voltage detection circuit also includes: a comparator, the same-phase input terminal is connected to the power supply terminal via a first resistor, the reverse input terminal is connected to the detection point voltage terminal, the output terminal is the power-on reset signal terminal, and the control terminal is connected to the power-on initialization signal terminal; a first MOSFET tube, the gate is connected to the power-on initialization signal terminal, the drain is connected to the first resistor via a second resistor, and the source is grounded. After the chip initialization work is completed, the present invention can put the voltage detection circuit into a low power consumption mode, thereby avoiding the static power consumption of the voltage detection circuit.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a power-on detection circuit. Background Art

[0002] In ASIC and MCU circuit design, the devices that are just powered on have initialization actions. In the initialization action, the data in the non-volatile registers will be transferred to various status registers, such as storing the Band Gap configuration in the BGR status register to configure the reference voltage value after power-on; storing the OSC configuration in the OSC status register to configure the OSC frequency; storing the LDO configuration in the LDO register to configure the VDD power supply voltage of the digital power supply, etc.

[0003] However, the initialization action may cause errors in the transferred data due to the following reasons:

[0004] 1. The application environment, such as the power supply environment, is abnormal. When performing this action, the power supply jitter is too large;

[0005] 2. In the low-power design, no power supply detection is performed, resulting in the action being performed at a lower power supply voltage;

[0006] 3. The read conditions of some designs in the non-volatile registers are too strict, resulting in data reading errors in the non-volatile registers.

[0007] When errors such as the above occur, it will result in:

[0008] 1. After power-on, the analog parameters are abnormal, such as abnormal device parameters such as Vref, VDD or OSC, which causes the chip operating voltage to be too high, the chip to burn out or the power consumption to be too high;

[0009] 2. Abnormalities in the digital status register lead to digital logic function errors, etc.

[0010] In order to prevent the above problems, a power-on / power-off protection circuit with voltage detection is generally added to the ASIC and MCU circuit design to make the chip work at a suitable voltage during initialization. Although the voltage detection circuit used in the prior art can avoid the above problems, it will cause static power consumption. Summary of the invention

[0011] The present invention aims to provide a one-time power-on detection circuit, which can avoid errors in initialization actions but will cause technical problems of static power consumption.

[0012] A one-time power-on detection circuit includes a voltage detection circuit having a power supply terminal and a power-on reset signal terminal;

[0013] The voltage detection circuit also includes:

[0014] A comparator, wherein the in-phase input terminal is connected to the power supply terminal via a first resistor, the inverting input terminal is connected to the detection point voltage terminal, the output terminal is the power-on reset signal terminal, and the control terminal is connected to the power-on initialization signal terminal;

[0015] A first MOSFET tube, with a gate connected to the power-on initialization signal terminal, a drain connected to the first resistor via a second resistor, and a source grounded.

[0016] When the chip is powered on, the power-on initialization signal inputted by the power-on initialization signal terminal is at a high level, and the voltage detection circuit enters the working mode when:

[0017] VDD>Vref*(R2+R1) / R2

[0018] When the power-on reset signal terminal is flipped, the chip starts initialization work;

[0019] Wherein, VDD represents the voltage of the power supply terminal, Vref represents the detection point voltage input by the detection point voltage terminal, R1 represents the first resistor, and R2 represents the second resistor;

[0020] When the chip initialization work is completed, the power-on initialization signal input to the power-on initialization signal terminal is at a low level, and the voltage detection circuit enters a low power consumption mode.

[0021] The first MOSFET tube is an N-channel MOSFET tube.

[0022] The power-on initialization signal inputted by the power-on initialization signal terminal is provided by an external digital circuit, and the following circuit structure may also be adopted:

[0023] The voltage detection circuit also includes:

[0024] a delay device, whose input end is connected to the output end of the comparator;

[0025] A trigger, a clock input end is connected to the output end of the delay device, a signal input end is grounded, and a signal output end is the power-on initialization signal end.

[0026] When the chip is powered on, a high level is input to the set end of the trigger, and the power-on initialization signal input to the power-on initialization signal end is a high level, and the voltage detection circuit enters the working mode. After the delay device delays for a preset time, the voltage signal at the output end of the delay device flips, and the trigger is actuated. The signal output end of the trigger outputs a low level, that is, the power-on initialization signal input to the power-on initialization signal end is a low level, and the voltage detection circuit enters the low power consumption mode.

[0027] The delay time of the delay device is not less than the initialization working time of the chip.

[0028] A one-time power-on detection circuit includes a voltage detection circuit having a power supply terminal and a power-on reset signal terminal;

[0029] The voltage detection circuit also includes:

[0030] a second MOSFET tube, the gate of which is connected to the power-on initialization signal terminal, the drain of which is connected to the power supply terminal, the source of which is connected to one end of a third resistor, and the other end of the third resistor is grounded via a fourth resistor;

[0031] a third MOSFET tube, with a gate connected to the other end of the third resistor, a drain connected to the power supply terminal via a fifth resistor, and a source grounded;

[0032] An inverter, whose input end is connected to the drain of the third MOSFET tube, and whose output end is the power-on reset signal end.

[0033] When the chip is powered on, the power-on initialization signal inputted by the power-on initialization signal terminal is at a low level, and the voltage detection circuit enters the working mode when:

[0034] VDD>Vth*(R3+R4) / R4

[0035] When the power-on reset signal terminal is flipped, the chip starts initialization work;

[0036] Wherein, VDD represents the voltage of the power supply terminal, Vth represents the threshold voltage of the third MOSFET tube, R3 represents the third resistor, and R4 represents the fourth resistor;

[0037] When the chip initialization work is completed, the power-on initialization signal input to the power-on initialization signal terminal is at a high level, and the voltage detection circuit enters a low power consumption mode.

[0038] The second MOSFET tube and the third MOSFET tube are both N-channel MOSFET tubes.

[0039] The power-on initialization signal input to the power-on initialization signal terminal is provided by an external digital circuit.

[0040] The positive improvement effect of the present invention is that the present invention adopts a one-time power-on detection circuit, which can put the voltage detection circuit into a low power consumption mode after the chip initialization work is completed, thereby avoiding the static power consumption of the voltage detection circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 A circuit connection schematic diagram of the present invention;

[0042] Figure 2 for Figure 1 Schematic diagram of optimized circuit connection;

[0043] Figure 3 Another circuit connection diagram of the present invention;

[0044] Figure 4 A voltage detection flow chart of the present invention;

[0045] Figure 5 This is another voltage detection flow chart of the present invention. DETAILED DESCRIPTION

[0046] In order to make the technical means, creative features, objectives and effects achieved by the present invention easy to understand, the present invention is further described below with reference to specific illustrations.

[0047] Reference Figure 1 A one-time power-on detection circuit includes a voltage detection circuit, which includes a power supply terminal VDD, a power-on reset signal terminal por, a comparator U1, a first resistor R1, a detection point voltage terminal, a power-on initialization signal terminal init, a first MOSFET tube Q1 and a second resistor R2.

[0048] The in-phase input terminal of the comparator U1 is connected to the power supply terminal VDD via the first resistor R1, the inverting input terminal of the comparator U1 is connected to the detection point voltage terminal, the output terminal of the comparator U1 is the power-on reset signal terminal por, and the control terminal of the comparator U1 is connected to the power-on initialization signal terminal init. Among them, the power-on reset signal terminal por is used to connect to the external mathematical circuit. If the signal of the power-on reset signal terminal por is flipped, it is considered that the chip is in a suitable voltage condition and the chip can be initialized. The power-on initialization signal terminal init provides a power-on initialization signal, which is a high level 1 when the chip initialization is turned on and a low level 0 after the chip initialization is completed.

[0049] The gate of the first MOSFET tube Q1 is connected to the power-on initialization signal terminal init, the drain of the first MOSFET tube Q1 is connected to the power supply terminal VDD through the second resistor R2 and the first resistor R1 connected in series, and the source of the first MOSFET tube Q1 is grounded. The first MOSFET tube Q1 is an N-channel first MOSFET tube.

[0050] Reference Figure 4When the chip is powered on, the power-on initialization signal input at the power-on initialization signal terminal init is high level 1, and the voltage detection circuit enters the working mode. When: VDD>Vref*(R2+R1) / R2, the power-on reset signal terminal por is flipped, and it is considered that the chip is in a suitable voltage environment at this time, so the chip starts to initialize; when the chip initialization work is completed, the power-on initialization signal input at the power-on initialization signal terminal init is low level 0, at this time the comparator U1 stops working, and the voltage detection circuit enters the low power consumption mode.

[0051] The power-on initialization signal input by the power-on initialization signal terminal init is provided by an external digital circuit, and the following circuit structure can also be used:

[0052] Reference Figure 2 The voltage detection circuit also includes a delay device Delay and a trigger Dff. The input end of the delay device Delay is connected to the output end of the comparator U1, and the delay device Delay delays the output of the signal output by the comparator U1. The delay time of the delay device Delay is not less than the initialization working time of the chip.

[0053] The clock input terminal (clk pin) of the trigger Dff is connected to the output terminal of the delay device Delay, the signal input terminal (D pin) of the trigger Dff is grounded, and the signal output terminal (Q pin) of the trigger Dff is the power-on initialization signal terminal init. The set terminal (SET pin) of the trigger Dff is configured as a high level 1.

[0054] Reference Figure 5 , when the chip is powered on, the set end of the trigger Dff inputs a high level 1, at this time the signal output end of the trigger Dff is a high level 1, that is, the power-on initialization signal input by the power-on initialization signal end init is a high level 1, the voltage detection circuit enters the working mode, when: VDD>Vref*(R2+R1) / R2, the power-on reset signal end por is flipped, it is considered that the chip is in a suitable voltage environment at this time, so the chip starts initialization work; the initialization work of the chip is completed within the delay time of the delay device Delay, after the delay device Delay delays the preset time, the voltage signal delay at the output end A point of the delay device Delay flips, the trigger Dff acts, and the signal output end of the trigger Dff outputs a low level 0, that is, the power-on initialization signal input by the power-on initialization signal end init is a low level 0, and the voltage detection circuit enters the low power consumption mode.

[0055] Reference Figure 3The present invention also provides another one-time power-on detection circuit, including a voltage detection circuit, which includes a power supply terminal VDD, a power-on reset signal terminal por, a second MOSFET tube Q2, a power-on initialization signal terminal initN, a third resistor R3, a fourth resistor R4, a third MOSFET tube Q3, a fifth resistor R5, and an inverter G1.

[0056] The gate of the second MOSFET tube Q2 is connected to the power-on initialization signal terminal initN, the drain of the second MOSFET tube Q2 is connected to the power supply terminal VDD, the source of the second MOSFET tube Q2 is connected to one end of the third resistor R3, and the other end of the third resistor R3 is grounded via the fourth resistor R4. The second MOSFET tube Q2 is an N-channel MOSFET tube.

[0057] The gate of the third MOSFET tube Q3 is connected to the other end of the third resistor R3, the drain of the third MOSFET tube Q3 is connected to the power supply terminal VDD via the fifth resistor R5, and the source of the third MOSFET tube Q3 is grounded. The third MOSFET tube Q3 is an N-channel MOSFET tube. The threshold voltage of the third MOSFET tube Q2 is the threshold voltage Vth.

[0058] The input end of the inverter G1 is connected to the drain of the third MOSFET tube Q3, and the output end of the inverter G1 is the power-on reset signal end por.

[0059] Reference Figure 4 When the chip is powered on, the power-on initialization signal input to the power-on initialization signal terminal initN is low level 0, and the voltage detection circuit enters the working mode. When: VDD>Vth*(R3+R4) / R4, the power-on reset signal terminal por is flipped, and it is considered that the chip is in a suitable voltage environment at this time, so the chip starts to initialize; when the chip initialization work is completed, the power-on initialization signal input to the power-on initialization signal terminal initN is high level 1, and the voltage detection circuit enters the low power consumption mode. The power-on initialization signal input to the power-on initialization signal terminal initN is provided by an external digital circuit.

[0060] The above shows and describes the basic principles, main features and advantages of the present invention. It should be understood by those skilled in the art that the present invention is not limited to the above embodiments, and the above embodiments and descriptions are only for explaining the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, which fall within the scope of the present invention to be protected. The scope of protection of the present invention is defined by the attached claims and their equivalents.

Claims

1. A one-time power-on detection circuit, comprising a voltage detection circuit having a power supply terminal and a power-on reset signal terminal; It is characterized in that The voltage detection circuit also includes: A comparator, wherein the in-phase input terminal is connected to the power supply terminal via a first resistor, the inverting input terminal is connected to the detection point voltage terminal, the output terminal is the power-on reset signal terminal, and the control terminal is connected to the power-on initialization signal terminal; a first MOSFET tube, with a gate connected to the power-on initialization signal terminal, a drain connected to the first resistor via a second resistor, and a source grounded; a delay device, whose input end is connected to the output end of the comparator, and whose delay time is not less than the initialization working time of the chip; A trigger, the clock input end of which is connected to the output end of the delay device, the signal input end is grounded, and the signal output end is the power-on initialization signal end; When the chip is powered on, the power-on initialization signal inputted by the power-on initialization signal terminal is at a high level, and the voltage detection circuit enters the working mode when: VDD>Vref*(R2+R1) / R2 When the power-on reset signal terminal is flipped, the chip starts initialization work; Wherein, VDD represents the voltage of the power supply terminal, Vref represents the detection point voltage input by the detection point voltage terminal, R1 represents the first resistor, and R2 represents the second resistor; When the chip initialization work is completed, the power-on initialization signal input to the power-on initialization signal terminal is at a low level, and the voltage detection circuit enters a low power consumption mode.

2. The one-time power-on detection circuit according to claim 1, characterized in that: The first MOSFET tube is an N-channel MOSFET tube.

3. The one-time power-on detection circuit according to claim 1, characterized in that: The power-on initialization signal input to the power-on initialization signal terminal is provided by an external digital circuit.

4. The one-time power-on detection circuit according to claim 1, characterized in that: When the chip is powered on, a high level is input to the set end of the trigger, and the power-on initialization signal input to the power-on initialization signal end is a high level, and the voltage detection circuit enters the working mode. After the delay device delays for a preset time, the voltage signal at the output end of the delay device flips, and the trigger is actuated. The signal output end of the trigger outputs a low level, that is, the power-on initialization signal input to the power-on initialization signal end is a low level, and the voltage detection circuit enters the low power consumption mode.

5. A one-time power-on detection circuit, comprising a voltage detection circuit having a power supply terminal and a power-on reset signal terminal; It is characterized in that The voltage detection circuit also includes: a second MOSFET tube, the gate of which is connected to the power-on initialization signal terminal, the drain of which is connected to the power supply terminal, the source of which is connected to one end of a third resistor, and the other end of the third resistor is grounded via a fourth resistor; a third MOSFET tube, with a gate connected to the other end of the third resistor, a drain connected to the power supply terminal via a fifth resistor, and a source grounded; an inverter, the input end of which is connected to the drain of the third MOSFET tube, and the output end of which is the power-on reset signal end; When the chip is powered on, the power-on initialization signal inputted by the power-on initialization signal terminal is at a low level, and the voltage detection circuit enters the working mode when: VDD>Vth*(R3+R4) / R4 When the power-on reset signal terminal is flipped, the chip starts initialization work; Wherein, VDD represents the voltage of the power supply terminal, Vth represents the threshold voltage of the third MOSFET tube, R3 represents the third resistor, and R4 represents the fourth resistor; When the chip initialization work is completed, the power-on initialization signal input to the power-on initialization signal terminal is at a high level, and the voltage detection circuit enters a low power consumption mode.

6. The one-time power-on detection circuit according to claim 5, characterized in that: The second MOSFET tube and the third MOSFET tube are both N-channel MOSFET tubes; The power-on initialization signal input to the power-on initialization signal terminal is provided by an external digital circuit.

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