Fan-out packaging method

Abstract

This application discloses a fan-out packaging method, comprising: placing a first chip on a first surface of a carrier; wherein the first chip includes a functional surface and a non-functional surface disposed opposite each other, with the functional surface of the first chip facing away from the first surface; forming an annular dam around the periphery of a side of the first chip; at least fixing the annular dam to the first chip; removing the carrier, and placing a first heat sink on the non-functional surface of the first chip. Through the above-described method, this application can reduce the probability of chip warping and improve the heat dissipation effect of fan-out devices.

Description

Technical Field

[0001] The present application relates to the field of semiconductor packaging technology, and in particular to a fan-out packaging method. Background Art

[0002] After the traditional fan-out packaging method is used to package the chip, the material in the packaging structure will shrink and deform, which can easily cause the chip to shift within the packaging structure, reducing the chip's service life. In addition, the performance of the fan-out device is easily affected by the poor heat dissipation performance of the traditional fan-out packaging device. Summary of the Invention

[0003] The main technical problem solved by the present application is to provide a fan-out packaging method that can reduce the probability of chip warping and improve the heat dissipation effect of fan-out devices.

[0004] In order to solve the above technical problems, a technical solution adopted in the present application is: providing a fan-out packaging method, comprising: arranging a first chip on the first surface of a carrier board; wherein the first chip includes a functional surface and a non-functional surface arranged opposite to each other, and the functional surface of the first chip is away from the first surface; forming an annular dam on the outer periphery of the side of the first chip; at least fixing the annular dam and the first chip to each other; removing the carrier board, and arranging a first heat sink on the side of the non-functional surface of the first chip.

[0005] The step of arranging the first chip on the first surface of the carrier includes: making the non-functional surface of the first chip face the carrier, and arranging a second heat sink between the non-functional surface of the first chip and the carrier.

[0006] Among them, the step of making the non-functional surface of the first chip face the carrier board and arranging a second heat sink between the non-functional surface of the first chip and the carrier board includes: forming a first metal layer on the first surface of the carrier board and performing back gold treatment on the non-functional surface of the first chip; wherein the first metal layer forms the second heat sink; and fixing the non-functional surface of the first chip to the first metal layer.

[0007] The orthographic projections of the first chip and the annular dam on the second heat sink are located inside the second heat sink.

[0008] The step of at least fixing the annular dam and the first chip in fixed connection comprises: forming an adhesive layer on the periphery of the side surfaces of the first chip and the annular dam; wherein the adhesive layer is insulating adhesive; or the adhesive layer is conductive.

[0009] Wherein, before the step of forming a ring-shaped dam on the outer periphery of the side surface of the first chip, it includes: simultaneously forming multiple conductive columns and multiple conductive bumps; wherein, the multiple conductive columns are located on the outer periphery of the side surface of the first chip, and the multiple conductive bumps are located on the functional surface of the first chip.

[0010] In which, the conductive column is located on the periphery of the adhesive layer, and the step of removing the carrier and setting a first heat sink on the non-functional side of the first chip includes: making the side of the carrier with the first chip face the conductive substrate, and electrically connecting the conductive column and the conductive bump to the conductive substrate; removing the carrier; setting the first heat sink on the non-functional surface of the first chip, and the conductive column is exposed from the first heat sink.

[0011] The first heat sink includes a base plate and a plurality of side plates extending from the base plate; the orthographic projection of the base plate on the conductive substrate covers the first chip and the annular dam, and the side plates are arranged through the gap between the annular dam and the conductive column and contact the conductive substrate.

[0012] Wherein, the adhesive layer is an insulating adhesive, the conductive column is located in the adhesive layer, and before the step of removing the carrier, it includes: forming a first redistribution layer on the side of the adhesive layer away from the carrier, and the first redistribution layer is electrically connected to one end of the conductive column and the functional surface of the first chip.

[0013] The orthographic projection of the first heat sink on the adhesive layer covers the first chip, the annular dam and a portion of the conductive column adjacent to the annular dam; or, after the step of removing the carrier board, the step further includes: providing a second redistribution layer at the other end of the conductive column, the second redistribution layer being electrically connected to the conductive column; the orthographic projection of the first heat sink on the adhesive layer covers the first chip and the annular dam.

[0014] The beneficial effects of this application are as follows: Unlike the prior art, this application reduces the deformation of the material in the adhesive layer due to shrinkage by providing an annular dam, thereby reducing the probability of warping of the first chip. In addition, the provision of the first heat sink and the second heat sink greatly improves the heat dissipation performance of the fan-out device. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without inventive efforts. Among them:

[0016] Figure 1 1 is a flow chart of an embodiment of the fan-out packaging method of the present application;

[0017] Figure 2 yes Figure 1 Step S101 corresponds to a cross-sectional structural diagram of an embodiment;

[0018] Figure 3 yes Figure 1 Step S102 corresponds to a cross-sectional structural diagram of an embodiment;

[0019] Figure 4 yes Figure 1 Step S103 corresponds to a cross-sectional structural diagram of an embodiment;

[0020] Figure 5 This is a flow chart of another embodiment of the fan-out packaging method of the present application;

[0021] Figure 6 yes Figure 5 Step S201 corresponds to a cross-sectional structural diagram of an embodiment;

[0022] Figure 7 yes Figure 5 Step S202 corresponds to a cross-sectional structural diagram of an embodiment;

[0023] Figure 8 yes Figure 5 Step S204 corresponds to a flowchart of an embodiment;

[0024] Figure 9 yes Figure 8 Step S301 corresponds to a cross-sectional structural diagram of an embodiment;

[0025] Figure 10 yes Figure 8 Step S302 corresponds to a cross-sectional structural diagram of an embodiment;

[0026] Figure 11 yes Figure 8 The cross-sectional structural diagram corresponding to an embodiment after step S302;

[0027] Figure 12 yes Figure 1 Step S103 corresponds to a flowchart of another embodiment;

[0028] Figure 13 yes Figure 12 Step S401 corresponds to a cross-sectional structural diagram of an embodiment;

[0029] Figure 14 yes Figure 12Step S402 corresponds to a cross-sectional structural diagram of an embodiment;

[0030] Figure 15 yes Figure 12 Step S403 corresponds to a cross-sectional structural diagram of an embodiment;

[0031] Figure 16 yes Figure 12 Step S403 corresponds to a cross-sectional structural diagram of another embodiment. DETAILED DESCRIPTION

[0032] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0033] See also Figure 1 , Figure 1 : is a flow chart of an embodiment of the fan-out packaging method of the present application, the method comprising:

[0034] S101: Disposing a first chip on a first surface of a carrier board.

[0035] See also Figure 2 , Figure 2 for Figure 1Step S101 corresponds to a schematic cross-sectional structure diagram of an embodiment. The specific implementation process of step S101 includes: setting a carrier 10, which includes a first surface 11 and a second surface 12 arranged opposite to each other. The material of the carrier 10 can be a hard material such as metal or plastic, and the flatness of the first surface 11 of the carrier 10 is higher. Furthermore, a first chip 100 is set on the first surface 11 of the carrier 10. The first chip 100 includes a functional surface 101 and a non-functional surface 102 arranged opposite to each other, and the functional surface 101 includes a plurality of pads 103 (only two are drawn in the figure) for information transmission, and the functional surface 102 of the first chip 100 is away from the first surface 11, and the non-functional surface 102 of the first chip 100 faces the carrier 10. In addition, a second heat sink 70 is provided between the non-functional surface 102 of the first chip 100 and the carrier 10, which helps to improve the heat dissipation performance of the first chip 100. Specifically, a first metal layer can be formed on the first surface 11 of the carrier 10 by a metal sputtering process; then, a back-gold treatment is performed on the non-functional surface 102 of the first chip 100 to facilitate connection between the non-functional surface 102 and the first metal layer. The first metal layer forms a second heat sink 70. Furthermore, the non-functional surface 102 of the first chip 100 is fixed to the first metal layer. In this embodiment, the orthographic projection of the non-functional surface 102 of the first chip 100 on the first metal layer is located within the first metal layer, and the area of ​​the first metal layer can be larger than the area of ​​the non-functional surface 102; however, in other embodiments, the area of ​​the first metal layer can also be the same as the area of ​​the non-functional surface 102. In addition, a soldering flux can be provided on the first metal layer to facilitate fixation of the non-functional surface 102 to the first metal layer.

[0036] S102: forming an annular dam on the periphery of a side surface of the first chip, so that at least the annular dam is fixedly connected to the first chip.

[0037] See also Figure 3 , Figure 3 for Figure 1 Step S102 corresponds to a cross-sectional structural diagram of an embodiment. Prior to step S102 , the process includes forming a plurality of conductive bumps 20 . Specifically, the plurality of conductive bumps 20 are located on the functional surface 101 of the first chip 100 , with each conductive bump 20 being electrically connected to each pad 103 .

[0038] Please continue reading Figure 3The specific implementation process of step S103 includes: forming an annular dam 40 on the outer side of the first chip 100. In response to the area of ​​the second heat sink 70 being larger than the area of ​​the non-functional surface 102, the annular dam 40 can be set on the second heat sink 70, that is, the orthographic projection of the first chip 100 and the annular dam 40 on the second heat sink 70 is located inside the second heat sink 70. In this embodiment, one or more annular dams 40 can be set on the outer side of the first chip 100. Figure 3 As shown in Figure 3 Only two annular dams 40 are schematically illustrated. If there are multiple annular dams 40, they can be arranged at intervals, i.e., one annular dam 40 is arranged around the periphery of another annular dam 40. Alternatively, the orthographic projection of the annular dam 40 on the carrier 10 can be a circular ring, a rectangular ring, etc. Furthermore, in other applications, the annular dam 40 may not be arranged around the side periphery of the second heat sink 70. The specific process is not further described here.

[0039] The annular dam 40 can be formed by applying a photoresist layer on the side of the carrier 10 where the first chip 100 is disposed, exposing and developing the photoresist layer to form an annular opening, and then filling the annular opening with a conductive metal to form the annular dam 40. In this embodiment, the annular dam 40 is made of a conductive metal. However, in other embodiments, the annular dam 40 can also be made of a non-metallic material. When the annular dam 40 is made of metal, it not only protects the first chip 100 but also provides electromagnetic shielding. When the annular dam 40 is made of a non-metallic material, it can also protect the first chip 100.

[0040] Of course, in other embodiments, the annular dam 40 may be prefabricated and then attached to the outer side of the first chip 100 .

[0041] For further information, please refer to Figure 3 , Figure 1 Step S102 further includes: at least securing the annular dam 40 to the first chip 100. Specifically, an adhesive layer 45 can be formed around the outer side of the first chip 100 and the outer side of the annular dam 40 to secure and protect the first chip 100 and the annular dam 40. The adhesive layer 45 covers the side of the annular dam 40 facing away from the carrier 10; the adhesive layer 45 can be flush with or lower than the functional surface 101 of the first chip 100, although this application does not limit this. The adhesive layer 45 can be an insulating adhesive; alternatively, the adhesive layer 45 can be conductive to provide enhanced electromagnetic shielding.

[0042] S103: removing the carrier board and disposing a first heat sink on the non-functional surface of the first chip.

[0043] See also Figure 4 , Figure 4 for Figure 1 Step S103 corresponds to a cross-sectional structural diagram of an embodiment, and the specific implementation process of step S103 includes: Figure 4 As shown in Figure a, a plastic layer 46 is provided on the side of the carrier 10 where the first chip 100 is provided. The plastic layer 46 is flush with the functional surface 101 of the first chip 100, and the conductive bumps 20 are exposed from the plastic layer 46. The plastic layer 46 further secures and protects the second heat sink 70, the first chip 100, and the annular dam 40.

[0044] Further, if Figure 4 As shown in Figure b, the carrier 10 is removed, and a first heat sink 80 is provided on the non-functional surface 102 of the first chip 100. The first heat sink 80 can be made of a metal material such as elemental indium, an indium alloy, or a silver alloy, or an organic material. When the first heat sink 80 is made of a metal material, flux is required during the formation of the first heat sink 80 to remove the oxide layer and foreign matter on the surface of the metal heat sink material and to improve wettability and solderability.

[0045] For further information, please refer to Figure 4 In Figure b, after the first heat sink 80 is provided, the following further steps are performed: a first electrical connector 140 is provided on the functional surface 101 of the first chip 100. The first electrical connector 140 is electrically connected to the conductive bump 20. The provision of the first electrical connector 140 facilitates connection of other devices or chips to the first chip 100.

[0046] Optionally, in this embodiment, the first electrical connector 140 may be provided first and then the first heat sink 80 may be provided, which is not limited in this application.

[0047] By providing an annular dam 40 around the side periphery of the first chip 100, the present application can reduce the deformation caused by shrinkage of the material in the adhesive layer 45, thereby reducing the probability of warping of the first chip 100. In addition, the provision of the first heat sink 80 and the second heat sink 70 greatly improves the heat dissipation performance of the fan-out device.

[0048] In another embodiment, Figure 1 Before step S102, the following steps may be further included: forming a plurality of conductive pillars 30 and a plurality of conductive bumps 20 simultaneously. Figure 5 , Figure 5 This is a flow chart of another embodiment of the fan-out packaging method of the present application. The specific implementation process includes:

[0049] S201: forming a plurality of conductive pillars and a plurality of conductive bumps simultaneously.

[0050] See also Figure 6 , Figure 6 For Figure 5 Step S201 corresponds to a schematic cross-sectional structure diagram of an embodiment. The specific implementation process of step S201 includes: simultaneously forming a plurality of conductive pillars 30 and conductive bumps 20. The plurality of conductive pillars 30 are located on the side periphery of the first chip 100, and the plurality of conductive bumps 20 are located on the functional surface 101 of the first chip 100. The plurality of conductive pillars 30 and the plurality of conductive bumps 20 can be formed by providing a photoresist layer on the side of the carrier 10 where the first chip 100 is provided, and exposing and developing the photoresist layer to generate a plurality of vias, and then filling the vias with conductive metal to generate the plurality of conductive pillars 30 and the conductive bumps 20. After forming the conductive bumps 20 and the conductive pillars 30, the process also includes: removing the photoresist layer to expose the conductive pillars 30 and the conductive bumps 20. The formation of the plurality of conductive bumps 20 helps to connect the first chip 100 to other devices; the conductive pillars 30 help to achieve a three-dimensional vertical interconnected structure.

[0051] S202: forming a ring-shaped dam on the periphery of the side surface of the first chip.

[0052] See also Figure 7 , Figure 7 for Figure 5 Step S202 corresponds to a schematic cross-sectional view of an embodiment. The specific implementation process of step S202 includes forming an annular dam 40 around the outer periphery of the side of the first chip 100. The orthographic projection of the annular dam 40 on the second heat sink 70 is located within the second heat sink 70, and the plurality of conductive pillars 30 are located around the outer periphery of the annular dam 40.

[0053] S203: At least the annular dam and the first chip are fixedly connected.

[0054] For details, please refer again to Figure 7 A glue layer 45 may be formed on the side periphery of the first chip 100 and the side periphery of the annular dam 40 to fix the annular dam 40 and the first chip 100 together, and the conductive pillar 30 may be located on the periphery of the glue layer 45 .

[0055] S204: Disposing a first heat sink on the non-functional surface of the first chip.

[0056] See also Figure 8 , Figure 8 for Figure 5 Step S204 corresponds to a flowchart of an embodiment, and the specific implementation process of step S105 includes:

[0057] S301: The side of the carrier board provided with the first chip faces the conductive substrate.

[0058] See also Figure 9 , Figure 9 for Figure 8 Step S301 corresponds to a schematic cross-sectional view of one embodiment. The specific implementation process of step S301 includes: providing a conductive substrate 90, aligning the carrier 10 with the side of the carrier 10 provided with the first chip 100 facing the conductive substrate 90, and electrically connecting the conductive pillars 30 and the conductive bumps 20 to the conductive substrate 90. Specifically, the conductive substrate 90 includes multiple solder joints 92. The ends of the conductive pillars 30 facing away from the carrier 10 are electrically connected to the conductive substrate 90 via the solder joints 92; the conductive bumps 20 are also electrically connected to the conductive substrate 90 via the solder joints 92. The conductive substrate 90 can connect to the first chip 100 and exchange information.

[0059] S302: Disposing a first heat sink on a non-functional surface of the first chip.

[0060] See also Figure 10 , Figure 10 for Figure 8 Step S302 corresponds to a schematic cross-sectional view of an embodiment. The specific implementation process of step S202 includes: removing the carrier 10, and placing a first heat sink 80 on the non-functional surface 102 of the first chip 100; exposing the conductive pillars 30 from the first heat sink 80 to facilitate the subsequent placement of connected devices at the exposed ends of the conductive pillars 30. The first heat sink 80 includes a base plate 81 and multiple side plates 82 extending from the base plate 81. The orthographic projection of the base plate 81 on the conductive substrate 90 covers the first chip 100 and the annular dam 40, while the side plates 82 extend through the gap between the annular dam 40 and the conductive pillars 30 and contact the conductive substrate 90. Providing the first heat sink 80, including the base plate 81 and multiple side plates 82, helps increase the heat sink area, thereby improving heat dissipation. The design of the multiple side plates 82 also helps separate the conductive pillars 30 from the annular dam 40, preventing short circuits. Of course, in other embodiments, the first heat sink 80 may also only include the bottom plate 81 , which is not limited in this application.

[0061] Further, see Figure 11 , Figure 11 yes Figure 8The schematic diagram of the cross-sectional structure after step S302 corresponds to one embodiment. Specifically, after step S302, the following steps include: disposing a first electrical connector 140 and a second electrical connector 150 on both sides of the conductive pillar 30 in the longitudinal direction. The first electrical connector 140 is electrically connected to the end of the conductive pillar 30 facing away from the conductive substrate 90 via multiple solder balls 145; the second electrical connector 150 is electrically connected to the conductive substrate 90 via multiple solder balls 145. Through the first electrical connector 140 and the second electrical connector 150, the fan-out device can be connected to the substrate or other chips.

[0062] In another embodiment, before step S103, the following steps may be performed: forming a glue layer 45 on the side of the carrier 10 where the first chip 100 is provided, wherein the glue layer 45 is an insulating glue, and the first chip 100, the annular dam 40 and the conductive pillar 30 form an integral structure through the glue layer 45. Figure 12 , Figure 12 for Figure 1 Step S103 corresponds to a flow chart of another embodiment, and the specific implementation process of this embodiment includes:

[0063] S401: forming an adhesive layer on the side of the carrier board where the first chip is disposed.

[0064] See also Figure 13 , Figure 13 for Figure 12 Step S401 corresponds to a schematic structural diagram of one embodiment. Specifically, step S401 includes forming an insulating adhesive layer 45 on the side of the carrier 10 where the first chip 100 is mounted. The adhesive layer 45 then forms an integrated structure with the first chip 100, the annular dam 40, and the conductive pillars 30, thereby securing and protecting the first chip 100, the annular dam 40, and the conductive pillars 30. The conductive pillars 30 are exposed from the adhesive layer 45 at one end facing away from the carrier 10, and the conductive bumps 20 are then exposed, allowing step S402 to proceed.

[0065] S402: forming a first redistribution layer on the side of the adhesive layer facing away from the carrier board.

[0066] See also Figure 14 , Figure 14 for Figure 12 Step S402 corresponds to a schematic cross-sectional view of one embodiment. Specifically, step S402 includes forming a first redistribution layer 110 on the side of the adhesive layer 45 facing away from the carrier 10. The first redistribution layer 110 is electrically connected to one end of the conductive pillar 30 and the functional surface 101 of the first chip 100. The first redistribution layer 110 is electrically connected to the first chip 100 via the conductive bumps 20. The provision of the first redistribution layer 110 facilitates connection of other devices to the first chip 100 and the conductive pillars 30.

[0067] S403: Disposing a first heat sink on the non-functional surface of the first chip.

[0068] See also Figure 15 , Figure 15 for Figure 12 Step S403 corresponds to a schematic cross-sectional structure diagram of an embodiment. The specific implementation process of step S303 includes: removing the carrier board 10, and setting a first heat sink 80 on the side of the non-functional surface 102 of the first chip 100. The orthographic projection of the first heat sink 80 on the adhesive layer 45 covers the first chip 100, the annular dam 40, and the portion of the conductive pillars 30 adjacent to the annular dam 40, that is, the first heat sink 80 is in contact with the annular dam 40, the second heat sink 70, and the portion of the conductive pillars 30. The contact between the first heat sink 80 and the annular dam 40 and the portion of the conductive pillars 30 helps to dissipate heat from the annular dam 40 and the portion of the conductive pillars 30, further improving the heat dissipation performance of the fan-out device.

[0069] For further information, please refer to Figure 15 Step S403 further includes providing a first electrical connector 140 and a second electrical connector 150 on either side of the conductive pillar 30 in the longitudinal direction. The first electrical connector 140 is electrically connected to the first redistribution layer 110 via a plurality of solder balls 145; the second electrical connector 150 is electrically connected to one end of the conductive pillar 30 via a plurality of solder balls 145. Providing the first and second electrical connectors 140 and 150 facilitates connecting the fan-out device to a substrate or other chips.

[0070] Optionally, in another application mode, the first heat sink 80 may not be in contact with the conductive column 30. In this case, please refer to Figure 16 , Figure 16 for Figure 12 Step S403 corresponds to a schematic cross-sectional structure diagram of another embodiment. Specifically, the carrier 10 is removed, and a first heat sink 80 is provided on the side of the non-functional surface 102 of the first chip 100. The orthographic projection of the first heat sink 80 on the adhesive layer 45 covers the first chip 100 and the annular dam 40. Furthermore, a second redistribution layer 120 is provided at one end of the conductive column 30, and the second redistribution layer 120 is electrically connected to the conductive column 30. The surface of the second redistribution layer 120 facing away from the conductive column 30 is flush with the surface of the first heat sink 80 facing away from the first chip 100, and the second redistribution layer 120 is not provided in the area covered by the first heat sink 80. The second redistribution layer 120 helps to connect the conductive column 30 to the substrate or other devices.

[0071] For further information, please refer to Figure 16In this application, step S403 further includes providing a first electrical connector 140 and a second electrical connector 150 on both sides of the conductive pillar 30 in the longitudinal direction. The first electrical connector 140 is electrically connected to the first redistribution layer 110 via a plurality of solder balls 145; the second electrical connector 150 is electrically connected to the second redistribution layer 120 via a plurality of solder balls 145. Providing the first electrical connector 140 and the second electrical connector 150 facilitates connecting the fan-out device to a substrate or other chips.

[0072] In this embodiment, the first chip 100, the annular dam 40, and the conductive pillars 30 form an integrated structure via the adhesive layer 45. The annular dam 40 and the conductive pillars 30 act as retaining walls, limiting the movement of material within the adhesive layer 45. This reduces deformation of the adhesive layer 45 due to material shrinkage and reduces the probability of warping of the first chip 100. The conductive pillars 30 also enable a three-dimensional vertical interconnect structure, which helps reduce the height of the fan-out device. The provision of a first heat sink 80 further improves the heat dissipation performance of the fan-out device.

[0073] The above description is only an implementation method of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A fan-out packaging method, characterized in that: include: A first chip is arranged on the first surface of the carrier; wherein the first chip includes a functional surface and a non-functional surface arranged opposite to each other, and the functional surface of the first chip faces away from the first surface; forming an annular dam on the periphery of a side surface of the first chip; and at least fixing the annular dam to the first chip; The carrier board is removed, and a first heat sink is provided on the non-functional surface side of the first chip; The step of at least fixing the annular dam and the first chip in a fixed connection comprises: forming an adhesive layer on the periphery of the side of the first chip and the periphery of the side of the annular dam; wherein the adhesive layer is an insulating adhesive; or the adhesive layer is conductive; Before the step of forming an annular dam on the periphery of the side of the first chip, the method further includes: simultaneously forming a plurality of conductive pillars and a plurality of conductive bumps; wherein the plurality of conductive pillars are located on the periphery of the side of the first chip, and the plurality of conductive bumps are located on the functional surface of the first chip; specifically, a photoresist layer is provided on the side of the carrier where the first chip is provided, the photoresist layer is exposed and developed to form a plurality of vias, and the vias are filled with conductive metal to form the conductive pillars and the conductive bumps; The step of arranging the first chip on the first surface of the carrier includes: making the non-functional surface of the first chip face the carrier, and arranging a second heat sink between the non-functional surface of the first chip and the carrier; The conductive pillars are located on the periphery of the adhesive layer, and the step of removing the carrier and providing a first heat sink on the non-functional side of the first chip comprises: orienting the side of the carrier provided with the first chip toward the conductive substrate, and electrically connecting the conductive pillars and the conductive bumps to the conductive substrate; removing the carrier; and providing the first heat sink on the non-functional side of the first chip, with the conductive pillars exposed from the first heat sink; The first heat sink includes a base plate and a plurality of side plates extending from the base plate; the orthographic projection of the base plate on the conductive substrate covers the first chip and the annular dam, and the side plates are arranged through the gap between the annular dam and the conductive column and contact the conductive substrate.

2. The fan-out packaging method according to claim 1, wherein: The step of making the non-functional surface of the first chip face the carrier board, and disposing a second heat sink between the non-functional surface of the first chip and the carrier board, comprises: forming a first metal layer on the first surface of the carrier board, and performing back-metal processing on the non-functional surface of the first chip; wherein the first metal layer forms the second heat sink; The non-functional surface of the first chip is fixed to the first metal layer.

3. The fan-out packaging method according to claim 2, wherein: The orthographic projections of the first chip and the annular dam on the second heat sink are located inside the second heat sink.

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