Packaging Method and Packaging Structure of Multilayer Stacked High-Bandwidth Memory

Abstract

The present invention provides a packaging method and a packaging structure for a multi-layer stacked high-bandwidth memory. The method includes: providing a substrate and multiple groups of memory chips respectively, each group of memory chips including a first memory chip and a second memory chip; the first memory chip and the second memory chip are provided with a plurality of conductive vias; respectively hybrid bonding the first memory chip and the second memory chip to form a plurality of memory micro-modules; sequentially forming a first conductive bump and a second conductive bump on the surface of the first memory chip facing the substrate; forming pads on the surface of the second memory chip facing away from the substrate; nesting the second conductive bump and the pads through a thermocompression bonding process to sequentially stack the plurality of memory micro-modules on the substrate in an insulated manner; performing reflow soldering on the stacked plurality of memory micro-modules and the substrate through a reflow soldering process; forming a plastic encapsulation layer. The present invention can achieve ultra-multi-layer chip stacking, improve production efficiency, and achieve ultra-fine pitch interconnection.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor packaging, and particularly relates to a packaging method and a packaging structure for a multi-layer stacked high-bandwidth memory. Background Art

[0002] With the development of cloud computing and mobile interconnection, the demand for servers such as data centers has increased sharply. High-end servers require high-capacity, large-bandwidth, and low-power storage devices. To meet this demand, companies have successively introduced multi-layer stacked storage packaging products based on three-dimensional stacking technology. As Figure 1 shown, in the multi-layer stacked memory packaging stacked structure, through-silicon vias 2 are used to vertically interconnect several memory chips 1. Multiple memory chips 1 are welded together through bumps 3. The memory chips 1 are stacked on a substrate 4. There is a non-conductive adhesive 5 between the chips. The entire memory chip structure is protected by a plastic encapsulation layer 6. Finally, the package is connected to the outside through solder balls 7. Since the through-silicon vias 2 have the advantages of high density and short vertical interconnection distance, the data transmission speed is greatly improved.

[0003] Currently, for the multi-layer chips of multi-layer stacked memories, a thermal compression bonding (TCB) process is mostly used. Through rapid heating, the bumps 3 are connected to the back pads 8 of the chips, and the back pads 8 of the chips are connected to the through-silicon vias 2 of the chips. Currently, the main component of the bumps is a copper-tin structure, and the main component of the back pads of the chips is a nickel-gold structure. The final stacked structure is protected by a plastic encapsulation layer 6.

[0004] In the case of using copper-tin bumps, due to the deformability of tin during reflow, in order to prevent short circuits between the bumps, the spacing between the bumps 3 and the height of tin need to be strictly controlled. Currently, the spacing is above 40 um. When the spacing is reduced to below 25 um, due to the too small amount of tin, it is completely converted into an intermetallic compound under hot carrier conditions, resulting in reliability failure.

[0005] In order to increase the storage capacity and data throughput speed, it is necessary to increase the number of stacked chips and the number of pins. However, in the current structure of micro-bumps, due to the limitations of the bump height and spacing, the room for continuous improvement is limited.

[0006] In view of the above problems, it is necessary to propose a packaging method and a packaging structure for a multi-layer stacked high-bandwidth memory that are reasonably designed and can effectively solve the above problems. Summary of the Invention

[0007] The present invention aims to at least solve one of the technical problems existing in the prior art, and provides a packaging method and a packaging structure for a multi-layer stacked high-bandwidth memory.

[0008] One aspect of the present invention provides a packaging method for a multi-layer stacked high-bandwidth memory, the method comprising:

[0009] A substrate and multiple groups of memory chips are respectively provided, and each group of the memory chips includes a first memory chip and a second memory chip; wherein, a plurality of conductive vias are provided on both the first memory chip and the second memory chip;

[0010] The first memory chip and the second memory chip in each group of the memory chips are respectively hybrid bonded to form a plurality of memory micro-modules;

[0011] At positions corresponding to the conductive vias on the surface of the first memory chip facing the substrate, a first conductive bump and a second conductive bump are sequentially formed;

[0012] A pad is formed at a position corresponding to the conductive via on the surface of the second memory chip facing away from the substrate;

[0013] Through a thermocompression bonding process, the second conductive bump and the pad are nested to sequentially stack the plurality of memory micro-modules on the substrate in an insulating manner;

[0014] Through a reflow soldering process, the stacked plurality of memory micro-modules and the substrate are reflow soldered;

[0015] A molding layer is formed, and the molding layer wraps the plurality of memory micro-modules and the substrate.

[0016] Optionally, a first passivation layer and a first metal pad are provided on the surface of the first memory chip facing the second memory chip, and a second passivation layer and a second metal pad are provided on the surface of the second memory chip facing the first memory chip;

[0017] The step of respectively hybrid bonding the first memory chip and the second memory chip in each group of the memory chips to form a plurality of memory micro-modules includes:

[0018] Bonding the first passivation layer in the first memory chip to the second passivation layer in the corresponding second memory chip; and,

[0019] Bonding the first metal pad in the first memory chip to the second metal pad in the corresponding second memory chip.

[0020] Optionally, the step of nesting the second conductive bump and the pad through a thermocompression bonding process includes:

[0021] Forming a protrusion on the pad;

[0022] Press the protrusion into the second conductive bump through a thermocompression bonding process.

[0023] Optionally, forming a first conductive bump and a second conductive bump in sequence at a position corresponding to the conductive through-hole on the surface of the first memory chip facing the substrate includes:

[0024] Form a third passivation layer and a dielectric layer in sequence on the surface of the first memory chip facing the substrate;

[0025] Form a photoresist layer on the dielectric layer, pattern the photoresist layer to form a plurality of openings, and the plurality of openings respectively correspond to the plurality of conductive through-holes;

[0026] Form the first conductive bump and the second conductive bump in sequence at the plurality of openings;

[0027] Remove the photoresist layer.

[0028] Optionally, the surface of the second conductive bump protrudes from the surface of the photoresist layer; before removing the photoresist layer, the method further includes:

[0029] Grind the second conductive bump so that the surface of the second conductive bump is flush with the surface of the photoresist layer.

[0030] Optionally, encapsulant is filled between each of the memory micro-modules and between the micro-module and the substrate.

[0031] Optionally, in each group of the memory chips, the first memory chip is disposed close to the substrate, the second memory chip is disposed away from the substrate, and the thickness of the first memory chip is less than the thickness of the second memory chip.

[0032] Another aspect of the present invention provides a multi-layer stacked high-bandwidth memory packaging structure, the packaging structure includes: a substrate, a plurality of memory micro-modules, and a plastic encapsulation layer, and the plurality of memory micro-modules are insulatingly stacked on the substrate; wherein,

[0033] Each of the memory micro-modules includes a first memory chip and a second memory chip, and each of the first memory chips is hybrid-bonded to the corresponding second memory chip through a hybrid bonding structure, wherein the first memory chip and the second memory chip are both provided with a plurality of conductive through-holes; and,

[0034] On the surface of the first memory chip facing the substrate corresponding to the conductive vias, a first conductive bump and a second conductive bump are sequentially arranged. On the surface of the second memory chip facing away from the substrate corresponding to the conductive vias, a pad is arranged, and the second conductive bump and the pad are nested and connected.

[0035] The encapsulation layer wraps the plurality of memory micro-modules and the substrate.

[0036] Optionally, the hybrid bonding structure includes a first passivation layer and a first metal pad arranged on the surface of the first memory chip facing the second memory chip, and a second passivation layer and a second metal pad arranged on the surface of the second memory chip facing the first memory chip.

[0037] The first passivation layer in the first memory chip is bonded to the second passivation layer in the corresponding second memory chip, and the first metal pad in the first memory chip is bonded to the second metal pad in the corresponding second memory chip.

[0038] Optionally, a protrusion is arranged on one side of the pad facing the second conductive bump, and a groove is arranged on one side of the second conductive bump facing the pad, and the protrusion is inserted into the groove.

[0039] Optionally, the second conductive bump has a columnar structure.

[0040] Optionally, the first memory chip is arranged close to the substrate, the second memory chip is arranged facing away from the substrate, and the thickness of the first memory chip is less than the thickness of the second memory chip.

[0041] The packaging method and packaging structure of the multi-layer stacked high-bandwidth memory of the present invention form multiple memory micro-modules by hybrid bonding the first memory chip and the second memory chip. By using dual chips for hybrid bonding to form memory micro-modules, ultra-multi-layer chip stacking can be achieved, improving production efficiency, reducing the bonding height, greatly increasing the number of chip layers, and increasing the capacity. The number of chip layers of this packaging structure can be greatly increased, the capacity can be increased, and the packaging height can be reduced to the greatest extent. At the position corresponding to the conductive vias on the surface of the first memory chip facing the substrate, a first conductive bump and a second conductive bump are sequentially formed. At the position corresponding to the conductive vias on the surface of the second memory chip facing away from the substrate, pads are formed. Through the thermocompression bonding process, the second conductive bump and the pads are nested to stack multiple memory micro-modules on the substrate in sequence. Through the reflow soldering process, the stacked multiple memory micro-modules and the substrate are reflow soldered. By using a two-step soldering process in the present invention to nest the second conductive bump and the pads, the deformation of the second conductive bump can be reduced, so that the pitch of the second conductive bumps can be reduced, realizing ultra-fine pitch interconnection. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 FIG. 6 is a schematic diagram of the packaging process of multi-layer chips in the prior art;

[0043] Figure 2 FIG. 10 is a schematic flow chart of a packaging method for a multi-layer stacked high-bandwidth memory according to an embodiment of the present invention;

[0044] Figures 3 to 12 FIG. 14 is a schematic diagram of the packaging process of a packaging method for a multi-layer stacked high-bandwidth memory according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0045] To enable those skilled in the art to better understand the technical solutions of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0046] As Figure 2 shown, one aspect of the present invention provides a packaging method S100 for a multi-layer stacked high-bandwidth memory. The packaging method S100 includes:

[0047] S100. Provide a substrate and multiple groups of memory chips respectively. Each group of the memory chips includes a first memory chip and a second memory chip; wherein, both the first memory chip and the second memory chip are provided with a plurality of conductive vias.

[0048] Specifically, as Figure 11 and Figure 12As shown, a substrate 110 and multiple groups of memory chips are respectively provided. Each group of memory chips includes a first memory chip 120 and a second memory chip 130. Among them, multiple conductive vias 140 are provided on both the first memory chip 120 and the second memory chip 130. That is to say, the first memory chip 120 and the second memory chip 130 are electrically connected through the conductive vias 140. Further preferably, the multiple conductive vias 140 can be through-silicon vias. The vertical electrical interconnection of through-silicon vias is realized by using through-silicon via technology, reducing the package height. In this embodiment, the first memory chip 120 and the second memory chip 130 adopt dynamic random access memory chips, or other memory chips, which are not specifically limited in this embodiment.

[0049] S120. The first memory chip and the second memory chip in each group of the memory chips are respectively hybrid-bonded to form multiple memory micro-modules.

[0050] Specifically, the first memory chip 120 and the second memory chip 130 in each group of memory chips are hybrid-bonded to form multiple memory micro-modules 150.

[0051] Exemplarily, as Figure 3 shown, a first passivation layer 121 and a first metal pad 122 are provided on the surface of the first memory chip 120 facing the second memory chip 130, and a second passivation layer 131 and a second metal pad 132 are provided on the surface of the second memory chip 130 facing the first memory chip 120. The surface of the first memory chip 120 with the first passivation layer 121 and the first metal pad 122 is subjected to chemical mechanical polishing treatment. Similarly, the surface of the second memory chip 130 with the second passivation layer 131 and the second metal pad 132 is also subjected to chemical mechanical polishing treatment.

[0052] Among them, the first memory chip 120 and the second memory chip 130 in each group of memory chips are respectively hybrid-bonded to form multiple memory micro-modules 150 as Figure 10 shown, which specifically includes:

[0053] First, as Figure 3 shown, the first passivation layer 121 in the first memory chip 120 is bonded to the second passivation layer 131 in the corresponding second memory chip 130. The materials of the first passivation layer 121 and the second passivation layer 131 can be silicon dioxide passivation layers or silicon nitride layers. The circuit layers of the first memory chip 120 and the second memory chip 130 are stacked on top of each other, so that the first passivation layer 121 and the second passivation layer 131 on the surface, that is, the silicon dioxide passivation layers, are bonded. The materials of the first passivation layer 121 and the second passivation layer 131 are not specifically limited in this embodiment.

[0054] Secondly, as Figure 3 shown, bond the first metal pad 122 in the first memory chip 120 to the corresponding second metal pad 132 in the second memory chip 130. In this embodiment, both the first metal pad 122 and the second metal pad 132 are copper pads. After the first passivation layer 121 and the second passivation layer 131 are bonded, perform high-temperature pressing at a temperature above 200 °C, and utilize the thermal expansion of copper to form a bond between the first metal pad 122 and the second metal pad 132. In this embodiment, the materials of the first metal pad 122 and the second metal pad 132 are not specifically limited in this embodiment.

[0055] Exemplarily, as Figure 10 shown, in each memory micro-module, the first memory chip 120 is disposed close to the substrate 110, the second memory chip 130 is disposed away from the substrate 110, and the thickness of the first memory chip 120 is less than the thickness of the second memory chip 130. Further preferably, the thickness of the first memory chip 120 is 10 um to 20 um, and the thickness of the second memory chip 130 is 40 um to 50 um. Among them, the back surface of the first memory chip 120 can be thinned to the limit, that is, it can be thinned to only retain the circuit layer.

[0056] S130. At a position corresponding to the conductive through-hole on the surface of the first memory chip facing the substrate, sequentially form a first conductive bump and a second conductive bump.

[0057] It should be noted that when the thickness of the first memory chip 120 is very thin and multiple conductive through-holes 140 can be exposed, the first memory chip 120 does not need to be thinned; similarly, when the thickness of the second memory chip 130 is very thin and multiple conductive through-holes 140 can be exposed, the second memory chip 130 also does not need to be thinned. However, when the thickness of the first memory chip 120 is very thick and multiple conductive through-holes 140 cannot be exposed, and the thickness of the second memory chip 130 is also very thick and multiple conductive through-holes 140 cannot be exposed, the first memory chip 120 and the second memory chip 130 need to be thinned first. In this embodiment, both the first memory chip 120 and the second memory chip 130 need to be thinned.

[0058] At a position corresponding to the conductive through-hole on the surface of the first memory chip facing the substrate, sequentially forming a first conductive bump and a second conductive bump includes:

[0059] First, thin the surface of the first memory chip facing away from the second memory chip to expose multiple said conductive through-holes.

[0060] Specifically, as Figure 6As shown, the back surface of the first memory chip 120 is thinned, and then a plurality of conductive vias 140 are exposed through an etching process.

[0061] Secondly, a third passivation layer and a dielectric layer are sequentially formed on the surface of the first memory chip facing the substrate.

[0062] Specifically, as Figure 4 shown, after hybrid bonding, a third passivation layer 123 and a dielectric layer 124 are sequentially formed by spin coating on the surface of the first memory chip 120 facing the substrate 110 through a backside opening process. Among them, after forming the third passivation layer 123, a connection metal pad 123a is formed on the third passivation layer 123, and the connection metal pad 123a corresponds to the conductive via 140. It should be noted that the material of the third passivation layer 123 can be silicon dioxide or silicon nitride, and the material of the dielectric layer 124 can be polyimide (PI), polybenzoxazole (PBO), etc. In this embodiment, the material of the dielectric layer 124 is polyimide (PI). The coating method is usually wafer spin coating, which is not specifically limited in this embodiment.

[0063] Again, a photoresist layer is formed on the dielectric layer, and the photoresist layer is patterned to form a plurality of openings, and the plurality of openings respectively correspond to the plurality of conductive vias.

[0064] Specifically, as Figure 5 shown, a photoresist layer 125 is coated on the surface of the dielectric layer 124, and the photoresist layer 125 is patterned by exposure and development to form a plurality of openings (not marked in the figure), and the plurality of openings correspond to the plurality of conductive vias 140 on the first memory chip 120.

[0065] Again, the first conductive bumps and the second conductive bumps are sequentially formed at the plurality of openings.

[0066] Specifically, as Figure 5 shown, a first conductive bump 126 and a second conductive bump 127 are sequentially formed at the plurality of openings through an electroplating process, and the first conductive bump 126 and the second conductive bump 127 are electrically connected to the conductive via 140. In this embodiment, the material of the first conductive bump 126 can be metal copper, and the material of the second conductive bump 127 can be metal tin. Using metal tin for the second conductive bump 127 can keep the packaging cost at a relatively low level.

[0067] Finally, the photoresist layer is removed.

[0068] As Figure 6 shown, the photoresist layer 125 can be removed by dry plasma etching and wet cleaning. The method for removing the photoresist is not specifically limited in this embodiment.

[0069] Exemplarily, the surface of the second conductive bump protrudes from the surface of the photoresist layer; before removing the photoresist layer, the method further includes:

[0070] Grinding the second conductive bump so that the surface of the second conductive bump is flush with the surface of the photoresist layer.

[0071] Specifically, when the first conductive bump 126 and the second conductive bump 127 are sequentially formed at multiple openings by electroplating, the surface of the second conductive bump 127 protrudes from the surface of the photoresist layer 125. At this time, before removing the photoresist layer 125, it is also necessary to grind the surface of the second conductive bump 127 so that the height of the second conductive bump 127 is the same as the height of the photoresist layer 125. As Figure 6 shown, that is to say, the second conductive bump 127 is in a columnar structure, which can be a cylindrical structure or a prismatic structure. The original form of the second conductive bump 127 is in a columnar structure, different from the spherical shape of the traditional conductive bump. In this way, the lateral width can be reduced under the same volume.

[0072] S140. Form pads at positions corresponding to the conductive vias on the surface of the second memory chip facing away from the substrate.

[0073] It should be noted that when the thickness of the second memory chip 130 is very thin and multiple conductive vias 140 can be exposed, the second memory chip 130 does not need to be thinned. However, in this embodiment, as Figure 8 shown, the second memory chip 130 first needs to be thinned to expose the conductive vias 140 on the second memory chip 130.

[0074] Specifically, step S140 includes the following steps.

[0075] First, thin the surface of the second memory chip facing away from the substrate.

[0076] Specifically, as Figure 8 shown, thin the surface of the second memory chip 130 facing away from the substrate 110, that is, the back surface of the first memory chip 120, to expose the multiple conductive vias 140 on the back surface of the second memory chip 130. The thinning process can be carried out by grinding or other methods, and this embodiment does not make specific limitations.

[0077] Secondly, form a fourth passivation layer on the surface of the second memory chip facing away from the substrate, and pattern the fourth passivation layer to form a plurality of first openings, and the plurality of first openings correspond to the plurality of conductive vias.

[0078] Specifically, asFigure 9 As shown, a back via process is performed on the back surface of the thinned second memory chip 130 to fabricate a fourth passivation layer 133. The fourth passivation layer 133 is patterned using a photolithography process to form a plurality of first openings (not marked in the figure). Among them, the plurality of first openings are correspondingly arranged with the plurality of conductive vias 140. In this embodiment, the material of the fourth passivation layer 133 can be silicon dioxide or other materials that can play a passivation role. This embodiment does not make specific limitations.

[0079] Finally, pads are formed at the plurality of first openings.

[0080] Specifically, as Figure 9 shown, pads 134 are formed at the plurality of first openings by an electroplating process. The cross-section of the pad 134 is generally circular or square. In this embodiment, the pad 134 is a copper pad, and the pad 134 has a cylindrical structure. The material of the pad 134 can be selected according to actual needs. This embodiment does not make specific limitations.

[0081] S150, through a thermocompression bonding process, nest the second conductive bumps and the pads to stack the plurality of memory micro-modules on the substrate in sequence and insulatingly.

[0082] Specifically, through a thermocompression bonding process, the second conductive bumps 127 of the first memory chip 120 are nested with the pads 134 on the second memory chip 130. Then, as Figure 10 shown, a plurality of memory micro-modules 150 are stacked on the substrate 110 in sequence and insulatingly by a thermocompression bonding process. When stacking a plurality of memory micro-modules 150 to form a stacked module, it should be that a plurality of memory micro-modules 150 are stacked to form a plurality of stacked modules. Therefore, it is necessary to first divide the plurality of stacked modules to form independent memory micro-module stacked modules, and then stack the plurality of independent memory micro-module stacked modules on the substrate 110 by a thermocompression bonding process.

[0083] The thermocompression bonding process of nesting the second conductive bumps and the pads includes:

[0084] First, a protrusion is formed on the pad.

[0085] Specifically, as Figure 9 shown, a photoresist layer is coated on the pad 134, and the pad 134 is patterned using photolithography and etching processes to form a protrusion (not marked in the figure) in the central region of the pad 134. The size of the protrusion is generally 3 um - 5 um, and the height of the protrusion is below 5 um. In this embodiment, the protrusion is in the shape of a square prism.

[0086] Second, through a thermocompression bonding process, press the protrusion into the second conductive bump.

[0087] Specifically, as Figure 9 shown, there are protrusions (not marked in the figure) formed on the pad 134. Through the thermocompression bonding process, the protrusions are pressed into the second conductive bump 127.

[0088] Exemplarily, the melting point of the first conductive bump 126 is greater than that of the second conductive bump 127, and the temperature of the thermocompression bonding process is less than the melting point of the second conductive bump 127.

[0089] Specifically, the temperature of the thermocompression bonding process is lower than the melting point of the second conductive bump 127. In this embodiment, since the second conductive bump is a tin bump, it is generally set to 180°C to 210°C. This temperature can ensure the low modulus of the tin bump, enable the protrusions to be embedded in the tin bump, fix the first memory chip 120 and the second memory chip 130, and at the same time, the shape of the tin bump remains basically unchanged.

[0090] It should be noted that, as Figure 10 shown, the thickness of the second memory chip 130 in the topmost memory micro-module 150 is thicker than that of other second memory chips 130, which plays a protective role for the entire package structure.

[0091] S160. Through the reflow soldering process, the stacked multiple memory micro-modules and the substrate are reflow soldered.

[0092] Exemplarily, the step of reflow soldering the stacked multiple memory micro-modules and the substrate through the reflow soldering process includes:

[0093] In an acidic gas environment, through the reflow soldering process, the stacked multiple memory micro-modules and the substrate are reflow soldered.

[0094] Specifically, as Figure 10 shown, the stacked multiple memory micro-modules 150 and the substrate 110 are put into an acidic reflow furnace for reflow. In an acidic gas environment, without melting, the oxides of the second conductive bump 127 can be completely removed, that is, the oxides of the tin bump are removed. Since the second conductive bump 127 and the pad 134 have been soldered, during the reflow in the acidic reflow furnace, the deformation of the second conductive bump 127, that is, the tin bump, is relatively small and will not become shorter. During the entire reflow process, under the action of the upper and lower surface tensions, the second conductive bump 127 can basically maintain its columnar shape unchanged, which can reduce the pitch of the tin bumps and achieve a connection with a center pitch of less than 20 um.

[0095] It should be noted that the acidic gas can be carbon dioxide, chlorine, hydrogen sulfide, hydrogen chloride, sulfur dioxide, etc., and no specific limitation is made in this embodiment.

[0096] S170. Form a plastic encapsulation layer that encapsulates the multiple memory micro-modules and the substrate.

[0097] Specifically, as Figure 11 shown, use plastic encapsulation material to encapsulate the multiple memory micro-modules 150 and the substrate 110 to form a plastic encapsulation layer 160. The plastic encapsulation method can be film layer vacuum lamination or traditional plastic encapsulation process, and no specific limitation is made in this embodiment. After the encapsulation is completed, cutting is performed to form the final independent multi-layer stacked high-bandwidth memory packaging structure.

[0098] Exemplarily, plastic encapsulation material is filled between each of the memory micro-modules and between the micro-module and the substrate.

[0099] Specifically, as Figure 11 shown, when encapsulating the multiple memory micro-modules 150 and the substrate 110, plastic encapsulation material is also filled between each memory micro-module 150 and between the memory micro-module 150 and the substrate 110. That is to say, the plastic encapsulation material encapsulates the multiple first conductive bumps 126 and the multiple second conductive bumps 127, playing a protective role for the multiple first conductive bumps 126 and the multiple second conductive bumps 127 to prevent short circuits between the first conductive bumps 126 and the second conductive bumps 127. Since the plastic encapsulation material is relatively low in price compared to non-conductive glue, it has the advantage of low production cost.

[0100] Exemplarily, as Figure 12 shown, after forming the plastic encapsulation layer 160, a plurality of solder balls 170 are formed on the surface of the substrate 110 facing away from the memory micro-module 150, and the packaging structure is connected to the outside through the plurality of solder balls 170.

[0101] The wafer-level hybrid bonding of the first memory chip and the second memory chip utilizes the production efficiency of wafer-level hybrid bonding, and at the same time reduces the yield loss problem during multi-layer wafer-level hybrid bonding. The positions of the defective chips on the two wafers are different in the wafers. When the two wafers are stacked on top of each other, it will cause additional losses. The more the number of wafer-level stacking layers, the greater the yield loss. Two-layer stacking can preferably use similar wafers to minimize this yield loss. In this embodiment, in order to minimize the yield loss during the wafer-level stacking process, the first memory chip 120 and the second memory chip 130 are of the same type.

[0102] The first memory chip and the second memory chip are electrically connected through wafer-level hybrid bonding, enabling a smaller pitch (below 10um). At the same time, as a memory micro-module, the back surface of the first memory chip can be thinned to the limit. Such a dual-chip combination significantly reduces the thickness compared to the same through-silicon via chips of current conventional high-bandwidth memories. Moreover, it also reduces the number and height of bumps, allowing for a significant increase in the number of chip layers and capacity.

[0103] The packaging method of the multi-layer stacked high-bandwidth memory of the present invention forms a dual-chip electrical connection through wafer-level hybrid bonding to constitute a memory micro-module, achieving a decrease in bonding height, a significant increase in the number of chip layers, an increase in capacity, and enabling ultra-multi-layer chip stacking. At the same time, it improves production efficiency and minimizes the yield loss of wafer-level stacking. At the position corresponding to the conductive vias on the surface of the first memory chip facing the substrate, a first conductive bump and a second conductive bump are sequentially formed. At the position corresponding to the conductive vias on the surface of the second memory chip facing away from the substrate, pads are formed. Through a thermocompression bonding process, the second conductive bump and the pads are nested to stack multiple memory micro-modules on the substrate in sequence. Through a reflow soldering process, the stacked multiple memory micro-modules and the substrate are reflow soldered. The present invention nests the second conductive bump and the pads through two-step soldering processes, which can reduce the deformation of the second conductive bump, thereby reducing the pitch of the second conductive bump and achieving ultra-fine pitch interconnection.

[0104] As Figure 11 and Figure 12 shown, another aspect of the present invention provides a multi-layer stacked high-bandwidth memory packaging structure 100, including: a substrate 110, multiple memory micro-modules 150, and a molding layer 160. The multiple memory micro-modules 150 are stacked on the substrate 110 in an insulated manner; wherein,

[0105] Each memory micro-module 150 includes a first memory chip 120 and a second memory chip 130. Each first memory chip 120 is hybrid-bonded to the corresponding second memory chip 130 through a hybrid bonding structure. Among them, both the first memory chip 120 and the second memory chip 130 are provided with multiple conductive vias 140; and,

[0106] At the position corresponding to the conductive vias 140 on the surface of the first memory chip 120 facing the substrate 110, a first conductive bump 126 and a second conductive bump 127 are sequentially provided. At the position corresponding to the conductive vias 140 on the surface of the second memory chip 130 facing away from the substrate 110, pads 134 are provided. The second conductive bump 127 and the pads 134 are nested and connected.

[0107] As Figure 12As shown, in this embodiment, the first conductive bump 126 can be a copper bump, and the second conductive bump 127 can be a tin bump. Further preferably, as Figure 3 shown, the second conductive bump 127 has a columnar structure, that is, the tin bump has a columnar structure, which can be a cylindrical structure or a prismatic structure. The original form of the second conductive bump 127 is a columnar structure, different from the spherical shape of the traditional conductive bump, which can reduce the lateral width under the same volume. In this embodiment, the pad 134 is a copper pad, and the pad 134 has a cylindrical structure.

[0108] As Figure 11 shown, the encapsulation layer 160 wraps a plurality of memory micro-modules 150 and the substrate 110.

[0109] Exemplarily, as Figure 9 shown, the hybrid bonding structure includes a first passivation layer 121 and a first metal pad 122 disposed on the surface of the first memory chip 120 facing the second memory chip 130, and a second passivation layer 131 and a second metal pad 132 disposed on the surface of the second memory chip 130 facing the first memory chip 120; in this embodiment, the materials of the first passivation layer 121 and the second passivation layer 131 can be silicon dioxide passivation layers, and both the first metal pad 122 and the second metal pad 132 can be copper pads.

[0110] The first passivation layer 121 in the first memory chip 120 is bonded to the second passivation layer 131 in the corresponding second memory chip 130, and the first metal pad 122 in the first memory chip 120 is bonded and connected to the second metal pad 132 in the corresponding second memory chip 130.

[0111] Exemplarily, as Figure 12 shown, a protrusion (not marked in the figure) is provided on the side of the pad 134 facing the second conductive bump 127, and a groove (not marked in the figure) is provided on the side of the second conductive bump 127 facing the pad 134, and the protrusion is inserted into the groove. The size of the protrusion is generally 3 um - 5 um, and the height of the protrusion is below 5 um. In this embodiment, the protrusion is a square prism, that is, the cross-section is a square.

[0112] Exemplarily, as Figure 12 shown, the first memory chip 120 is disposed close to the substrate 110, the second memory chip 130 is disposed away from the substrate 110, and moreover, the thickness of the first memory chip 120 is less than the thickness of the second memory chip 130. Further preferably, the thickness of the first memory chip 120 is 10 um - 20 um, the thickness of the second memory chip 130 is 40 um - 50 um, and the back surface of the first memory chip 120 can be thinned to the limit, that is, it can be thinned to only retain the circuit layer.

[0113] Exemplarily, as Figure 12 shown, when encapsulating multiple memory micro-modules 150 and the substrate 110, inter-page filling encapsulant is performed between each memory micro-module 150 and between the memory micro-module 150 and the substrate 110. That is to say, the encapsulant wraps multiple first conductive bumps 126 and multiple second conductive bumps 127, playing a protective role for the multiple first conductive bumps 126 and the multiple second conductive bumps 127 to prevent short circuits between the first conductive bumps 126 and the second conductive bumps 127. Since the encapsulant has a lower price compared to non-conductive glue, it has the advantage of low production cost.

[0114] As Figure 12 shown, a third passivation layer 123 and a dielectric layer 124 are further provided on the surface of the first memory chip 120 facing the substrate 110. It should be noted that the material of the third passivation layer 123 can be silicon dioxide or silicon nitride, and the material of the dielectric layer 124 can be polyimide (PI), polybenzoxazole (PBO), etc. In this embodiment, the material of the dielectric layer 124 is polyimide (PI). The coating method is usually wafer spin coating, which is not specifically limited in this embodiment.

[0115] As Figure 12 shown, the packaging structure further includes multiple solder balls 170, and the multiple solder balls 170 are connected to the outside.

[0116] For the packaging structure of the multi-layer stacked high-bandwidth memory of the present invention, the first memory chip and the second memory chip form a memory micro-module, and multiple memory micro-modules are stacked on the substrate in an insulating manner. The number of chip layers in this packaging structure can be greatly increased, the capacity is increased, and the packaging height is reduced to the greatest extent. In the packaging structure of the present invention, the second conductive bumps on the first memory chip are nested and connected with the pads on the second memory chip, and the pads and the second conductive bumps are nested and connected, which can reduce the deformation of the second conductive bumps, reduce the pitch of the second conductive bumps, and achieve interconnection with a center pitch of less than 20 um.

[0117] It can be understood that the above embodiments are merely exemplary embodiments adopted to illustrate the principle of the present invention, but the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also regarded as the protection scope of the present invention.

Claims

1. A packaging method for a multi-layer stacked high-bandwidth memory, characterized in that, The method includes: providing a substrate and multiple groups of memory chips respectively, each group of the memory chips including a first memory chip and a second memory chip; wherein, both the first memory chip and the second memory chip are provided with a plurality of conductive vias; hybrid bonding the first memory chip and the second memory chip in each group of the memory chips respectively to form a plurality of memory micromodules; forming a first conductive bump and a second conductive bump in sequence at positions corresponding to the conductive vias on the surface of the first memory chip facing the substrate; forming pads at positions corresponding to the conductive vias on the surface of the second memory chip facing away from the substrate; nesting the second conductive bump and the pad through a thermocompression bonding process to reduce the deformation of the second conductive bump, realizing ultra-fine pitch interconnection, and then insulating and stacking the plurality of memory micromodules on the substrate in sequence; wherein, the specific process of nesting the second conductive bump and the pad includes: forming a protrusion on the pad; pressing the protrusion into the second conductive bump through a thermocompression bonding process; wherein, the melting point of the first conductive bump is greater than that of the second conductive bump, and the temperature of the thermocompression bonding process is less than the melting point of the second conductive bump; performing reflow soldering on the stacked plurality of memory micromodules and the substrate through a reflow soldering process in an acidic gas environment; forming a molding layer, and the molding layer wraps the plurality of memory micromodules and the substrate.

2. The method according to claim 1, wherein The surface of the first memory chip facing the second memory chip is provided with a first passivation layer and a first metal pad, and the surface of the second memory chip facing the first memory chip is provided with a second passivation layer and a second metal pad; the hybrid bonding of the first memory chip and the second memory chip in each group of the memory chips respectively to form a plurality of memory micromodules includes: bonding the first passivation layer in the first memory chip with the second passivation layer in the corresponding second memory chip; and, bonding the first metal pad in the first memory chip with the second metal pad in the corresponding second memory chip.

3. The method according to claim 2, characterized in that, The forming of the first conductive bump and the second conductive bump in sequence at positions corresponding to the conductive vias on the surface of the first memory chip facing the substrate includes: forming a third passivation layer and a dielectric layer in sequence on the surface of the first memory chip facing the substrate; forming a photoresist layer on the dielectric layer, and patterning the photoresist layer to form a plurality of openings, and the plurality of openings respectively correspond to the plurality of conductive vias; forming the first conductive bump and the second conductive bump in sequence at the plurality of openings; removing the photoresist layer.

4. The method according to claim 3, characterized in that, The surface of the second conductive bump protrudes from the surface of the photoresist layer; before removing the photoresist layer, the method further includes: grinding the second conductive bump so that the surface of the second conductive bump is flush with the surface of the photoresist layer.

5. The method according to any one of claims 1 to 4, characterized in that, An encapsulant is filled between each of the memory micro-modules and between the micro-module and the substrate.

6. The method according to any one of claims 1 to 4, characterized in that In each group of the memory chips, the first memory chip is disposed close to the substrate, the second memory chip is disposed away from the substrate, and the thickness of the first memory chip is less than the thickness of the second memory chip.

7. A multi-layer stacked high-bandwidth memory packaging structure, characterized in that, It is formed by encapsulating using the encapsulation method of the multi-layer stacked high-bandwidth memory according to any one of claims 1 to 6. The encapsulation structure includes: a substrate, a plurality of memory micro-modules, and an encapsulation layer. The plurality of memory micro-modules are stacked on the substrate in an insulating manner; wherein, Each of the memory micro-modules includes a first memory chip and a second memory chip. Each of the first memory chips is hybrid-bonded to the corresponding second memory chip through a hybrid bonding structure. Among them, the first memory chip and the second memory chip are both provided with a plurality of conductive vias; and, At the surface of the first memory chip facing the substrate corresponding to the conductive via, a first conductive bump and a second conductive bump are sequentially provided. A pad is provided at the surface of the second memory chip facing away from the substrate corresponding to the conductive via. The second conductive bump and the pad are nested and connected; wherein, A protrusion is provided on one side of the pad facing the second conductive bump, and a groove is provided on one side of the second conductive bump facing the pad. The protrusion is inserted into the groove; The encapsulation layer wraps the plurality of memory micro-modules and the substrate.

8. The encapsulation structure according to claim 7, wherein The hybrid bonding structure includes a first passivation layer and a first metal pad provided on the surface of the first memory chip facing the second memory chip, and a second passivation layer and a second metal pad provided on the surface of the second memory chip facing the first memory chip; The first passivation layer in the first memory chip is bonded to the second passivation layer in the corresponding second memory chip, and the first metal pad in the first memory chip is bonded to the second metal pad in the corresponding second memory chip.

9. The encapsulation structure according to claim 8, characterized in that The second conductive bump has a columnar structure.

10. The encapsulation structure according to claim 9, characterized in that The first memory chip is disposed close to the substrate, the second memory chip is disposed away from the substrate, and the thickness of the first memory chip is less than the thickness of the second memory chip.

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